Syntax errors fixed... tx Vivado!

cntr.v

 module cntr (
   input clk, rst, en, par,
-  output [3:0] q,
+  output [3:0] q
 );
 
 reg [3:0] cntr;

data.v

 module data(
   input clk, rst, en,
-  output q, empty,
+  output q, empty
 );
 
   reg [41:0] data;
@@ -15,7 +15,7 @@ module data(
         7'b1001101, // M
         7'b1001101, // M
         7'b1000010, // B
-        7'b1010100, // T - LSB
+        7'b1010100 // T - LSB
       };
     end
 
@@ -25,6 +25,6 @@ module data(
   end
 
   assign q = data[0]; // LSB of data
-  assign empty (cntr >= 42) ? 1 : 0;
+  assign empty = (cntr >= 42) ? 1 : 0;
 
 endmodule

debouncer.v

 module debouncer(
 input clk, rst, din,
-output q,
+output q
 );
 
 reg state;
@@ -21,5 +21,5 @@ always @ (posedge clk) begin
 
 end
 
-assign q = (~state && din)
+assign q = (~state && din);
 endmodule

parity.v

 module parity(
   input clk, rst, din,
-  output q,
+  output q
 );
 
 reg t;

rategen.v

 // SYSCLK is 50MHz
 module rategen(
   input clk, rst, start, sw_speed, sw_par,
-  output iclk,
+  output iclk
 );
 
   reg [15:0] cntr;

uartop.v

@@ -5,11 +5,11 @@ module uartop(
   input sw7, // parity on/off
 
   output txd,
-  output rts,
+  output rts
 );
 
-  wire iclk, // Internal CLK for correct Baud Rate
-  wire starten, // Main enabler
+  wire iclk; // Internal CLK for correct Baud Rate
+  wire starten; // Main enabler
 
   rategen rategen(
     .clk(clk),

udata.v

@@ -2,11 +2,11 @@ module udata(
   input clk, rst, en,
   input [3:0] sel,
   input [15:0] din,
-  output q,
+  output q
 );
 
   wire out;
   assign out = din[sel];
 
-  assign q (rst || !en) ? 1 : (out & clk);
+  assign q = (rst || !en) ? 1 : (out & clk);
 endmodule