From 19669748f064f265639fa54972fb4647e5dfe8d5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tam=C3=A1si=20Benjamin?= <halftome@yahoo.com>
Date: Thu, 16 Oct 2014 00:56:44 +0200
Subject: [PATCH] Syntax errors fixed... tx Vivado!

---
 cntr.v      | 4 ++--
 data.v      | 6 +++---
 debouncer.v | 4 ++--
 parity.v    | 2 +-
 rategen.v   | 2 +-
 uartop.v    | 6 +++---
 udata.v     | 4 ++--
 7 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/cntr.v b/cntr.v
index 4535726..5608338 100644
--- a/cntr.v
+++ b/cntr.v
@@ -1,6 +1,6 @@
-module cntr(
+module cntr (
   input clk, rst, en, par,
-  output [3:0] q,
+  output [3:0] q
 );
 
 reg [3:0] cntr;
diff --git a/data.v b/data.v
index 238e56b..c82a7eb 100644
--- a/data.v
+++ b/data.v
@@ -1,6 +1,6 @@
 module data(
   input clk, rst, en,
-  output q, empty,
+  output q, empty
 );
 
   reg [41:0] data;
@@ -15,7 +15,7 @@ module data(
         7'b1001101, // M
         7'b1001101, // M
         7'b1000010, // B
-        7'b1010100, // T - LSB
+        7'b1010100 // T - LSB
       };
     end
 
@@ -25,6 +25,6 @@ module data(
   end
 
   assign q = data[0]; // LSB of data
-  assign empty (cntr >= 42) ? 1 : 0;
+  assign empty = (cntr >= 42) ? 1 : 0;
 
 endmodule
diff --git a/debouncer.v b/debouncer.v
index 3b1cf00..fd8d0a6 100644
--- a/debouncer.v
+++ b/debouncer.v
@@ -1,6 +1,6 @@
 module debouncer(
 input clk, rst, din,
-output q,
+output q
 );
 
 reg state;
@@ -21,5 +21,5 @@ always @ (posedge clk) begin
 
 end
 
-assign q = (~state && din)
+assign q = (~state && din);
 endmodule
diff --git a/parity.v b/parity.v
index b337867..ff2ec47 100644
--- a/parity.v
+++ b/parity.v
@@ -1,6 +1,6 @@
 module parity(
   input clk, rst, din,
-  output q,
+  output q
 );
 
 reg t;
diff --git a/rategen.v b/rategen.v
index 587b41b..5c09e9d 100644
--- a/rategen.v
+++ b/rategen.v
@@ -1,7 +1,7 @@
 // SYSCLK is 50MHz
 module rategen(
   input clk, rst, start, sw_speed, sw_par,
-  output iclk,
+  output iclk
 );
 
   reg [15:0] cntr;
diff --git a/uartop.v b/uartop.v
index 6fa2bb6..3119794 100644
--- a/uartop.v
+++ b/uartop.v
@@ -5,11 +5,11 @@ module uartop(
   input sw7, // parity on/off
 
   output txd,
-  output rts,
+  output rts
 );
 
-  wire iclk, // Internal CLK for correct Baud Rate
-  wire starten, // Main enabler
+  wire iclk; // Internal CLK for correct Baud Rate
+  wire starten; // Main enabler
 
   rategen rategen(
     .clk(clk),
diff --git a/udata.v b/udata.v
index 7f00a1e..a552ea6 100644
--- a/udata.v
+++ b/udata.v
@@ -2,11 +2,11 @@ module udata(
   input clk, rst, en,
   input [3:0] sel,
   input [15:0] din,
-  output q,
+  output q
 );
 
   wire out;
   assign out = din[sel];
 
-  assign q (rst || !en) ? 1 : (out & clk);
+  assign q = (rst || !en) ? 1 : (out & clk);
 endmodule
-- 
GitLab