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Uart Transmitter FPGA
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Tamási Benjamin
Uart Transmitter FPGA
Commits
e120a32e
Commit
e120a32e
authored
10 years ago
by
Tamási Benjamin
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12ab5f4d
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uartop.v
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-0
35 additions, 0 deletions
uartop.v
udata.v
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-0
12 additions, 0 deletions
udata.v
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and
0 deletions
uartop.v
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+
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−
0
View file @
e120a32e
module
uartop
(
input
clk
,
rst
,
input
btn1
,
// start/stop
input
sw6
,
// baud rate fast/slow
input
sw7
,
// parity on/off
output
txd
,
output
rts
,
);
wire
iclk
,
// Internal CLK for correct Baud Rate
wire
starten
,
// Main enabler
rategen
rategen
(
.
clk
(
clk
),
.
rst
(
rst
),
.
start
(
btn1
),
.
sw_speed
(
sw6
),
.
sw_par
(
sw7
),
.
iclk
(
iclk
),
);
debouncer
debouncer
(
.
clk
(
clk
),
.
rst
(
rst
),
.
din
(
btn1
),
.
q
(
starten
),
);
always
@
(
posedge
clk
)
begin
end
endmodule
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udata.v
0 → 100644
+
12
−
0
View file @
e120a32e
module
udata
(
input
clk
,
rst
,
en
,
input
[
3
:
0
]
sel
,
input
[
15
:
0
]
din
,
output
q
,
);
wire
out
;
assign
out
=
din
[
sel
];
assign
q
(
rst
||
!
en
)
?
1
:
(
out
&
clk
);
endmodule
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