Skip to content
Snippets Groups Projects
Commit e120a32e authored by Tamási Benjamin's avatar Tamási Benjamin
Browse files

started top module

parent 12ab5f4d
No related branches found
No related tags found
No related merge requests found
uartop.v 0 → 100644
module uartop(
input clk, rst,
input btn1, // start/stop
input sw6, // baud rate fast/slow
input sw7, // parity on/off
output txd,
output rts,
);
wire iclk, // Internal CLK for correct Baud Rate
wire starten, // Main enabler
rategen rategen(
.clk(clk),
.rst(rst),
.start(btn1),
.sw_speed(sw6),
.sw_par(sw7),
.iclk(iclk),
);
debouncer debouncer(
.clk(clk),
.rst(rst),
.din(btn1),
.q(starten),
);
always @ (posedge clk) begin
end
endmodule
udata.v 0 → 100644
module udata(
input clk, rst, en,
input [3:0] sel,
input [15:0] din,
output q,
);
wire out;
assign out = din[sel];
assign q (rst || !en) ? 1 : (out & clk);
endmodule
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment