diff --git a/cntr.v b/cntr.v
index 45357267e0bb245ef935561505fe251d24601855..5608338799399d27c8f757f9d057de9d7a04348d 100644
--- a/cntr.v
+++ b/cntr.v
@@ -1,6 +1,6 @@
-module cntr(
+module cntr (
   input clk, rst, en, par,
-  output [3:0] q,
+  output [3:0] q
 );
 
 reg [3:0] cntr;
diff --git a/data.v b/data.v
index 238e56bf5e59fd50d56cb01a1a9f363f766d602d..c82a7eb626a542ae238b50d0ef9060f8df111a3f 100644
--- a/data.v
+++ b/data.v
@@ -1,6 +1,6 @@
 module data(
   input clk, rst, en,
-  output q, empty,
+  output q, empty
 );
 
   reg [41:0] data;
@@ -15,7 +15,7 @@ module data(
         7'b1001101, // M
         7'b1001101, // M
         7'b1000010, // B
-        7'b1010100, // T - LSB
+        7'b1010100 // T - LSB
       };
     end
 
@@ -25,6 +25,6 @@ module data(
   end
 
   assign q = data[0]; // LSB of data
-  assign empty (cntr >= 42) ? 1 : 0;
+  assign empty = (cntr >= 42) ? 1 : 0;
 
 endmodule
diff --git a/debouncer.v b/debouncer.v
index 3b1cf005c44324d62958464427a89a2884e09cab..fd8d0a6bb841e4539d54dd0e6b145ef5684c1529 100644
--- a/debouncer.v
+++ b/debouncer.v
@@ -1,6 +1,6 @@
 module debouncer(
 input clk, rst, din,
-output q,
+output q
 );
 
 reg state;
@@ -21,5 +21,5 @@ always @ (posedge clk) begin
 
 end
 
-assign q = (~state && din)
+assign q = (~state && din);
 endmodule
diff --git a/parity.v b/parity.v
index b33786737043f478d20e6215ecb54b646adf3bc2..ff2ec474cebb40ab153b83ab0e725fb3b71fb775 100644
--- a/parity.v
+++ b/parity.v
@@ -1,6 +1,6 @@
 module parity(
   input clk, rst, din,
-  output q,
+  output q
 );
 
 reg t;
diff --git a/rategen.v b/rategen.v
index 587b41b076503ee7bda65f584f975eb4c5861a4d..5c09e9daf72e76cde4176c7814955d75377d1b37 100644
--- a/rategen.v
+++ b/rategen.v
@@ -1,7 +1,7 @@
 // SYSCLK is 50MHz
 module rategen(
   input clk, rst, start, sw_speed, sw_par,
-  output iclk,
+  output iclk
 );
 
   reg [15:0] cntr;
diff --git a/uartop.v b/uartop.v
index 6fa2bb65f23af8632695f8c0154740c01463de64..31197947c19b11ecc034ab5ad20e95162fed6f42 100644
--- a/uartop.v
+++ b/uartop.v
@@ -5,11 +5,11 @@ module uartop(
   input sw7, // parity on/off
 
   output txd,
-  output rts,
+  output rts
 );
 
-  wire iclk, // Internal CLK for correct Baud Rate
-  wire starten, // Main enabler
+  wire iclk; // Internal CLK for correct Baud Rate
+  wire starten; // Main enabler
 
   rategen rategen(
     .clk(clk),
diff --git a/udata.v b/udata.v
index 7f00a1e91986844dc8dc31f7a7d2a0a366a11ed9..a552ea6360fe2f37670485ea696ea67e5d11be27 100644
--- a/udata.v
+++ b/udata.v
@@ -2,11 +2,11 @@ module udata(
   input clk, rst, en,
   input [3:0] sel,
   input [15:0] din,
-  output q,
+  output q
 );
 
   wire out;
   assign out = din[sel];
 
-  assign q (rst || !en) ? 1 : (out & clk);
+  assign q = (rst || !en) ? 1 : (out & clk);
 endmodule