Skip to content
Snippets Groups Projects
Commit 9c5d64f2 authored by Tamási Benjamin's avatar Tamási Benjamin
Browse files

Moving into testing stage

parent 19669748
No related branches found
No related tags found
No related merge requests found
module parity(
input clk, rst, din,
input clk, rst, din, en, par,
output q
);
......@@ -7,8 +7,7 @@ reg t;
always @ (posedge clk) begin
if(rst) begin
// t <= 0; // Even parity
t <= 1; // Odd parity
t <= 0;
end
else if(din) begin
......@@ -16,6 +15,6 @@ always @ (posedge clk) begin
end
end
assign q = t;
assign q = (par) ? ~t : t;
endmodule
// SYSCLK is 50MHz
module rategen(
input clk, rst, start, sw_speed, sw_par,
output iclk
output iclk, pulse
);
reg [15:0] cntr;
......@@ -29,9 +29,12 @@ module rategen(
end
end
assign fast = (cntr >= 2604) ? 1 : 0; // 50% pulse width
assign slow = (cntr >= 20833) ? 1 : 0; // 50% pulse width
assign fast = (cntr >= 5208) ? 1 : 0; // pulse width of clk for SYNC
assign slow = (cntr >= 41666) ? 1 : 0; // pulse width of clk for SYNC
assign p_fast = (cntr >= 2704) ? 1 : 0; // pulse width of 50%
assign p_slow = (cntr >= 20833) ? 1 : 0; // pulse width of 50%
assign iclk = (sw_speed) ? fast : slow;
assign pulse = (sw_speed) ? p_fast : p_slow;
endmodule
......@@ -8,8 +8,28 @@ module uartop(
output rts
);
reg outbuf;
reg [6:0] datacntr;
wire iclk; // Internal CLK for correct Baud Rate
wire starten; // Main enabler
wire [3:0] count;
wire mpxen;
wire dout;
wire pulse;
wire parity;
wire uart_data;
wire [15:0] uart_mpx;
wire wordend;
wire [6:0] data_count;
wire eot; // End of transmit
assign uart_mpx[15] = 0; // Start bit
assign uart_mpx[14:8] = dout; // UART DATA 7bit
assign uart_mpx[7] = (sw7) ? parity : 1; // Parity or stop bit
assign uart_mpx[6:0] = 1; // Stop bits
assign mpxen = (count == 0 || (count >= 8 && count <= 10));
rategen rategen(
.clk(clk),
......@@ -18,18 +38,64 @@ module uartop(
.sw_speed(sw6),
.sw_par(sw7),
.iclk(iclk),
.pulse(pulse)
);
debouncer debouncer(
.clk(clk),
.rst(rst),
.din(btn1),
.q(starten),
.din(btn1 || eot),
.q(starten)
);
cntr cntr(
.clk(clk),
.rst(rst),
.en(starten && iclk),
.par(sw7),
.q(count)
);
always @ (posedge clk) begin
data data(
.clk(clk),
.rst(rst),
.en(mpxen && iclk && starten),
.q(dout)
);
parity parity(
.clk(clk),
.rst(rst || wordend),
.din(dout),
.en(iclk),
.par(1), // Odd Parity
.q(parity)
);
udata udata(
.clk(clk),
.rst(rst),
.en(iclk && starten),
.sel(count),
.din(uart_mpx),
.q(uart_data)
);
always @ (posedge clk) begin
if(rst) begin
outbuf <= 0;
datacntr <= 0;
end
else if(datacntr == 41 && mpxen) begin
datacntr <= 0;
end
else if(mpxen) begin
datacntr <= datacntr + 1;
end
end
assign data_count = datacntr;
assign wordend = (data_count%6 == 0);
assign eot = (data_count == 42);
endmodule
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment