From 9c5d64f23fee50a757f055045ea629213eee1ae0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tam=C3=A1si=20Benjamin?= <halftome@yahoo.com>
Date: Thu, 16 Oct 2014 12:45:36 +0200
Subject: [PATCH] Moving into testing stage
---
parity.v | 29 +++++++++++-----------
rategen.v | 9 ++++---
uartop.v | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++---
3 files changed, 89 insertions(+), 21 deletions(-)
diff --git a/parity.v b/parity.v
index ff2ec47..e6f9fbe 100644
--- a/parity.v
+++ b/parity.v
@@ -1,21 +1,20 @@
module parity(
- input clk, rst, din,
+ input clk, rst, din, en, par,
output q
);
-reg t;
-
-always @ (posedge clk) begin
- if(rst) begin
-// t <= 0; // Even parity
- t <= 1; // Odd parity
- end
-
- else if(din) begin
- t <= ~t;
- end
-end
-
-assign q = t;
+ reg t;
+
+ always @ (posedge clk) begin
+ if(rst) begin
+ t <= 0;
+ end
+
+ else if(din) begin
+ t <= ~t;
+ end
+ end
+
+ assign q = (par) ? ~t : t;
endmodule
diff --git a/rategen.v b/rategen.v
index 5c09e9d..a03b78c 100644
--- a/rategen.v
+++ b/rategen.v
@@ -1,7 +1,7 @@
// SYSCLK is 50MHz
module rategen(
input clk, rst, start, sw_speed, sw_par,
- output iclk
+ output iclk, pulse
);
reg [15:0] cntr;
@@ -29,9 +29,12 @@ module rategen(
end
end
-assign fast = (cntr >= 2604) ? 1 : 0; // 50% pulse width
-assign slow = (cntr >= 20833) ? 1 : 0; // 50% pulse width
+assign fast = (cntr >= 5208) ? 1 : 0; // pulse width of clk for SYNC
+assign slow = (cntr >= 41666) ? 1 : 0; // pulse width of clk for SYNC
+assign p_fast = (cntr >= 2704) ? 1 : 0; // pulse width of 50%
+assign p_slow = (cntr >= 20833) ? 1 : 0; // pulse width of 50%
assign iclk = (sw_speed) ? fast : slow;
+assign pulse = (sw_speed) ? p_fast : p_slow;
endmodule
diff --git a/uartop.v b/uartop.v
index 3119794..46c1e96 100644
--- a/uartop.v
+++ b/uartop.v
@@ -8,8 +8,28 @@ module uartop(
output rts
);
+ reg outbuf;
+ reg [6:0] datacntr;
+
wire iclk; // Internal CLK for correct Baud Rate
wire starten; // Main enabler
+ wire [3:0] count;
+ wire mpxen;
+ wire dout;
+ wire pulse;
+ wire parity;
+ wire uart_data;
+ wire [15:0] uart_mpx;
+ wire wordend;
+ wire [6:0] data_count;
+ wire eot; // End of transmit
+
+ assign uart_mpx[15] = 0; // Start bit
+ assign uart_mpx[14:8] = dout; // UART DATA 7bit
+ assign uart_mpx[7] = (sw7) ? parity : 1; // Parity or stop bit
+ assign uart_mpx[6:0] = 1; // Stop bits
+
+ assign mpxen = (count == 0 || (count >= 8 && count <= 10));
rategen rategen(
.clk(clk),
@@ -18,18 +38,64 @@ module uartop(
.sw_speed(sw6),
.sw_par(sw7),
.iclk(iclk),
+ .pulse(pulse)
);
debouncer debouncer(
.clk(clk),
.rst(rst),
- .din(btn1),
- .q(starten),
+ .din(btn1 || eot),
+ .q(starten)
+ );
+
+ cntr cntr(
+ .clk(clk),
+ .rst(rst),
+ .en(starten && iclk),
+ .par(sw7),
+ .q(count)
);
+ data data(
+ .clk(clk),
+ .rst(rst),
+ .en(mpxen && iclk && starten),
+ .q(dout)
+ );
+
+ parity parity(
+ .clk(clk),
+ .rst(rst || wordend),
+ .din(dout),
+ .en(iclk),
+ .par(1), // Odd Parity
+ .q(parity)
+ );
+
+ udata udata(
+ .clk(clk),
+ .rst(rst),
+ .en(iclk && starten),
+ .sel(count),
+ .din(uart_mpx),
+ .q(uart_data)
+ );
always @ (posedge clk) begin
-
+ if(rst) begin
+ outbuf <= 0;
+ datacntr <= 0;
+ end
+ else if(datacntr == 41 && mpxen) begin
+ datacntr <= 0;
+ end
+ else if(mpxen) begin
+ datacntr <= datacntr + 1;
+ end
end
+assign data_count = datacntr;
+assign wordend = (data_count%6 == 0);
+assign eot = (data_count == 42);
+
endmodule
--
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