Skip to content
Snippets Groups Projects
Commit 12ab5f4d authored by Tamási Benjamin's avatar Tamási Benjamin
Browse files

counter, debouncer, parity

parent 6e4aea68
Branches
No related tags found
No related merge requests found
cntr.v 0 → 100644
module cntr(
input clk, rst, en, par,
output [3:0] q,
);
reg [3:0] cntr;
always @ (posedge clk) begin
if(rst) begin
cntr <= 0;
end
else if(en) begin
if(par) begin
if(cntr >= 9) begin
cntr <= 0;
end
else begin
cntr <= cntr + 1;
end
end
else begin
if(cntr >= 8) begin
cntr <= 0;
end
else begin
cntr <= cntr + 1;
end
end
end
end
assign q = cntr;
endmodule
module debouncer(
input clk, rst, din,
output q,
);
reg state;
always @ (posedge clk) begin
if(rst) begin
state <= 0;
end
else begin
if(din) begin
state <= 1;
end
else begin
state <= 0;
end
end
end
assign q = (~state && din)
endmodule
parity.v 0 → 100644
module parity(
input clk, rst, din,
output q,
);
reg t;
always @ (posedge clk) begin
if(rst) begin
// t <= 0; // Even parity
t <= 1; // Odd parity
end
else if(din) begin
t <= ~t;
end
end
assign q = t;
endmodule
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment