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Uart Transmitter FPGA
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Tamási Benjamin
Uart Transmitter FPGA
Commits
12ab5f4d
Commit
12ab5f4d
authored
Oct 15, 2014
by
Tamási Benjamin
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counter, debouncer, parity
parent
6e4aea68
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cntr.v
+37
-0
37 additions, 0 deletions
cntr.v
debouncer.v
+25
-0
25 additions, 0 deletions
debouncer.v
parity.v
+21
-0
21 additions, 0 deletions
parity.v
with
83 additions
and
0 deletions
cntr.v
0 → 100644
+
37
−
0
View file @
12ab5f4d
module
cntr
(
input
clk
,
rst
,
en
,
par
,
output
[
3
:
0
]
q
,
);
reg
[
3
:
0
]
cntr
;
always
@
(
posedge
clk
)
begin
if
(
rst
)
begin
cntr
<=
0
;
end
else
if
(
en
)
begin
if
(
par
)
begin
if
(
cntr
>=
9
)
begin
cntr
<=
0
;
end
else
begin
cntr
<=
cntr
+
1
;
end
end
else
begin
if
(
cntr
>=
8
)
begin
cntr
<=
0
;
end
else
begin
cntr
<=
cntr
+
1
;
end
end
end
end
assign
q
=
cntr
;
endmodule
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debouncer.v
0 → 100644
+
25
−
0
View file @
12ab5f4d
module
debouncer
(
input
clk
,
rst
,
din
,
output
q
,
);
reg
state
;
always
@
(
posedge
clk
)
begin
if
(
rst
)
begin
state
<=
0
;
end
else
begin
if
(
din
)
begin
state
<=
1
;
end
else
begin
state
<=
0
;
end
end
end
assign
q
=
(
~
state
&&
din
)
endmodule
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parity.v
0 → 100644
+
21
−
0
View file @
12ab5f4d
module
parity
(
input
clk
,
rst
,
din
,
output
q
,
);
reg
t
;
always
@
(
posedge
clk
)
begin
if
(
rst
)
begin
// t <= 0; // Even parity
t
<=
1
;
// Odd parity
end
else
if
(
din
)
begin
t
<=
~
t
;
end
end
assign
q
=
t
;
endmodule
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