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Uart Transmitter FPGA
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Tamási Benjamin
Uart Transmitter FPGA
Commits
6e4aea68
Commit
6e4aea68
authored
Oct 15, 2014
by
Tamási Benjamin
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Rategen and data
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data.v
+30
-0
30 additions, 0 deletions
data.v
rategen.v
+37
-0
37 additions, 0 deletions
rategen.v
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and
0 deletions
data.v
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+
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−
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6e4aea68
module
data
(
input
clk
,
rst
,
en
,
output
q
,
empty
,
);
reg
[
41
:
0
]
data
;
reg
[
6
:
0
]
cntr
;
always
@
(
posedge
clk
)
begin
if
(
rst
)
begin
cntr
<=
0
;
data
<=
{
7'b0001010
,
// LF - MSB
7'b0001101
,
// CR
7'b1001101
,
// M
7'b1001101
,
// M
7'b1000010
,
// B
7'b1010100
,
// T - LSB
}
;
end
else
if
(
en
)
begin
data
<=
{
0
,
data
[
41
:
1
]
}
;
// Shift -> LSB
end
end
assign
q
=
data
[
0
];
// LSB of data
assign
empty
(
cntr
>=
42
)
?
1
:
0
;
endmodule
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rategen.v
0 → 100644
+
37
−
0
View file @
6e4aea68
// SYSCLK is 50MHz
module
rategen
(
input
clk
,
rst
,
start
,
sw_speed
,
sw_par
,
output
iclk
,
);
reg
[
15
:
0
]
cntr
;
wire
fast
;
wire
slow
;
always
@
(
posedge
clk
)
begin
if
(
rst
)
begin
cntr
<=
0
;
end
else
begin
if
(
sw_speed
)
begin
// Baud rate at 9600
if
(
cntr
>=
5208
)
begin
cntr
<=
0
;
end
end
else
begin
// Baud rate at 1200
if
(
cntr
>=
41666
)
begin
cntr
<=
0
;
end
end
cntr
<=
cntr
+
1
;
end
end
assign
fast
=
(
cntr
>=
2604
)
?
1
:
0
;
// 50% pulse width
assign
slow
=
(
cntr
>=
20833
)
?
1
:
0
;
// 50% pulse width
assign
iclk
=
(
sw_speed
)
?
fast
:
slow
;
endmodule
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