Added test fixture

test.v

+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   13:07:18 10/16/2014
+// Design Name:   uartop
+// Module Name:   /home/halftome/ise_uart/testop.v
+// Project Name:  ise_uart
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: uartop
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module testop;
+
+	// Inputs
+	reg clk;
+	reg rst;
+	reg btn1;
+	reg sw6;
+	reg sw7;
+
+	// Outputs
+	wire txd;
+	wire rts;
+
+	// Instantiate the Unit Under Test (UUT)
+	uartop uut (
+		.clk(clk), 
+		.rst(rst), 
+		.btn1(btn1), 
+		.sw6(sw6), 
+		.sw7(sw7), 
+		.txd(txd), 
+		.rts(rts)
+	);
+
+	initial begin
+		// Initialize Inputs
+		clk = 0;
+		rst = 1;
+		btn1 = 0;
+		sw6 = 1;
+		sw7 = 1;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+        
+		// Add stimulus here
+		rst = 0; // RST finished
+		#50 btn1 = 1; // Button push
+		#50 btn1 = 0; // Button release
+
+	end
+	
+	always #10 clk = ~clk;
+      
+endmodule
+
+