another

uartop.v

@@ -11,6 +11,7 @@ module uartop(
   reg outbuf;
   reg [6:0] datacntr;
   reg main_en;
+  reg eot; // end of transmit
   
   wire iclk; // Internal CLK for correct Baud Rate
   wire starten; // Main enabler
@@ -20,9 +21,7 @@ module uartop(
   wire w_parity;
   wire uart_data;
   wire [15:0] uart_mpx;
-  wire wordend;
   wire [6:0] data_count;
-  wire eot; // End of transmit
   wire dbnc;
   
   assign uart_mpx[0] = 0; // Start bit
@@ -77,9 +76,9 @@ module uartop(
   
   parity parity(
     .clk(clk),
-    .rst(rst || wordend),
+    .rst(rst || ~shiften),
     .din(dout),
-    .en(iclk),
+    .en(iclk && iclk && starten),
     .par(1), // Odd Parity
     .q(w_parity)
   );
@@ -115,9 +114,17 @@ module uartop(
 	 
   end
   
+  always @ (negedge clk) begin
+	if(rst) begin
+		eot <= 0;
+	end
+	else if(data_count == 42) begin
+		eot <= 1;
+	end
+	else eot <= 0;
+  end
+
 assign data_count = datacntr;
-assign wordend = ((data_count%6) == 0);
-assign eot = (data_count == 42);
 assign starten = main_en;
 
 assign txd = outbuf;