Modified makefile to use $(CC) variable, to be more generic.

Makefile

@@ -3,15 +3,16 @@ main_src = src/main.c src/class.c src/nfa.c src/dfa.c src/parse.c src/regex.c
 test_src = src/test.c src/class.c src/nfa.c src/dfa.c src/parse.c src/regex.c
 include_flags = -I include
 flags = -g -Wall -pedantic -g
-compiler = gcc $(flags) $(include_flags)
+compiler = $(CC) $(flags) $(include_flags)
 
-all: main_ spec.pdf
+all: main_
 main_:
 	$(compiler) $(main_src) -o main
 test: test_
 test_:
 	$(compiler) $(test_src) -o test
 	./test
+spec: spec.pdf
 spec.pdf: spec.tex
 	latexmk -pdf spec.tex
 	latexmk -c