diff --git a/.gitignore b/.gitignore
deleted file mode 100644
index d16386367f7cd7dd3c1842c484239e9e82a25efc..0000000000000000000000000000000000000000
--- a/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-build/
\ No newline at end of file
diff --git a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h
deleted file mode 100644
index fb6173f6b3ab7c41f037addaa633cb82a6660b22..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h
+++ /dev/null
@@ -1,10644 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f103xb.h
- * @author MCD Application Team
- * @version V4.2.0
- * @date 31-March-2017
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
- * This file contains all the peripheral register's definitions, bits
- * definitions and memory mapping for STM32F1xx devices.
- *
- * This file contains:
- * - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral�s registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f103xb
- * @{
- */
-
-#ifndef __STM32F103xB_H
-#define __STM32F103xB_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-/**
- * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
- */
-#define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
- #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
-#define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_interrupt_number_definition
- * @{
- */
-
-/**
- * @brief STM32F10x Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
-
-/****** STM32 specific Interrupt Numbers *********************************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
- TAMPER_IRQn = 2, /*!< Tamper Interrupt */
- RTC_IRQn = 3, /*!< RTC global Interrupt */
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */
- RCC_IRQn = 5, /*!< RCC global Interrupt */
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
- DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
- DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
- DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
- DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
- DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
- DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
- DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
- ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
- USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
- USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
- TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
- TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
- TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
- USART1_IRQn = 37, /*!< USART1 global Interrupt */
- USART2_IRQn = 38, /*!< USART2 global Interrupt */
- USART3_IRQn = 39, /*!< USART3 global Interrupt */
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
- USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm3.h"
-#include "system_stm32f1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t SR;
- __IO uint32_t CR1;
- __IO uint32_t CR2;
- __IO uint32_t SMPR1;
- __IO uint32_t SMPR2;
- __IO uint32_t JOFR1;
- __IO uint32_t JOFR2;
- __IO uint32_t JOFR3;
- __IO uint32_t JOFR4;
- __IO uint32_t HTR;
- __IO uint32_t LTR;
- __IO uint32_t SQR1;
- __IO uint32_t SQR2;
- __IO uint32_t SQR3;
- __IO uint32_t JSQR;
- __IO uint32_t JDR1;
- __IO uint32_t JDR2;
- __IO uint32_t JDR3;
- __IO uint32_t JDR4;
- __IO uint32_t DR;
-} ADC_TypeDef;
-
-typedef struct
-{
- __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
- __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
- __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
- uint32_t RESERVED[16];
- __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
-} ADC_Common_TypeDef;
-
-/**
- * @brief Backup Registers
- */
-
-typedef struct
-{
- uint32_t RESERVED0;
- __IO uint32_t DR1;
- __IO uint32_t DR2;
- __IO uint32_t DR3;
- __IO uint32_t DR4;
- __IO uint32_t DR5;
- __IO uint32_t DR6;
- __IO uint32_t DR7;
- __IO uint32_t DR8;
- __IO uint32_t DR9;
- __IO uint32_t DR10;
- __IO uint32_t RTCCR;
- __IO uint32_t CR;
- __IO uint32_t CSR;
-} BKP_TypeDef;
-
-/**
- * @brief Controller Area Network TxMailBox
- */
-
-typedef struct
-{
- __IO uint32_t TIR;
- __IO uint32_t TDTR;
- __IO uint32_t TDLR;
- __IO uint32_t TDHR;
-} CAN_TxMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FIFOMailBox
- */
-
-typedef struct
-{
- __IO uint32_t RIR;
- __IO uint32_t RDTR;
- __IO uint32_t RDLR;
- __IO uint32_t RDHR;
-} CAN_FIFOMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FilterRegister
- */
-
-typedef struct
-{
- __IO uint32_t FR1;
- __IO uint32_t FR2;
-} CAN_FilterRegister_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-
-typedef struct
-{
- __IO uint32_t MCR;
- __IO uint32_t MSR;
- __IO uint32_t TSR;
- __IO uint32_t RF0R;
- __IO uint32_t RF1R;
- __IO uint32_t IER;
- __IO uint32_t ESR;
- __IO uint32_t BTR;
- uint32_t RESERVED0[88];
- CAN_TxMailBox_TypeDef sTxMailBox[3];
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
- uint32_t RESERVED1[12];
- __IO uint32_t FMR;
- __IO uint32_t FM1R;
- uint32_t RESERVED2;
- __IO uint32_t FS1R;
- uint32_t RESERVED3;
- __IO uint32_t FFA1R;
- uint32_t RESERVED4;
- __IO uint32_t FA1R;
- uint32_t RESERVED5[8];
- CAN_FilterRegister_TypeDef sFilterRegister[14];
-} CAN_TypeDef;
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
- uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
-} CRC_TypeDef;
-
-
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE;
- __IO uint32_t CR;
-}DBGMCU_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CCR;
- __IO uint32_t CNDTR;
- __IO uint32_t CPAR;
- __IO uint32_t CMAR;
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t ISR;
- __IO uint32_t IFCR;
-} DMA_TypeDef;
-
-
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
- __IO uint32_t IMR;
- __IO uint32_t EMR;
- __IO uint32_t RTSR;
- __IO uint32_t FTSR;
- __IO uint32_t SWIER;
- __IO uint32_t PR;
-} EXTI_TypeDef;
-
-/**
- * @brief FLASH Registers
- */
-
-typedef struct
-{
- __IO uint32_t ACR;
- __IO uint32_t KEYR;
- __IO uint32_t OPTKEYR;
- __IO uint32_t SR;
- __IO uint32_t CR;
- __IO uint32_t AR;
- __IO uint32_t RESERVED;
- __IO uint32_t OBR;
- __IO uint32_t WRPR;
-} FLASH_TypeDef;
-
-/**
- * @brief Option Bytes Registers
- */
-
-typedef struct
-{
- __IO uint16_t RDP;
- __IO uint16_t USER;
- __IO uint16_t Data0;
- __IO uint16_t Data1;
- __IO uint16_t WRP0;
- __IO uint16_t WRP1;
- __IO uint16_t WRP2;
- __IO uint16_t WRP3;
-} OB_TypeDef;
-
-/**
- * @brief General Purpose I/O
- */
-
-typedef struct
-{
- __IO uint32_t CRL;
- __IO uint32_t CRH;
- __IO uint32_t IDR;
- __IO uint32_t ODR;
- __IO uint32_t BSRR;
- __IO uint32_t BRR;
- __IO uint32_t LCKR;
-} GPIO_TypeDef;
-
-/**
- * @brief Alternate Function I/O
- */
-
-typedef struct
-{
- __IO uint32_t EVCR;
- __IO uint32_t MAPR;
- __IO uint32_t EXTICR[4];
- uint32_t RESERVED0;
- __IO uint32_t MAPR2;
-} AFIO_TypeDef;
-/**
- * @brief Inter Integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1;
- __IO uint32_t CR2;
- __IO uint32_t OAR1;
- __IO uint32_t OAR2;
- __IO uint32_t DR;
- __IO uint32_t SR1;
- __IO uint32_t SR2;
- __IO uint32_t CCR;
- __IO uint32_t TRISE;
-} I2C_TypeDef;
-
-/**
- * @brief Independent WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
- __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
- __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t CSR;
-} PWR_TypeDef;
-
-/**
- * @brief Reset and Clock Control
- */
-
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t CFGR;
- __IO uint32_t CIR;
- __IO uint32_t APB2RSTR;
- __IO uint32_t APB1RSTR;
- __IO uint32_t AHBENR;
- __IO uint32_t APB2ENR;
- __IO uint32_t APB1ENR;
- __IO uint32_t BDCR;
- __IO uint32_t CSR;
-
-
-} RCC_TypeDef;
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint32_t CRH;
- __IO uint32_t CRL;
- __IO uint32_t PRLH;
- __IO uint32_t PRLL;
- __IO uint32_t DIVH;
- __IO uint32_t DIVL;
- __IO uint32_t CNTH;
- __IO uint32_t CNTL;
- __IO uint32_t ALRH;
- __IO uint32_t ALRL;
-} RTC_TypeDef;
-
-/**
- * @brief SD host Interface
- */
-
-typedef struct
-{
- __IO uint32_t POWER;
- __IO uint32_t CLKCR;
- __IO uint32_t ARG;
- __IO uint32_t CMD;
- __I uint32_t RESPCMD;
- __I uint32_t RESP1;
- __I uint32_t RESP2;
- __I uint32_t RESP3;
- __I uint32_t RESP4;
- __IO uint32_t DTIMER;
- __IO uint32_t DLEN;
- __IO uint32_t DCTRL;
- __I uint32_t DCOUNT;
- __I uint32_t STA;
- __IO uint32_t ICR;
- __IO uint32_t MASK;
- uint32_t RESERVED0[2];
- __I uint32_t FIFOCNT;
- uint32_t RESERVED1[13];
- __IO uint32_t FIFO;
-} SDIO_TypeDef;
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1;
- __IO uint32_t CR2;
- __IO uint32_t SR;
- __IO uint32_t DR;
- __IO uint32_t CRCPR;
- __IO uint32_t RXCRCR;
- __IO uint32_t TXCRCR;
- __IO uint32_t I2SCFGR;
-} SPI_TypeDef;
-
-/**
- * @brief TIM Timers
- */
-typedef struct
-{
- __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
- __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
- __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
- __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
-}TIM_TypeDef;
-
-
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
- __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
- __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
- __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
- __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
- __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/**
- * @brief Universal Serial Bus Full Speed Device
- */
-
-typedef struct
-{
- __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
- __IO uint16_t RESERVED0; /*!< Reserved */
- __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
- __IO uint16_t RESERVED1; /*!< Reserved */
- __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
- __IO uint16_t RESERVED2; /*!< Reserved */
- __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
- __IO uint16_t RESERVED3; /*!< Reserved */
- __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
- __IO uint16_t RESERVED4; /*!< Reserved */
- __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
- __IO uint16_t RESERVED5; /*!< Reserved */
- __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
- __IO uint16_t RESERVED6; /*!< Reserved */
- __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
- __IO uint16_t RESERVED7[17]; /*!< Reserved */
- __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
- __IO uint16_t RESERVED8; /*!< Reserved */
- __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
- __IO uint16_t RESERVED9; /*!< Reserved */
- __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
- __IO uint16_t RESERVEDA; /*!< Reserved */
- __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
- __IO uint16_t RESERVEDB; /*!< Reserved */
- __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
- __IO uint16_t RESERVEDC; /*!< Reserved */
-} USB_TypeDef;
-
-
-/**
- * @brief Window WATCHDOG
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-
-
-#define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
-#define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */
-#define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
-#define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
-
-#define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
-
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE PERIPH_BASE
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
-
-#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
-#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
-#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
-#define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
-#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
-#define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
-#define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
-#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
-#define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
-#define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
-#define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
-#define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
-#define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
-#define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)
-#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
-#define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
-
-#define SDIO_BASE (PERIPH_BASE + 0x00018000U)
-
-#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
-#define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
-#define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
-
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
-#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
-#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
-#define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
-
-
-
-#define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
-
-/* USB device FS */
-#define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
-
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-
-#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
-#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
-#define RTC ((RTC_TypeDef *)RTC_BASE)
-#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
-#define USART2 ((USART_TypeDef *)USART2_BASE)
-#define USART3 ((USART_TypeDef *)USART3_BASE)
-#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
-#define USB ((USB_TypeDef *)USB_BASE)
-#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
-#define BKP ((BKP_TypeDef *)BKP_BASE)
-#define PWR ((PWR_TypeDef *)PWR_BASE)
-#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
-#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
-#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
-#define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
-#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
-#define USART1 ((USART_TypeDef *)USART1_BASE)
-#define SDIO ((SDIO_TypeDef *)SDIO_BASE)
-#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
-#define RCC ((RCC_TypeDef *)RCC_BASE)
-#define CRC ((CRC_TypeDef *)CRC_BASE)
-#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
-#define OB ((OB_TypeDef *)OB_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
-
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers_Bits_Definition */
-/******************************************************************************/
-
-/******************************************************************************/
-/* */
-/* CRC calculation unit (CRC) */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for CRC_DR register *********************/
-#define CRC_DR_DR_Pos (0U)
-#define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
-#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
-
-/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR_Pos (0U)
-#define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
-#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
-
-/******************** Bit definition for CRC_CR register ********************/
-#define CRC_CR_RESET_Pos (0U)
-#define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
-#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
-
-/******************************************************************************/
-/* */
-/* Power Control */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for PWR_CR register ********************/
-#define PWR_CR_LPDS_Pos (0U)
-#define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
-#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
-#define PWR_CR_PDDS_Pos (1U)
-#define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
-#define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF_Pos (2U)
-#define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
-#define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF_Pos (3U)
-#define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
-#define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
-#define PWR_CR_PVDE_Pos (4U)
-#define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
-#define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS_Pos (5U)
-#define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
-#define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
-#define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
-#define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
-#define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
-#define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
-#define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
-#define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
-#define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
-#define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
-#define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
-
-/* Legacy defines */
-#define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
-#define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
-#define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
-#define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
-#define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
-#define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
-#define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
-#define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
-
-#define PWR_CR_DBP_Pos (8U)
-#define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
-#define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
-
-
-/******************* Bit definition for PWR_CSR register ********************/
-#define PWR_CSR_WUF_Pos (0U)
-#define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
-#define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
-#define PWR_CSR_SBF_Pos (1U)
-#define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
-#define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
-#define PWR_CSR_PVDO_Pos (2U)
-#define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
-#define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
-#define PWR_CSR_EWUP_Pos (8U)
-#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
-#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
-
-/******************************************************************************/
-/* */
-/* Backup registers */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for BKP_DR1 register ********************/
-#define BKP_DR1_D_Pos (0U)
-#define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR2 register ********************/
-#define BKP_DR2_D_Pos (0U)
-#define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR3 register ********************/
-#define BKP_DR3_D_Pos (0U)
-#define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR4 register ********************/
-#define BKP_DR4_D_Pos (0U)
-#define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR5 register ********************/
-#define BKP_DR5_D_Pos (0U)
-#define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR6 register ********************/
-#define BKP_DR6_D_Pos (0U)
-#define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR7 register ********************/
-#define BKP_DR7_D_Pos (0U)
-#define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR8 register ********************/
-#define BKP_DR8_D_Pos (0U)
-#define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR9 register ********************/
-#define BKP_DR9_D_Pos (0U)
-#define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
-
-/******************* Bit definition for BKP_DR10 register *******************/
-#define BKP_DR10_D_Pos (0U)
-#define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
-#define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
-
-#define RTC_BKP_NUMBER 10
-
-/****************** Bit definition for BKP_RTCCR register *******************/
-#define BKP_RTCCR_CAL_Pos (0U)
-#define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
-#define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
-#define BKP_RTCCR_CCO_Pos (7U)
-#define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
-#define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
-#define BKP_RTCCR_ASOE_Pos (8U)
-#define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
-#define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
-#define BKP_RTCCR_ASOS_Pos (9U)
-#define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
-#define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
-
-/******************** Bit definition for BKP_CR register ********************/
-#define BKP_CR_TPE_Pos (0U)
-#define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
-#define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
-#define BKP_CR_TPAL_Pos (1U)
-#define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
-#define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
-
-/******************* Bit definition for BKP_CSR register ********************/
-#define BKP_CSR_CTE_Pos (0U)
-#define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
-#define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
-#define BKP_CSR_CTI_Pos (1U)
-#define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
-#define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
-#define BKP_CSR_TPIE_Pos (2U)
-#define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
-#define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
-#define BKP_CSR_TEF_Pos (8U)
-#define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
-#define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
-#define BKP_CSR_TIF_Pos (9U)
-#define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
-#define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
-
-/******************************************************************************/
-/* */
-/* Reset and Clock Control */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for RCC_CR register ********************/
-#define RCC_CR_HSION_Pos (0U)
-#define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
-#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY_Pos (1U)
-#define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
-#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSITRIM_Pos (3U)
-#define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
-#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
-#define RCC_CR_HSICAL_Pos (8U)
-#define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
-#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
-#define RCC_CR_HSEON_Pos (16U)
-#define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
-#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY_Pos (17U)
-#define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
-#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP_Pos (18U)
-#define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
-#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSON_Pos (19U)
-#define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
-#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
-#define RCC_CR_PLLON_Pos (24U)
-#define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
-#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
-#define RCC_CR_PLLRDY_Pos (25U)
-#define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
-#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
-
-
-/******************* Bit definition for RCC_CFGR register *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos (0U)
-#define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
-#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
-#define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos (2U)
-#define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
-#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos (4U)
-#define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos (8U)
-#define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
-
-#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos (11U)
-#define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
-
-#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
-
-/*!< ADCPPRE configuration */
-#define RCC_CFGR_ADCPRE_Pos (14U)
-#define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
-#define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
-#define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
-#define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
-
-#define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
-#define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
-#define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
-#define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
-
-#define RCC_CFGR_PLLSRC_Pos (16U)
-#define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
-#define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLXTPRE_Pos (17U)
-#define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
-#define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMULL_Pos (18U)
-#define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
-#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
-#define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
-#define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
-#define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
-
-#define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
-
-#define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
-#define RCC_CFGR_PLLMULL3_Pos (18U)
-#define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
-#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
-#define RCC_CFGR_PLLMULL4_Pos (19U)
-#define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
-#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
-#define RCC_CFGR_PLLMULL5_Pos (18U)
-#define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
-#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
-#define RCC_CFGR_PLLMULL6_Pos (20U)
-#define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
-#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
-#define RCC_CFGR_PLLMULL7_Pos (18U)
-#define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
-#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
-#define RCC_CFGR_PLLMULL8_Pos (19U)
-#define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
-#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
-#define RCC_CFGR_PLLMULL9_Pos (18U)
-#define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
-#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
-#define RCC_CFGR_PLLMULL10_Pos (21U)
-#define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
-#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
-#define RCC_CFGR_PLLMULL11_Pos (18U)
-#define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
-#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
-#define RCC_CFGR_PLLMULL12_Pos (19U)
-#define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
-#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
-#define RCC_CFGR_PLLMULL13_Pos (18U)
-#define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
-#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
-#define RCC_CFGR_PLLMULL14_Pos (20U)
-#define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
-#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
-#define RCC_CFGR_PLLMULL15_Pos (18U)
-#define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
-#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
-#define RCC_CFGR_PLLMULL16_Pos (19U)
-#define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
-#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
-#define RCC_CFGR_USBPRE_Pos (22U)
-#define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
-#define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCO_Pos (24U)
-#define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
-#define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
-#define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
-#define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
-
-#define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
-
- /* Reference defines */
- #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
- #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
- #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
- #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
- #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
- #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
- #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
- #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
- #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
-
-/*!<****************** Bit definition for RCC_CIR register ********************/
-#define RCC_CIR_LSIRDYF_Pos (0U)
-#define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF_Pos (1U)
-#define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF_Pos (2U)
-#define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF_Pos (3U)
-#define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF_Pos (4U)
-#define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_CSSF_Pos (7U)
-#define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
-#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
-#define RCC_CIR_LSIRDYIE_Pos (8U)
-#define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE_Pos (9U)
-#define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE_Pos (10U)
-#define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE_Pos (11U)
-#define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE_Pos (12U)
-#define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_LSIRDYC_Pos (16U)
-#define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC_Pos (17U)
-#define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC_Pos (18U)
-#define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC_Pos (19U)
-#define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC_Pos (20U)
-#define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_CSSC_Pos (23U)
-#define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
-#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
-
-
-/***************** Bit definition for RCC_APB2RSTR register *****************/
-#define RCC_APB2RSTR_AFIORST_Pos (0U)
-#define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
-#define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
-#define RCC_APB2RSTR_IOPARST_Pos (2U)
-#define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
-#define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
-#define RCC_APB2RSTR_IOPBRST_Pos (3U)
-#define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
-#define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
-#define RCC_APB2RSTR_IOPCRST_Pos (4U)
-#define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
-#define RCC_APB2RSTR_IOPDRST_Pos (5U)
-#define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
-#define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
-#define RCC_APB2RSTR_ADC1RST_Pos (9U)
-#define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
-#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
-
-#define RCC_APB2RSTR_ADC2RST_Pos (10U)
-#define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
-#define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
-
-#define RCC_APB2RSTR_TIM1RST_Pos (11U)
-#define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
-#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
-#define RCC_APB2RSTR_SPI1RST_Pos (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
-#define RCC_APB2RSTR_USART1RST_Pos (14U)
-#define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
-
-
-#define RCC_APB2RSTR_IOPERST_Pos (6U)
-#define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
-#define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
-
-
-
-
-/***************** Bit definition for RCC_APB1RSTR register *****************/
-#define RCC_APB1RSTR_TIM2RST_Pos (0U)
-#define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
-#define RCC_APB1RSTR_TIM3RST_Pos (1U)
-#define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
-#define RCC_APB1RSTR_WWDGRST_Pos (11U)
-#define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
-#define RCC_APB1RSTR_USART2RST_Pos (17U)
-#define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
-#define RCC_APB1RSTR_I2C1RST_Pos (21U)
-#define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
-
-#define RCC_APB1RSTR_CAN1RST_Pos (25U)
-#define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
-#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
-
-#define RCC_APB1RSTR_BKPRST_Pos (27U)
-#define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
-#define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
-#define RCC_APB1RSTR_PWRRST_Pos (28U)
-#define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
-
-#define RCC_APB1RSTR_TIM4RST_Pos (2U)
-#define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
-#define RCC_APB1RSTR_SPI2RST_Pos (14U)
-#define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
-#define RCC_APB1RSTR_USART3RST_Pos (18U)
-#define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
-#define RCC_APB1RSTR_I2C2RST_Pos (22U)
-#define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
-
-#define RCC_APB1RSTR_USBRST_Pos (23U)
-#define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
-#define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
-
-
-
-
-
-
-/****************** Bit definition for RCC_AHBENR register ******************/
-#define RCC_AHBENR_DMA1EN_Pos (0U)
-#define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
-#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
-#define RCC_AHBENR_SRAMEN_Pos (2U)
-#define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
-#define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
-#define RCC_AHBENR_FLITFEN_Pos (4U)
-#define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
-#define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
-#define RCC_AHBENR_CRCEN_Pos (6U)
-#define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
-#define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
-
-
-
-
-/****************** Bit definition for RCC_APB2ENR register *****************/
-#define RCC_APB2ENR_AFIOEN_Pos (0U)
-#define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
-#define RCC_APB2ENR_IOPAEN_Pos (2U)
-#define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
-#define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
-#define RCC_APB2ENR_IOPBEN_Pos (3U)
-#define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
-#define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
-#define RCC_APB2ENR_IOPCEN_Pos (4U)
-#define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
-#define RCC_APB2ENR_IOPDEN_Pos (5U)
-#define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
-#define RCC_APB2ENR_ADC1EN_Pos (9U)
-#define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
-
-#define RCC_APB2ENR_ADC2EN_Pos (10U)
-#define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
-#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
-
-#define RCC_APB2ENR_TIM1EN_Pos (11U)
-#define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
-#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
-#define RCC_APB2ENR_SPI1EN_Pos (12U)
-#define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
-#define RCC_APB2ENR_USART1EN_Pos (14U)
-#define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
-
-
-#define RCC_APB2ENR_IOPEEN_Pos (6U)
-#define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
-#define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
-
-
-
-
-/***************** Bit definition for RCC_APB1ENR register ******************/
-#define RCC_APB1ENR_TIM2EN_Pos (0U)
-#define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
-#define RCC_APB1ENR_TIM3EN_Pos (1U)
-#define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_WWDGEN_Pos (11U)
-#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_USART2EN_Pos (17U)
-#define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
-#define RCC_APB1ENR_I2C1EN_Pos (21U)
-#define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
-
-#define RCC_APB1ENR_CAN1EN_Pos (25U)
-#define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
-#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
-
-#define RCC_APB1ENR_BKPEN_Pos (27U)
-#define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
-#define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
-#define RCC_APB1ENR_PWREN_Pos (28U)
-#define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
-
-#define RCC_APB1ENR_TIM4EN_Pos (2U)
-#define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
-#define RCC_APB1ENR_SPI2EN_Pos (14U)
-#define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
-#define RCC_APB1ENR_USART3EN_Pos (18U)
-#define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
-#define RCC_APB1ENR_I2C2EN_Pos (22U)
-#define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
-
-#define RCC_APB1ENR_USBEN_Pos (23U)
-#define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
-
-
-
-
-
-
-/******************* Bit definition for RCC_BDCR register *******************/
-#define RCC_BDCR_LSEON_Pos (0U)
-#define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
-#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
-#define RCC_BDCR_LSERDY_Pos (1U)
-#define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
-#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
-#define RCC_BDCR_LSEBYP_Pos (2U)
-#define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
-#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
-
-#define RCC_BDCR_RTCSEL_Pos (8U)
-#define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
-#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
-#define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
-
-/*!< RTC congiguration */
-#define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
-
-#define RCC_BDCR_RTCEN_Pos (15U)
-#define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
-#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
-#define RCC_BDCR_BDRST_Pos (16U)
-#define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
-#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
-
-/******************* Bit definition for RCC_CSR register ********************/
-#define RCC_CSR_LSION_Pos (0U)
-#define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
-#define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY_Pos (1U)
-#define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
-#define RCC_CSR_RMVF_Pos (24U)
-#define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
-#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
-#define RCC_CSR_PINRSTF_Pos (26U)
-#define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF_Pos (27U)
-#define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF_Pos (28U)
-#define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF_Pos (29U)
-#define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF_Pos (30U)
-#define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF_Pos (31U)
-#define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
-
-
-
-/******************************************************************************/
-/* */
-/* General Purpose and Alternate Function I/O */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for GPIO_CRL register *******************/
-#define GPIO_CRL_MODE_Pos (0U)
-#define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
-#define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
-
-#define GPIO_CRL_MODE0_Pos (0U)
-#define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
-#define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
-#define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
-#define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
-
-#define GPIO_CRL_MODE1_Pos (4U)
-#define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
-#define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
-#define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
-#define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
-
-#define GPIO_CRL_MODE2_Pos (8U)
-#define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
-#define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
-#define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
-#define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
-
-#define GPIO_CRL_MODE3_Pos (12U)
-#define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
-#define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
-#define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
-#define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
-
-#define GPIO_CRL_MODE4_Pos (16U)
-#define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
-#define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
-#define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
-#define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
-
-#define GPIO_CRL_MODE5_Pos (20U)
-#define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
-#define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
-#define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
-#define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
-
-#define GPIO_CRL_MODE6_Pos (24U)
-#define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
-#define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
-#define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
-#define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
-
-#define GPIO_CRL_MODE7_Pos (28U)
-#define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
-#define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
-#define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
-#define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
-
-#define GPIO_CRL_CNF_Pos (2U)
-#define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
-#define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
-
-#define GPIO_CRL_CNF0_Pos (2U)
-#define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
-#define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
-#define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
-#define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
-
-#define GPIO_CRL_CNF1_Pos (6U)
-#define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
-#define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
-#define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
-#define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
-
-#define GPIO_CRL_CNF2_Pos (10U)
-#define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
-#define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
-#define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
-#define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
-
-#define GPIO_CRL_CNF3_Pos (14U)
-#define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
-#define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
-#define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
-#define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
-
-#define GPIO_CRL_CNF4_Pos (18U)
-#define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
-#define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
-#define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
-#define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
-
-#define GPIO_CRL_CNF5_Pos (22U)
-#define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
-#define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
-#define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
-#define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
-
-#define GPIO_CRL_CNF6_Pos (26U)
-#define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
-#define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
-#define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
-#define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
-
-#define GPIO_CRL_CNF7_Pos (30U)
-#define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
-#define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
-#define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
-#define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
-
-/******************* Bit definition for GPIO_CRH register *******************/
-#define GPIO_CRH_MODE_Pos (0U)
-#define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
-#define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
-
-#define GPIO_CRH_MODE8_Pos (0U)
-#define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
-#define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
-#define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
-#define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
-
-#define GPIO_CRH_MODE9_Pos (4U)
-#define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
-#define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
-#define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
-#define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
-
-#define GPIO_CRH_MODE10_Pos (8U)
-#define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
-#define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
-#define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
-#define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
-
-#define GPIO_CRH_MODE11_Pos (12U)
-#define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
-#define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
-#define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
-#define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
-
-#define GPIO_CRH_MODE12_Pos (16U)
-#define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
-#define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
-#define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
-#define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
-
-#define GPIO_CRH_MODE13_Pos (20U)
-#define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
-#define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
-#define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
-#define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
-
-#define GPIO_CRH_MODE14_Pos (24U)
-#define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
-#define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
-#define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
-#define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
-
-#define GPIO_CRH_MODE15_Pos (28U)
-#define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
-#define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
-#define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
-#define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
-
-#define GPIO_CRH_CNF_Pos (2U)
-#define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
-#define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
-
-#define GPIO_CRH_CNF8_Pos (2U)
-#define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
-#define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
-#define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
-#define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
-
-#define GPIO_CRH_CNF9_Pos (6U)
-#define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
-#define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
-#define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
-#define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
-
-#define GPIO_CRH_CNF10_Pos (10U)
-#define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
-#define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
-#define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
-#define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
-
-#define GPIO_CRH_CNF11_Pos (14U)
-#define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
-#define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
-#define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
-#define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
-
-#define GPIO_CRH_CNF12_Pos (18U)
-#define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
-#define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
-#define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
-#define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
-
-#define GPIO_CRH_CNF13_Pos (22U)
-#define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
-#define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
-#define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
-#define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
-
-#define GPIO_CRH_CNF14_Pos (26U)
-#define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
-#define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
-#define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
-#define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
-
-#define GPIO_CRH_CNF15_Pos (30U)
-#define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
-#define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
-#define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
-#define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
-
-/*!<****************** Bit definition for GPIO_IDR register *******************/
-#define GPIO_IDR_IDR0_Pos (0U)
-#define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
-#define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
-#define GPIO_IDR_IDR1_Pos (1U)
-#define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
-#define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
-#define GPIO_IDR_IDR2_Pos (2U)
-#define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
-#define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
-#define GPIO_IDR_IDR3_Pos (3U)
-#define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
-#define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
-#define GPIO_IDR_IDR4_Pos (4U)
-#define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
-#define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
-#define GPIO_IDR_IDR5_Pos (5U)
-#define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
-#define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
-#define GPIO_IDR_IDR6_Pos (6U)
-#define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
-#define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
-#define GPIO_IDR_IDR7_Pos (7U)
-#define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
-#define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
-#define GPIO_IDR_IDR8_Pos (8U)
-#define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
-#define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
-#define GPIO_IDR_IDR9_Pos (9U)
-#define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
-#define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
-#define GPIO_IDR_IDR10_Pos (10U)
-#define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
-#define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
-#define GPIO_IDR_IDR11_Pos (11U)
-#define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
-#define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
-#define GPIO_IDR_IDR12_Pos (12U)
-#define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
-#define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
-#define GPIO_IDR_IDR13_Pos (13U)
-#define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
-#define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
-#define GPIO_IDR_IDR14_Pos (14U)
-#define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
-#define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
-#define GPIO_IDR_IDR15_Pos (15U)
-#define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
-#define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
-
-/******************* Bit definition for GPIO_ODR register *******************/
-#define GPIO_ODR_ODR0_Pos (0U)
-#define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
-#define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
-#define GPIO_ODR_ODR1_Pos (1U)
-#define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
-#define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
-#define GPIO_ODR_ODR2_Pos (2U)
-#define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
-#define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
-#define GPIO_ODR_ODR3_Pos (3U)
-#define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
-#define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
-#define GPIO_ODR_ODR4_Pos (4U)
-#define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
-#define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
-#define GPIO_ODR_ODR5_Pos (5U)
-#define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
-#define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
-#define GPIO_ODR_ODR6_Pos (6U)
-#define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
-#define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
-#define GPIO_ODR_ODR7_Pos (7U)
-#define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
-#define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
-#define GPIO_ODR_ODR8_Pos (8U)
-#define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
-#define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
-#define GPIO_ODR_ODR9_Pos (9U)
-#define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
-#define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
-#define GPIO_ODR_ODR10_Pos (10U)
-#define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
-#define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
-#define GPIO_ODR_ODR11_Pos (11U)
-#define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
-#define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
-#define GPIO_ODR_ODR12_Pos (12U)
-#define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
-#define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
-#define GPIO_ODR_ODR13_Pos (13U)
-#define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
-#define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
-#define GPIO_ODR_ODR14_Pos (14U)
-#define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
-#define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
-#define GPIO_ODR_ODR15_Pos (15U)
-#define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
-#define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
-
-/****************** Bit definition for GPIO_BSRR register *******************/
-#define GPIO_BSRR_BS0_Pos (0U)
-#define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
-#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
-#define GPIO_BSRR_BS1_Pos (1U)
-#define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
-#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
-#define GPIO_BSRR_BS2_Pos (2U)
-#define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
-#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
-#define GPIO_BSRR_BS3_Pos (3U)
-#define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
-#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
-#define GPIO_BSRR_BS4_Pos (4U)
-#define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
-#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
-#define GPIO_BSRR_BS5_Pos (5U)
-#define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
-#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
-#define GPIO_BSRR_BS6_Pos (6U)
-#define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
-#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
-#define GPIO_BSRR_BS7_Pos (7U)
-#define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
-#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
-#define GPIO_BSRR_BS8_Pos (8U)
-#define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
-#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
-#define GPIO_BSRR_BS9_Pos (9U)
-#define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
-#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
-#define GPIO_BSRR_BS10_Pos (10U)
-#define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
-#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
-#define GPIO_BSRR_BS11_Pos (11U)
-#define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
-#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
-#define GPIO_BSRR_BS12_Pos (12U)
-#define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
-#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
-#define GPIO_BSRR_BS13_Pos (13U)
-#define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
-#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
-#define GPIO_BSRR_BS14_Pos (14U)
-#define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
-#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
-#define GPIO_BSRR_BS15_Pos (15U)
-#define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
-#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
-
-#define GPIO_BSRR_BR0_Pos (16U)
-#define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
-#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
-#define GPIO_BSRR_BR1_Pos (17U)
-#define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
-#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
-#define GPIO_BSRR_BR2_Pos (18U)
-#define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
-#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
-#define GPIO_BSRR_BR3_Pos (19U)
-#define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
-#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
-#define GPIO_BSRR_BR4_Pos (20U)
-#define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
-#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
-#define GPIO_BSRR_BR5_Pos (21U)
-#define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
-#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
-#define GPIO_BSRR_BR6_Pos (22U)
-#define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
-#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
-#define GPIO_BSRR_BR7_Pos (23U)
-#define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
-#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
-#define GPIO_BSRR_BR8_Pos (24U)
-#define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
-#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
-#define GPIO_BSRR_BR9_Pos (25U)
-#define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
-#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
-#define GPIO_BSRR_BR10_Pos (26U)
-#define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
-#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
-#define GPIO_BSRR_BR11_Pos (27U)
-#define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
-#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
-#define GPIO_BSRR_BR12_Pos (28U)
-#define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
-#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
-#define GPIO_BSRR_BR13_Pos (29U)
-#define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
-#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
-#define GPIO_BSRR_BR14_Pos (30U)
-#define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
-#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
-#define GPIO_BSRR_BR15_Pos (31U)
-#define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
-#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
-
-/******************* Bit definition for GPIO_BRR register *******************/
-#define GPIO_BRR_BR0_Pos (0U)
-#define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
-#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
-#define GPIO_BRR_BR1_Pos (1U)
-#define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
-#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
-#define GPIO_BRR_BR2_Pos (2U)
-#define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
-#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
-#define GPIO_BRR_BR3_Pos (3U)
-#define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
-#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
-#define GPIO_BRR_BR4_Pos (4U)
-#define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
-#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
-#define GPIO_BRR_BR5_Pos (5U)
-#define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
-#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
-#define GPIO_BRR_BR6_Pos (6U)
-#define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
-#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
-#define GPIO_BRR_BR7_Pos (7U)
-#define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
-#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
-#define GPIO_BRR_BR8_Pos (8U)
-#define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
-#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
-#define GPIO_BRR_BR9_Pos (9U)
-#define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
-#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
-#define GPIO_BRR_BR10_Pos (10U)
-#define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
-#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
-#define GPIO_BRR_BR11_Pos (11U)
-#define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
-#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
-#define GPIO_BRR_BR12_Pos (12U)
-#define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
-#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
-#define GPIO_BRR_BR13_Pos (13U)
-#define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
-#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
-#define GPIO_BRR_BR14_Pos (14U)
-#define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
-#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
-#define GPIO_BRR_BR15_Pos (15U)
-#define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
-#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
-
-/****************** Bit definition for GPIO_LCKR register *******************/
-#define GPIO_LCKR_LCK0_Pos (0U)
-#define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
-#define GPIO_LCKR_LCK1_Pos (1U)
-#define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
-#define GPIO_LCKR_LCK2_Pos (2U)
-#define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
-#define GPIO_LCKR_LCK3_Pos (3U)
-#define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
-#define GPIO_LCKR_LCK4_Pos (4U)
-#define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
-#define GPIO_LCKR_LCK5_Pos (5U)
-#define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
-#define GPIO_LCKR_LCK6_Pos (6U)
-#define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
-#define GPIO_LCKR_LCK7_Pos (7U)
-#define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
-#define GPIO_LCKR_LCK8_Pos (8U)
-#define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
-#define GPIO_LCKR_LCK9_Pos (9U)
-#define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
-#define GPIO_LCKR_LCK10_Pos (10U)
-#define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
-#define GPIO_LCKR_LCK11_Pos (11U)
-#define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
-#define GPIO_LCKR_LCK12_Pos (12U)
-#define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
-#define GPIO_LCKR_LCK13_Pos (13U)
-#define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
-#define GPIO_LCKR_LCK14_Pos (14U)
-#define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
-#define GPIO_LCKR_LCK15_Pos (15U)
-#define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
-#define GPIO_LCKR_LCKK_Pos (16U)
-#define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
-
-/*----------------------------------------------------------------------------*/
-
-/****************** Bit definition for AFIO_EVCR register *******************/
-#define AFIO_EVCR_PIN_Pos (0U)
-#define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
-#define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
-#define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
-#define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
-#define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
-#define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
-
-/*!< PIN configuration */
-#define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
-#define AFIO_EVCR_PIN_PX1_Pos (0U)
-#define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
-#define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
-#define AFIO_EVCR_PIN_PX2_Pos (1U)
-#define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
-#define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
-#define AFIO_EVCR_PIN_PX3_Pos (0U)
-#define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
-#define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
-#define AFIO_EVCR_PIN_PX4_Pos (2U)
-#define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
-#define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
-#define AFIO_EVCR_PIN_PX5_Pos (0U)
-#define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
-#define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
-#define AFIO_EVCR_PIN_PX6_Pos (1U)
-#define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
-#define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
-#define AFIO_EVCR_PIN_PX7_Pos (0U)
-#define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
-#define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
-#define AFIO_EVCR_PIN_PX8_Pos (3U)
-#define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
-#define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
-#define AFIO_EVCR_PIN_PX9_Pos (0U)
-#define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
-#define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
-#define AFIO_EVCR_PIN_PX10_Pos (1U)
-#define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
-#define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
-#define AFIO_EVCR_PIN_PX11_Pos (0U)
-#define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
-#define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
-#define AFIO_EVCR_PIN_PX12_Pos (2U)
-#define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
-#define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
-#define AFIO_EVCR_PIN_PX13_Pos (0U)
-#define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
-#define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
-#define AFIO_EVCR_PIN_PX14_Pos (1U)
-#define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
-#define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
-#define AFIO_EVCR_PIN_PX15_Pos (0U)
-#define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
-#define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
-
-#define AFIO_EVCR_PORT_Pos (4U)
-#define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
-#define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
-#define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
-#define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
-#define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
-
-/*!< PORT configuration */
-#define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
-#define AFIO_EVCR_PORT_PB_Pos (4U)
-#define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
-#define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
-#define AFIO_EVCR_PORT_PC_Pos (5U)
-#define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
-#define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
-#define AFIO_EVCR_PORT_PD_Pos (4U)
-#define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
-#define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
-#define AFIO_EVCR_PORT_PE_Pos (6U)
-#define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
-#define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
-
-#define AFIO_EVCR_EVOE_Pos (7U)
-#define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
-#define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
-
-/****************** Bit definition for AFIO_MAPR register *******************/
-#define AFIO_MAPR_SPI1_REMAP_Pos (0U)
-#define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
-#define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
-#define AFIO_MAPR_I2C1_REMAP_Pos (1U)
-#define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
-#define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
-#define AFIO_MAPR_USART1_REMAP_Pos (2U)
-#define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
-#define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
-#define AFIO_MAPR_USART2_REMAP_Pos (3U)
-#define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
-#define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
-
-#define AFIO_MAPR_USART3_REMAP_Pos (4U)
-#define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
-#define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
-#define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
-#define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
-
-/* USART3_REMAP configuration */
-#define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
-#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
-#define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
-
-#define AFIO_MAPR_TIM1_REMAP_Pos (6U)
-#define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
-#define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
-#define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
-#define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
-
-/*!< TIM1_REMAP configuration */
-#define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
-#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
-#define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
-
-#define AFIO_MAPR_TIM2_REMAP_Pos (8U)
-#define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
-#define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
-#define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
-#define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
-
-/*!< TIM2_REMAP configuration */
-#define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
-#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
-#define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
-
-#define AFIO_MAPR_TIM3_REMAP_Pos (10U)
-#define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
-#define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
-#define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
-#define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
-
-/*!< TIM3_REMAP configuration */
-#define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
-#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
-#define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
-
-#define AFIO_MAPR_TIM4_REMAP_Pos (12U)
-#define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
-#define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
-
-#define AFIO_MAPR_CAN_REMAP_Pos (13U)
-#define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
-#define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
-#define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
-#define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
-
-/*!< CAN_REMAP configuration */
-#define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
-#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
-#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
-#define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
-#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
-#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
-#define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
-
-#define AFIO_MAPR_PD01_REMAP_Pos (15U)
-#define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
-#define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-
-/*!< SWJ_CFG configuration */
-#define AFIO_MAPR_SWJ_CFG_Pos (24U)
-#define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
-#define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
-#define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
-#define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
-#define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
-
-#define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
-#define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
-#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
-#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
-#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
-#define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
-
-
-/***************** Bit definition for AFIO_EXTICR1 register *****************/
-#define AFIO_EXTICR1_EXTI0_Pos (0U)
-#define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
-#define AFIO_EXTICR1_EXTI1_Pos (4U)
-#define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
-#define AFIO_EXTICR1_EXTI2_Pos (8U)
-#define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
-#define AFIO_EXTICR1_EXTI3_Pos (12U)
-#define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
-
-/*!< EXTI0 configuration */
-#define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
-#define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
-#define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
-#define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
-#define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
-#define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
-#define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
-#define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
-#define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
-#define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
-#define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
-#define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
-#define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
-#define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
-#define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
-#define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
-#define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
-#define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
-#define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
-
-/*!< EXTI1 configuration */
-#define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
-#define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
-#define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
-#define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
-#define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
-#define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
-#define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
-#define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
-#define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
-#define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
-#define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
-#define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
-#define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
-#define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
-#define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
-#define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
-#define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
-#define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
-#define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
-
-/*!< EXTI2 configuration */
-#define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
-#define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
-#define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
-#define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
-#define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
-#define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
-#define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
-#define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
-#define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
-#define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
-#define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
-#define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
-#define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
-#define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
-#define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
-#define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
-#define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
-#define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
-#define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
-
-/*!< EXTI3 configuration */
-#define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
-#define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
-#define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
-#define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
-#define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
-#define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
-#define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
-#define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
-#define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
-#define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
-#define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
-#define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
-#define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
-#define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
-#define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
-#define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
-#define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
-#define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
-#define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
-
-/***************** Bit definition for AFIO_EXTICR2 register *****************/
-#define AFIO_EXTICR2_EXTI4_Pos (0U)
-#define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
-#define AFIO_EXTICR2_EXTI5_Pos (4U)
-#define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
-#define AFIO_EXTICR2_EXTI6_Pos (8U)
-#define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
-#define AFIO_EXTICR2_EXTI7_Pos (12U)
-#define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
-
-/*!< EXTI4 configuration */
-#define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
-#define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
-#define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
-#define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
-#define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
-#define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
-#define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
-#define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
-#define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
-#define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
-#define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
-#define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
-#define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
-#define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
-#define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
-#define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
-#define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
-#define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
-#define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
-
-/* EXTI5 configuration */
-#define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
-#define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
-#define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
-#define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
-#define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
-#define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
-#define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
-#define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
-#define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
-#define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
-#define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
-#define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
-#define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
-#define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
-#define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
-#define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
-#define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
-#define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
-#define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
-
-/*!< EXTI6 configuration */
-#define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
-#define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
-#define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
-#define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
-#define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
-#define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
-#define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
-#define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
-#define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
-#define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
-#define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
-#define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
-#define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
-#define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
-#define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
-#define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
-#define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
-#define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
-#define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
-
-/*!< EXTI7 configuration */
-#define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
-#define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
-#define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
-#define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
-#define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
-#define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
-#define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
-#define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
-#define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
-#define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
-#define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
-#define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
-#define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
-#define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
-#define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
-#define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
-#define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
-#define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
-#define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
-
-/***************** Bit definition for AFIO_EXTICR3 register *****************/
-#define AFIO_EXTICR3_EXTI8_Pos (0U)
-#define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
-#define AFIO_EXTICR3_EXTI9_Pos (4U)
-#define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
-#define AFIO_EXTICR3_EXTI10_Pos (8U)
-#define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
-#define AFIO_EXTICR3_EXTI11_Pos (12U)
-#define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
-
-/*!< EXTI8 configuration */
-#define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
-#define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
-#define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
-#define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
-#define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
-#define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
-#define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
-#define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
-#define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
-#define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
-#define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
-#define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
-#define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
-#define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
-#define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
-#define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
-#define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
-#define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
-#define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
-
-/*!< EXTI9 configuration */
-#define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
-#define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
-#define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
-#define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
-#define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
-#define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
-#define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
-#define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
-#define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
-#define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
-#define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
-#define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
-#define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
-#define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
-#define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
-#define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
-#define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
-#define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
-#define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
-
-/*!< EXTI10 configuration */
-#define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
-#define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
-#define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
-#define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
-#define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
-#define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
-#define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
-#define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
-#define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
-#define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
-#define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
-#define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
-#define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
-#define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
-#define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
-#define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
-#define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
-#define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
-#define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
-
-/*!< EXTI11 configuration */
-#define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
-#define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
-#define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
-#define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
-#define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
-#define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
-#define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
-#define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
-#define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
-#define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
-#define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
-#define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
-#define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
-#define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
-#define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
-#define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
-#define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
-#define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
-#define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
-
-/***************** Bit definition for AFIO_EXTICR4 register *****************/
-#define AFIO_EXTICR4_EXTI12_Pos (0U)
-#define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
-#define AFIO_EXTICR4_EXTI13_Pos (4U)
-#define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
-#define AFIO_EXTICR4_EXTI14_Pos (8U)
-#define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
-#define AFIO_EXTICR4_EXTI15_Pos (12U)
-#define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
-
-/* EXTI12 configuration */
-#define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
-#define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
-#define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
-#define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
-#define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
-#define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
-#define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
-#define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
-#define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
-#define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
-#define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
-#define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
-#define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
-#define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
-#define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
-#define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
-#define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
-#define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
-#define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
-
-/* EXTI13 configuration */
-#define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
-#define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
-#define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
-#define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
-#define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
-#define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
-#define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
-#define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
-#define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
-#define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
-#define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
-#define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
-#define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
-#define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
-#define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
-#define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
-#define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
-#define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
-#define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
-
-/*!< EXTI14 configuration */
-#define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
-#define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
-#define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
-#define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
-#define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
-#define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
-#define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
-#define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
-#define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
-#define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
-#define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
-#define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
-#define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
-#define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
-#define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
-#define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
-#define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
-#define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
-#define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
-
-/*!< EXTI15 configuration */
-#define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
-#define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
-#define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
-#define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
-#define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
-#define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
-#define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
-#define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
-#define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
-#define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
-#define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
-#define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
-#define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
-#define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
-#define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
-#define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
-#define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
-#define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
-#define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
-
-/****************** Bit definition for AFIO_MAPR2 register ******************/
-
-
-
-/******************************************************************************/
-/* */
-/* External Interrupt/Event Controller */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for EXTI_IMR register *******************/
-#define EXTI_IMR_MR0_Pos (0U)
-#define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
-#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos (1U)
-#define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
-#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos (2U)
-#define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
-#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos (3U)
-#define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
-#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos (4U)
-#define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
-#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos (5U)
-#define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
-#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos (6U)
-#define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
-#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos (7U)
-#define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
-#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos (8U)
-#define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
-#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos (9U)
-#define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
-#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos (10U)
-#define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
-#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos (11U)
-#define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
-#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos (12U)
-#define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
-#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos (13U)
-#define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
-#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos (14U)
-#define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
-#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos (15U)
-#define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
-#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos (16U)
-#define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
-#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos (17U)
-#define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
-#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos (18U)
-#define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
-#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
-
-/* References Defines */
-#define EXTI_IMR_IM0 EXTI_IMR_MR0
-#define EXTI_IMR_IM1 EXTI_IMR_MR1
-#define EXTI_IMR_IM2 EXTI_IMR_MR2
-#define EXTI_IMR_IM3 EXTI_IMR_MR3
-#define EXTI_IMR_IM4 EXTI_IMR_MR4
-#define EXTI_IMR_IM5 EXTI_IMR_MR5
-#define EXTI_IMR_IM6 EXTI_IMR_MR6
-#define EXTI_IMR_IM7 EXTI_IMR_MR7
-#define EXTI_IMR_IM8 EXTI_IMR_MR8
-#define EXTI_IMR_IM9 EXTI_IMR_MR9
-#define EXTI_IMR_IM10 EXTI_IMR_MR10
-#define EXTI_IMR_IM11 EXTI_IMR_MR11
-#define EXTI_IMR_IM12 EXTI_IMR_MR12
-#define EXTI_IMR_IM13 EXTI_IMR_MR13
-#define EXTI_IMR_IM14 EXTI_IMR_MR14
-#define EXTI_IMR_IM15 EXTI_IMR_MR15
-#define EXTI_IMR_IM16 EXTI_IMR_MR16
-#define EXTI_IMR_IM17 EXTI_IMR_MR17
-#define EXTI_IMR_IM18 EXTI_IMR_MR18
-#define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
-
-/******************* Bit definition for EXTI_EMR register *******************/
-#define EXTI_EMR_MR0_Pos (0U)
-#define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
-#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos (1U)
-#define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
-#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos (2U)
-#define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
-#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos (3U)
-#define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
-#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos (4U)
-#define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
-#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos (5U)
-#define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
-#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos (6U)
-#define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
-#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos (7U)
-#define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
-#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos (8U)
-#define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
-#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos (9U)
-#define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
-#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos (10U)
-#define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
-#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos (11U)
-#define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
-#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos (12U)
-#define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
-#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos (13U)
-#define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
-#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos (14U)
-#define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
-#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos (15U)
-#define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
-#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos (16U)
-#define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
-#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos (17U)
-#define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
-#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos (18U)
-#define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
-#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
-
-/* References Defines */
-#define EXTI_EMR_EM0 EXTI_EMR_MR0
-#define EXTI_EMR_EM1 EXTI_EMR_MR1
-#define EXTI_EMR_EM2 EXTI_EMR_MR2
-#define EXTI_EMR_EM3 EXTI_EMR_MR3
-#define EXTI_EMR_EM4 EXTI_EMR_MR4
-#define EXTI_EMR_EM5 EXTI_EMR_MR5
-#define EXTI_EMR_EM6 EXTI_EMR_MR6
-#define EXTI_EMR_EM7 EXTI_EMR_MR7
-#define EXTI_EMR_EM8 EXTI_EMR_MR8
-#define EXTI_EMR_EM9 EXTI_EMR_MR9
-#define EXTI_EMR_EM10 EXTI_EMR_MR10
-#define EXTI_EMR_EM11 EXTI_EMR_MR11
-#define EXTI_EMR_EM12 EXTI_EMR_MR12
-#define EXTI_EMR_EM13 EXTI_EMR_MR13
-#define EXTI_EMR_EM14 EXTI_EMR_MR14
-#define EXTI_EMR_EM15 EXTI_EMR_MR15
-#define EXTI_EMR_EM16 EXTI_EMR_MR16
-#define EXTI_EMR_EM17 EXTI_EMR_MR17
-#define EXTI_EMR_EM18 EXTI_EMR_MR18
-
-/****************** Bit definition for EXTI_RTSR register *******************/
-#define EXTI_RTSR_TR0_Pos (0U)
-#define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
-#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos (1U)
-#define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
-#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos (2U)
-#define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
-#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos (3U)
-#define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
-#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos (4U)
-#define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
-#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos (5U)
-#define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
-#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos (6U)
-#define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
-#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos (7U)
-#define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
-#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos (8U)
-#define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
-#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos (9U)
-#define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
-#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos (10U)
-#define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
-#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos (11U)
-#define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
-#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos (12U)
-#define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
-#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos (13U)
-#define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
-#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos (14U)
-#define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
-#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos (15U)
-#define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
-#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos (16U)
-#define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
-#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos (17U)
-#define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
-#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos (18U)
-#define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
-#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
-
-/* References Defines */
-#define EXTI_RTSR_RT0 EXTI_RTSR_TR0
-#define EXTI_RTSR_RT1 EXTI_RTSR_TR1
-#define EXTI_RTSR_RT2 EXTI_RTSR_TR2
-#define EXTI_RTSR_RT3 EXTI_RTSR_TR3
-#define EXTI_RTSR_RT4 EXTI_RTSR_TR4
-#define EXTI_RTSR_RT5 EXTI_RTSR_TR5
-#define EXTI_RTSR_RT6 EXTI_RTSR_TR6
-#define EXTI_RTSR_RT7 EXTI_RTSR_TR7
-#define EXTI_RTSR_RT8 EXTI_RTSR_TR8
-#define EXTI_RTSR_RT9 EXTI_RTSR_TR9
-#define EXTI_RTSR_RT10 EXTI_RTSR_TR10
-#define EXTI_RTSR_RT11 EXTI_RTSR_TR11
-#define EXTI_RTSR_RT12 EXTI_RTSR_TR12
-#define EXTI_RTSR_RT13 EXTI_RTSR_TR13
-#define EXTI_RTSR_RT14 EXTI_RTSR_TR14
-#define EXTI_RTSR_RT15 EXTI_RTSR_TR15
-#define EXTI_RTSR_RT16 EXTI_RTSR_TR16
-#define EXTI_RTSR_RT17 EXTI_RTSR_TR17
-#define EXTI_RTSR_RT18 EXTI_RTSR_TR18
-
-/****************** Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_TR0_Pos (0U)
-#define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
-#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos (1U)
-#define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
-#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos (2U)
-#define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
-#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos (3U)
-#define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
-#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos (4U)
-#define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
-#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos (5U)
-#define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
-#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos (6U)
-#define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
-#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos (7U)
-#define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
-#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos (8U)
-#define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
-#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos (9U)
-#define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
-#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos (10U)
-#define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
-#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos (11U)
-#define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
-#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos (12U)
-#define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
-#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos (13U)
-#define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
-#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos (14U)
-#define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
-#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos (15U)
-#define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
-#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos (16U)
-#define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
-#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos (17U)
-#define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
-#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos (18U)
-#define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
-#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
-
-/* References Defines */
-#define EXTI_FTSR_FT0 EXTI_FTSR_TR0
-#define EXTI_FTSR_FT1 EXTI_FTSR_TR1
-#define EXTI_FTSR_FT2 EXTI_FTSR_TR2
-#define EXTI_FTSR_FT3 EXTI_FTSR_TR3
-#define EXTI_FTSR_FT4 EXTI_FTSR_TR4
-#define EXTI_FTSR_FT5 EXTI_FTSR_TR5
-#define EXTI_FTSR_FT6 EXTI_FTSR_TR6
-#define EXTI_FTSR_FT7 EXTI_FTSR_TR7
-#define EXTI_FTSR_FT8 EXTI_FTSR_TR8
-#define EXTI_FTSR_FT9 EXTI_FTSR_TR9
-#define EXTI_FTSR_FT10 EXTI_FTSR_TR10
-#define EXTI_FTSR_FT11 EXTI_FTSR_TR11
-#define EXTI_FTSR_FT12 EXTI_FTSR_TR12
-#define EXTI_FTSR_FT13 EXTI_FTSR_TR13
-#define EXTI_FTSR_FT14 EXTI_FTSR_TR14
-#define EXTI_FTSR_FT15 EXTI_FTSR_TR15
-#define EXTI_FTSR_FT16 EXTI_FTSR_TR16
-#define EXTI_FTSR_FT17 EXTI_FTSR_TR17
-#define EXTI_FTSR_FT18 EXTI_FTSR_TR18
-
-/****************** Bit definition for EXTI_SWIER register ******************/
-#define EXTI_SWIER_SWIER0_Pos (0U)
-#define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos (1U)
-#define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos (2U)
-#define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos (3U)
-#define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos (4U)
-#define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos (5U)
-#define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos (6U)
-#define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos (7U)
-#define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos (8U)
-#define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos (9U)
-#define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos (10U)
-#define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos (11U)
-#define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos (12U)
-#define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos (13U)
-#define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos (14U)
-#define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos (15U)
-#define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos (16U)
-#define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos (17U)
-#define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos (18U)
-#define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
-
-/* References Defines */
-#define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
-#define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
-#define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
-#define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
-#define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
-#define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
-#define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
-#define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
-#define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
-#define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
-#define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
-#define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
-#define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
-#define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
-#define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
-#define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
-#define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
-#define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
-#define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
-
-/******************* Bit definition for EXTI_PR register ********************/
-#define EXTI_PR_PR0_Pos (0U)
-#define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
-#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos (1U)
-#define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
-#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos (2U)
-#define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
-#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos (3U)
-#define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
-#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos (4U)
-#define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
-#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos (5U)
-#define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
-#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos (6U)
-#define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
-#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos (7U)
-#define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
-#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos (8U)
-#define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
-#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos (9U)
-#define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
-#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos (10U)
-#define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
-#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos (11U)
-#define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
-#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos (12U)
-#define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
-#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos (13U)
-#define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
-#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos (14U)
-#define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
-#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos (15U)
-#define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
-#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos (16U)
-#define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
-#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos (17U)
-#define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
-#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos (18U)
-#define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
-#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
-
-/* References Defines */
-#define EXTI_PR_PIF0 EXTI_PR_PR0
-#define EXTI_PR_PIF1 EXTI_PR_PR1
-#define EXTI_PR_PIF2 EXTI_PR_PR2
-#define EXTI_PR_PIF3 EXTI_PR_PR3
-#define EXTI_PR_PIF4 EXTI_PR_PR4
-#define EXTI_PR_PIF5 EXTI_PR_PR5
-#define EXTI_PR_PIF6 EXTI_PR_PR6
-#define EXTI_PR_PIF7 EXTI_PR_PR7
-#define EXTI_PR_PIF8 EXTI_PR_PR8
-#define EXTI_PR_PIF9 EXTI_PR_PR9
-#define EXTI_PR_PIF10 EXTI_PR_PR10
-#define EXTI_PR_PIF11 EXTI_PR_PR11
-#define EXTI_PR_PIF12 EXTI_PR_PR12
-#define EXTI_PR_PIF13 EXTI_PR_PR13
-#define EXTI_PR_PIF14 EXTI_PR_PR14
-#define EXTI_PR_PIF15 EXTI_PR_PR15
-#define EXTI_PR_PIF16 EXTI_PR_PR16
-#define EXTI_PR_PIF17 EXTI_PR_PR17
-#define EXTI_PR_PIF18 EXTI_PR_PR18
-
-/******************************************************************************/
-/* */
-/* DMA Controller */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for DMA_ISR register ********************/
-#define DMA_ISR_GIF1_Pos (0U)
-#define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
-#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos (1U)
-#define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
-#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos (2U)
-#define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
-#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos (3U)
-#define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
-#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos (4U)
-#define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
-#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos (5U)
-#define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
-#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos (6U)
-#define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
-#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos (7U)
-#define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
-#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos (8U)
-#define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
-#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos (9U)
-#define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
-#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos (10U)
-#define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
-#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos (11U)
-#define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
-#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos (12U)
-#define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
-#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos (13U)
-#define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
-#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos (14U)
-#define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
-#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos (15U)
-#define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
-#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos (16U)
-#define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
-#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos (17U)
-#define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
-#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos (18U)
-#define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
-#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos (19U)
-#define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
-#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos (20U)
-#define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
-#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos (21U)
-#define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
-#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos (22U)
-#define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
-#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos (23U)
-#define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
-#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos (24U)
-#define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
-#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos (25U)
-#define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
-#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos (26U)
-#define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
-#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos (27U)
-#define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
-#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
-
-/******************* Bit definition for DMA_IFCR register *******************/
-#define DMA_IFCR_CGIF1_Pos (0U)
-#define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos (1U)
-#define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos (2U)
-#define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos (3U)
-#define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos (4U)
-#define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos (5U)
-#define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos (6U)
-#define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos (7U)
-#define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos (8U)
-#define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos (9U)
-#define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos (10U)
-#define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos (11U)
-#define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos (12U)
-#define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos (13U)
-#define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos (14U)
-#define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos (15U)
-#define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos (16U)
-#define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos (17U)
-#define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos (18U)
-#define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos (19U)
-#define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos (20U)
-#define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos (21U)
-#define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos (22U)
-#define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos (23U)
-#define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos (24U)
-#define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos (25U)
-#define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos (26U)
-#define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos (27U)
-#define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
-
-/******************* Bit definition for DMA_CCR register *******************/
-#define DMA_CCR_EN_Pos (0U)
-#define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
-#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
-#define DMA_CCR_TCIE_Pos (1U)
-#define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
-#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE_Pos (2U)
-#define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
-#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE_Pos (3U)
-#define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
-#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR_Pos (4U)
-#define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
-#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
-#define DMA_CCR_CIRC_Pos (5U)
-#define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
-#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
-#define DMA_CCR_PINC_Pos (6U)
-#define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
-#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
-#define DMA_CCR_MINC_Pos (7U)
-#define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
-#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE_Pos (8U)
-#define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
-#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos (10U)
-#define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos (12U)
-#define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
-#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
-#define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
-#define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos (14U)
-#define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
-
-/****************** Bit definition for DMA_CNDTR register ******************/
-#define DMA_CNDTR_NDT_Pos (0U)
-#define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
-#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CPAR register *******************/
-#define DMA_CPAR_PA_Pos (0U)
-#define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
-
-/****************** Bit definition for DMA_CMAR register *******************/
-#define DMA_CMAR_MA_Pos (0U)
-#define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
-
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter (ADC) */
-/* */
-/******************************************************************************/
-
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
- */
-#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
-
-/******************** Bit definition for ADC_SR register ********************/
-#define ADC_SR_AWD_Pos (0U)
-#define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
-#define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
-#define ADC_SR_EOS_Pos (1U)
-#define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
-#define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
-#define ADC_SR_JEOS_Pos (2U)
-#define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
-#define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
-#define ADC_SR_JSTRT_Pos (3U)
-#define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
-#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
-#define ADC_SR_STRT_Pos (4U)
-#define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
-#define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
-
-/* Legacy defines */
-#define ADC_SR_EOC (ADC_SR_EOS)
-#define ADC_SR_JEOC (ADC_SR_JEOS)
-
-/******************* Bit definition for ADC_CR1 register ********************/
-#define ADC_CR1_AWDCH_Pos (0U)
-#define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
-#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
-
-#define ADC_CR1_EOSIE_Pos (5U)
-#define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
-#define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
-#define ADC_CR1_AWDIE_Pos (6U)
-#define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
-#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
-#define ADC_CR1_JEOSIE_Pos (7U)
-#define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
-#define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
-#define ADC_CR1_SCAN_Pos (8U)
-#define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
-#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
-#define ADC_CR1_AWDSGL_Pos (9U)
-#define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CR1_JAUTO_Pos (10U)
-#define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
-#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
-#define ADC_CR1_DISCEN_Pos (11U)
-#define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
-#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CR1_JDISCEN_Pos (12U)
-#define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
-
-#define ADC_CR1_DISCNUM_Pos (13U)
-#define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
-#define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
-
-#define ADC_CR1_DUALMOD_Pos (16U)
-#define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
-#define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
-#define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
-#define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
-#define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
-#define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
-
-#define ADC_CR1_JAWDEN_Pos (22U)
-#define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
-#define ADC_CR1_AWDEN_Pos (23U)
-#define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
-#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-/* Legacy defines */
-#define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
-#define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
-
-/******************* Bit definition for ADC_CR2 register ********************/
-#define ADC_CR2_ADON_Pos (0U)
-#define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
-#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
-#define ADC_CR2_CONT_Pos (1U)
-#define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
-#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
-#define ADC_CR2_CAL_Pos (2U)
-#define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
-#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
-#define ADC_CR2_RSTCAL_Pos (3U)
-#define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
-#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
-#define ADC_CR2_DMA_Pos (8U)
-#define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
-#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
-#define ADC_CR2_ALIGN_Pos (11U)
-#define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
-#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
-
-#define ADC_CR2_JEXTSEL_Pos (12U)
-#define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
-#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
-#define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
-#define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
-#define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
-
-#define ADC_CR2_JEXTTRIG_Pos (15U)
-#define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
-#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
-
-#define ADC_CR2_EXTSEL_Pos (17U)
-#define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
-#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
-#define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
-#define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
-#define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
-
-#define ADC_CR2_EXTTRIG_Pos (20U)
-#define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
-#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
-#define ADC_CR2_JSWSTART_Pos (21U)
-#define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
-#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
-#define ADC_CR2_SWSTART_Pos (22U)
-#define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
-#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
-#define ADC_CR2_TSVREFE_Pos (23U)
-#define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
-#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
-
-/****************** Bit definition for ADC_SMPR1 register *******************/
-#define ADC_SMPR1_SMP10_Pos (0U)
-#define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
-#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
-#define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
-#define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
-
-#define ADC_SMPR1_SMP11_Pos (3U)
-#define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
-#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
-#define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
-#define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
-
-#define ADC_SMPR1_SMP12_Pos (6U)
-#define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
-#define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
-#define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
-
-#define ADC_SMPR1_SMP13_Pos (9U)
-#define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
-#define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
-#define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
-
-#define ADC_SMPR1_SMP14_Pos (12U)
-#define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
-#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
-#define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
-#define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
-
-#define ADC_SMPR1_SMP15_Pos (15U)
-#define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
-#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
-#define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
-#define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
-#define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
-
-#define ADC_SMPR1_SMP16_Pos (18U)
-#define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
-#define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
-#define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
-
-#define ADC_SMPR1_SMP17_Pos (21U)
-#define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
-#define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
-#define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
-#define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
-
-/****************** Bit definition for ADC_SMPR2 register *******************/
-#define ADC_SMPR2_SMP0_Pos (0U)
-#define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
-#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
-#define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
-#define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
-
-#define ADC_SMPR2_SMP1_Pos (3U)
-#define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
-#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
-#define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
-#define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
-
-#define ADC_SMPR2_SMP2_Pos (6U)
-#define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
-#define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
-#define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
-
-#define ADC_SMPR2_SMP3_Pos (9U)
-#define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
-#define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
-#define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
-
-#define ADC_SMPR2_SMP4_Pos (12U)
-#define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
-#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
-#define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
-#define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
-
-#define ADC_SMPR2_SMP5_Pos (15U)
-#define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
-#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
-#define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
-#define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
-
-#define ADC_SMPR2_SMP6_Pos (18U)
-#define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
-#define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
-#define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
-
-#define ADC_SMPR2_SMP7_Pos (21U)
-#define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
-#define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
-#define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
-
-#define ADC_SMPR2_SMP8_Pos (24U)
-#define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
-#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
-#define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
-#define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
-
-#define ADC_SMPR2_SMP9_Pos (27U)
-#define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
-#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
-#define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
-#define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
-
-/****************** Bit definition for ADC_JOFR1 register *******************/
-#define ADC_JOFR1_JOFFSET1_Pos (0U)
-#define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
-
-/****************** Bit definition for ADC_JOFR2 register *******************/
-#define ADC_JOFR2_JOFFSET2_Pos (0U)
-#define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
-
-/****************** Bit definition for ADC_JOFR3 register *******************/
-#define ADC_JOFR3_JOFFSET3_Pos (0U)
-#define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
-
-/****************** Bit definition for ADC_JOFR4 register *******************/
-#define ADC_JOFR4_JOFFSET4_Pos (0U)
-#define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
-
-/******************* Bit definition for ADC_HTR register ********************/
-#define ADC_HTR_HT_Pos (0U)
-#define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
-#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
-
-/******************* Bit definition for ADC_LTR register ********************/
-#define ADC_LTR_LT_Pos (0U)
-#define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
-#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
-
-/******************* Bit definition for ADC_SQR1 register *******************/
-#define ADC_SQR1_SQ13_Pos (0U)
-#define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
-#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
-#define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
-#define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
-#define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
-#define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
-#define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR1_SQ14_Pos (5U)
-#define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
-#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
-#define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
-#define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
-#define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
-#define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
-#define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
-
-#define ADC_SQR1_SQ15_Pos (10U)
-#define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
-#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
-#define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
-#define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
-#define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
-#define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
-#define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
-
-#define ADC_SQR1_SQ16_Pos (15U)
-#define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
-#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
-#define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
-#define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
-#define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
-#define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
-#define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
-
-#define ADC_SQR1_L_Pos (20U)
-#define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
-#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
-#define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
-#define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
-#define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
-#define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
-
-/******************* Bit definition for ADC_SQR2 register *******************/
-#define ADC_SQR2_SQ7_Pos (0U)
-#define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
-#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
-#define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
-#define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
-#define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
-#define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
-#define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR2_SQ8_Pos (5U)
-#define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
-#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
-#define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
-#define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
-#define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
-#define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
-#define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
-
-#define ADC_SQR2_SQ9_Pos (10U)
-#define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
-#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
-#define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
-#define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
-#define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
-#define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
-#define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
-
-#define ADC_SQR2_SQ10_Pos (15U)
-#define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
-#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
-#define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
-#define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
-#define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
-#define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
-#define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
-
-#define ADC_SQR2_SQ11_Pos (20U)
-#define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
-#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
-#define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
-#define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
-#define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
-#define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
-
-#define ADC_SQR2_SQ12_Pos (25U)
-#define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
-#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
-#define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
-#define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
-#define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
-#define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
-#define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
-
-/******************* Bit definition for ADC_SQR3 register *******************/
-#define ADC_SQR3_SQ1_Pos (0U)
-#define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
-#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
-#define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
-#define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
-#define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
-#define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
-#define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
-
-#define ADC_SQR3_SQ2_Pos (5U)
-#define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
-#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
-#define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
-#define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
-#define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
-#define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
-#define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
-
-#define ADC_SQR3_SQ3_Pos (10U)
-#define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
-#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
-#define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
-#define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
-#define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
-#define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
-#define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
-
-#define ADC_SQR3_SQ4_Pos (15U)
-#define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
-#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
-#define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
-#define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
-#define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
-#define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
-#define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
-
-#define ADC_SQR3_SQ5_Pos (20U)
-#define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
-#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
-#define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
-#define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
-#define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
-#define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
-#define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
-
-#define ADC_SQR3_SQ6_Pos (25U)
-#define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
-#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
-#define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
-#define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
-#define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
-#define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
-#define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
-
-/******************* Bit definition for ADC_JSQR register *******************/
-#define ADC_JSQR_JSQ1_Pos (0U)
-#define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
-#define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
-
-#define ADC_JSQR_JSQ2_Pos (5U)
-#define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
-#define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
-
-#define ADC_JSQR_JSQ3_Pos (10U)
-#define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
-#define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
-
-#define ADC_JSQR_JSQ4_Pos (15U)
-#define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
-#define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
-
-#define ADC_JSQR_JL_Pos (20U)
-#define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
-#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
-#define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
-#define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
-
-/******************* Bit definition for ADC_JDR1 register *******************/
-#define ADC_JDR1_JDATA_Pos (0U)
-#define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
-
-/******************* Bit definition for ADC_JDR2 register *******************/
-#define ADC_JDR2_JDATA_Pos (0U)
-#define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
-
-/******************* Bit definition for ADC_JDR3 register *******************/
-#define ADC_JDR3_JDATA_Pos (0U)
-#define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
-
-/******************* Bit definition for ADC_JDR4 register *******************/
-#define ADC_JDR4_JDATA_Pos (0U)
-#define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
-
-/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_DATA_Pos (0U)
-#define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
-#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
-#define ADC_DR_ADC2DATA_Pos (16U)
-#define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
-#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
-
-
-/*****************************************************************************/
-/* */
-/* Timers (TIM) */
-/* */
-/*****************************************************************************/
-/******************* Bit definition for TIM_CR1 register *******************/
-#define TIM_CR1_CEN_Pos (0U)
-#define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
-#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos (1U)
-#define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
-#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
-#define TIM_CR1_URS_Pos (2U)
-#define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
-#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
-#define TIM_CR1_OPM_Pos (3U)
-#define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
-#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos (4U)
-#define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
-#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
-
-#define TIM_CR1_CMS_Pos (5U)
-#define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
-#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
-#define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos (7U)
-#define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
-#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos (8U)
-#define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
-#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
-#define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
-
-/******************* Bit definition for TIM_CR2 register *******************/
-#define TIM_CR2_CCPC_Pos (0U)
-#define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
-#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS_Pos (2U)
-#define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
-#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS_Pos (3U)
-#define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
-#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos (4U)
-#define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
-#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
-#define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
-#define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos (7U)
-#define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
-#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
-#define TIM_CR2_OIS1_Pos (8U)
-#define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
-#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N_Pos (9U)
-#define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
-#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2_Pos (10U)
-#define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
-#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N_Pos (11U)
-#define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
-#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3_Pos (12U)
-#define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
-#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N_Pos (13U)
-#define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
-#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4_Pos (14U)
-#define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
-#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
-
-/******************* Bit definition for TIM_SMCR register ******************/
-#define TIM_SMCR_SMS_Pos (0U)
-#define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
-#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
-
-#define TIM_SMCR_TS_Pos (4U)
-#define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
-#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
-#define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
-#define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
-
-#define TIM_SMCR_MSM_Pos (7U)
-#define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
-#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos (8U)
-#define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
-#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos (12U)
-#define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
-#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos (14U)
-#define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
-#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos (15U)
-#define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
-#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
-
-/******************* Bit definition for TIM_DIER register ******************/
-#define TIM_DIER_UIE_Pos (0U)
-#define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
-#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos (1U)
-#define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
-#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos (2U)
-#define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
-#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos (3U)
-#define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
-#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos (4U)
-#define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
-#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE_Pos (5U)
-#define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
-#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
-#define TIM_DIER_TIE_Pos (6U)
-#define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
-#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
-#define TIM_DIER_BIE_Pos (7U)
-#define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
-#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
-#define TIM_DIER_UDE_Pos (8U)
-#define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
-#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos (9U)
-#define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
-#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos (10U)
-#define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
-#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos (11U)
-#define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
-#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos (12U)
-#define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
-#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE_Pos (13U)
-#define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
-#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos (14U)
-#define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
-#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
-
-/******************** Bit definition for TIM_SR register *******************/
-#define TIM_SR_UIF_Pos (0U)
-#define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
-#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos (1U)
-#define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
-#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos (2U)
-#define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
-#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos (3U)
-#define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
-#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos (4U)
-#define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
-#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF_Pos (5U)
-#define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
-#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
-#define TIM_SR_TIF_Pos (6U)
-#define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
-#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF_Pos (7U)
-#define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
-#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
-#define TIM_SR_CC1OF_Pos (9U)
-#define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
-#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos (10U)
-#define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
-#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos (11U)
-#define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
-#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos (12U)
-#define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
-#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
-
-/******************* Bit definition for TIM_EGR register *******************/
-#define TIM_EGR_UG_Pos (0U)
-#define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
-#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos (1U)
-#define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
-#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos (2U)
-#define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
-#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos (3U)
-#define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
-#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos (4U)
-#define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
-#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG_Pos (5U)
-#define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
-#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG_Pos (6U)
-#define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
-#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
-#define TIM_EGR_BG_Pos (7U)
-#define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
-#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
-
-/****************** Bit definition for TIM_CCMR1 register ******************/
-#define TIM_CCMR1_CC1S_Pos (0U)
-#define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos (2U)
-#define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos (3U)
-#define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos (4U)
-#define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
-
-#define TIM_CCMR1_OC1CE_Pos (7U)
-#define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos (8U)
-#define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos (10U)
-#define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos (11U)
-#define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos (12U)
-#define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
-
-#define TIM_CCMR1_OC2CE_Pos (15U)
-#define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
-
-/*---------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos (2U)
-#define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos (4U)
-#define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos (10U)
-#define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos (12U)
-#define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
-
-/****************** Bit definition for TIM_CCMR2 register ******************/
-#define TIM_CCMR2_CC3S_Pos (0U)
-#define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos (2U)
-#define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos (3U)
-#define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos (4U)
-#define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
-
-#define TIM_CCMR2_OC3CE_Pos (7U)
-#define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos (8U)
-#define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos (10U)
-#define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos (11U)
-#define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos (12U)
-#define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
-
-#define TIM_CCMR2_OC4CE_Pos (15U)
-#define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
-
-/*---------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos (2U)
-#define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos (4U)
-#define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos (10U)
-#define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos (12U)
-#define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
-
-/******************* Bit definition for TIM_CCER register ******************/
-#define TIM_CCER_CC1E_Pos (0U)
-#define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
-#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos (1U)
-#define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
-#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE_Pos (2U)
-#define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
-#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP_Pos (3U)
-#define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
-#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos (4U)
-#define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
-#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos (5U)
-#define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
-#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE_Pos (6U)
-#define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
-#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP_Pos (7U)
-#define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
-#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos (8U)
-#define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
-#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos (9U)
-#define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
-#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE_Pos (10U)
-#define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
-#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP_Pos (11U)
-#define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
-#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos (12U)
-#define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
-#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos (13U)
-#define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
-#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
-
-/******************* Bit definition for TIM_CNT register *******************/
-#define TIM_CNT_CNT_Pos (0U)
-#define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
-
-/******************* Bit definition for TIM_PSC register *******************/
-#define TIM_PSC_PSC_Pos (0U)
-#define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
-#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
-
-/******************* Bit definition for TIM_ARR register *******************/
-#define TIM_ARR_ARR_Pos (0U)
-#define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
-
-/******************* Bit definition for TIM_RCR register *******************/
-#define TIM_RCR_REP_Pos (0U)
-#define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
-#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
-
-/******************* Bit definition for TIM_CCR1 register ******************/
-#define TIM_CCR1_CCR1_Pos (0U)
-#define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
-
-/******************* Bit definition for TIM_CCR2 register ******************/
-#define TIM_CCR2_CCR2_Pos (0U)
-#define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
-
-/******************* Bit definition for TIM_CCR3 register ******************/
-#define TIM_CCR3_CCR3_Pos (0U)
-#define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
-
-/******************* Bit definition for TIM_CCR4 register ******************/
-#define TIM_CCR4_CCR4_Pos (0U)
-#define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
-
-/******************* Bit definition for TIM_BDTR register ******************/
-#define TIM_BDTR_DTG_Pos (0U)
-#define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
-#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
-#define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
-#define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
-#define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
-#define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
-#define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
-#define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
-#define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
-
-#define TIM_BDTR_LOCK_Pos (8U)
-#define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
-#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
-#define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
-
-#define TIM_BDTR_OSSI_Pos (10U)
-#define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
-#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR_Pos (11U)
-#define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
-#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE_Pos (12U)
-#define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
-#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
-#define TIM_BDTR_BKP_Pos (13U)
-#define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
-#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
-#define TIM_BDTR_AOE_Pos (14U)
-#define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
-#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
-#define TIM_BDTR_MOE_Pos (15U)
-#define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
-#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
-
-/******************* Bit definition for TIM_DCR register *******************/
-#define TIM_DCR_DBA_Pos (0U)
-#define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
-#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
-#define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
-#define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
-#define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
-#define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos (8U)
-#define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
-#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
-#define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
-#define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
-#define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
-#define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
-
-/******************* Bit definition for TIM_DMAR register ******************/
-#define TIM_DMAR_DMAB_Pos (0U)
-#define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
-
-/******************************************************************************/
-/* */
-/* Real-Time Clock */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for RTC_CRH register ********************/
-#define RTC_CRH_SECIE_Pos (0U)
-#define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
-#define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
-#define RTC_CRH_ALRIE_Pos (1U)
-#define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
-#define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
-#define RTC_CRH_OWIE_Pos (2U)
-#define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
-#define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
-
-/******************* Bit definition for RTC_CRL register ********************/
-#define RTC_CRL_SECF_Pos (0U)
-#define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
-#define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
-#define RTC_CRL_ALRF_Pos (1U)
-#define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
-#define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
-#define RTC_CRL_OWF_Pos (2U)
-#define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
-#define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
-#define RTC_CRL_RSF_Pos (3U)
-#define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
-#define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
-#define RTC_CRL_CNF_Pos (4U)
-#define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
-#define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
-#define RTC_CRL_RTOFF_Pos (5U)
-#define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
-#define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
-
-/******************* Bit definition for RTC_PRLH register *******************/
-#define RTC_PRLH_PRL_Pos (0U)
-#define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
-#define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
-
-/******************* Bit definition for RTC_PRLL register *******************/
-#define RTC_PRLL_PRL_Pos (0U)
-#define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
-#define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
-
-/******************* Bit definition for RTC_DIVH register *******************/
-#define RTC_DIVH_RTC_DIV_Pos (0U)
-#define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
-#define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
-
-/******************* Bit definition for RTC_DIVL register *******************/
-#define RTC_DIVL_RTC_DIV_Pos (0U)
-#define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
-#define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
-
-/******************* Bit definition for RTC_CNTH register *******************/
-#define RTC_CNTH_RTC_CNT_Pos (0U)
-#define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
-#define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
-
-/******************* Bit definition for RTC_CNTL register *******************/
-#define RTC_CNTL_RTC_CNT_Pos (0U)
-#define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
-#define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
-
-/******************* Bit definition for RTC_ALRH register *******************/
-#define RTC_ALRH_RTC_ALR_Pos (0U)
-#define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
-#define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
-
-/******************* Bit definition for RTC_ALRL register *******************/
-#define RTC_ALRL_RTC_ALR_Pos (0U)
-#define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
-#define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
-
-/******************************************************************************/
-/* */
-/* Independent WATCHDOG (IWDG) */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_KR_KEY_Pos (0U)
-#define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
-#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
-
-/******************* Bit definition for IWDG_PR register ********************/
-#define IWDG_PR_PR_Pos (0U)
-#define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
-#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
-#define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
-#define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
-
-/******************* Bit definition for IWDG_RLR register *******************/
-#define IWDG_RLR_RL_Pos (0U)
-#define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
-#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
-
-/******************* Bit definition for IWDG_SR register ********************/
-#define IWDG_SR_PVU_Pos (0U)
-#define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
-#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos (1U)
-#define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
-#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/* */
-/* Window WATCHDOG (WWDG) */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for WWDG_CR register ********************/
-#define WWDG_CR_T_Pos (0U)
-#define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
-#define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
-#define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
-#define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
-#define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
-#define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
-#define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
-#define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
-
-/* Legacy defines */
-#define WWDG_CR_T0 WWDG_CR_T_0
-#define WWDG_CR_T1 WWDG_CR_T_1
-#define WWDG_CR_T2 WWDG_CR_T_2
-#define WWDG_CR_T3 WWDG_CR_T_3
-#define WWDG_CR_T4 WWDG_CR_T_4
-#define WWDG_CR_T5 WWDG_CR_T_5
-#define WWDG_CR_T6 WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos (7U)
-#define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
-#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
-
-/******************* Bit definition for WWDG_CFR register *******************/
-#define WWDG_CFR_W_Pos (0U)
-#define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
-#define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
-#define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
-#define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
-#define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
-#define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
-#define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
-#define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
-
-/* Legacy defines */
-#define WWDG_CFR_W0 WWDG_CFR_W_0
-#define WWDG_CFR_W1 WWDG_CFR_W_1
-#define WWDG_CFR_W2 WWDG_CFR_W_2
-#define WWDG_CFR_W3 WWDG_CFR_W_3
-#define WWDG_CFR_W4 WWDG_CFR_W_4
-#define WWDG_CFR_W5 WWDG_CFR_W_5
-#define WWDG_CFR_W6 WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos (7U)
-#define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
-#define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
-
-/* Legacy defines */
-#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
-#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos (9U)
-#define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
-#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
-
-/******************* Bit definition for WWDG_SR register ********************/
-#define WWDG_SR_EWIF_Pos (0U)
-#define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
-#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/* */
-/* SD host Interface */
-/* */
-/******************************************************************************/
-
-/****************** Bit definition for SDIO_POWER register ******************/
-#define SDIO_POWER_PWRCTRL_Pos (0U)
-#define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
-#define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
-#define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
-#define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
-
-/****************** Bit definition for SDIO_CLKCR register ******************/
-#define SDIO_CLKCR_CLKDIV_Pos (0U)
-#define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
-#define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
-#define SDIO_CLKCR_CLKEN_Pos (8U)
-#define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
-#define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
-#define SDIO_CLKCR_PWRSAV_Pos (9U)
-#define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
-#define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
-#define SDIO_CLKCR_BYPASS_Pos (10U)
-#define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
-#define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
-
-#define SDIO_CLKCR_WIDBUS_Pos (11U)
-#define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
-#define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
-#define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
-
-#define SDIO_CLKCR_NEGEDGE_Pos (13U)
-#define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
-#define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
-#define SDIO_CLKCR_HWFC_EN_Pos (14U)
-#define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
-#define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
-
-/******************* Bit definition for SDIO_ARG register *******************/
-#define SDIO_ARG_CMDARG_Pos (0U)
-#define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
-
-/******************* Bit definition for SDIO_CMD register *******************/
-#define SDIO_CMD_CMDINDEX_Pos (0U)
-#define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
-#define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
-
-#define SDIO_CMD_WAITRESP_Pos (6U)
-#define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
-#define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
-#define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
-#define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
-
-#define SDIO_CMD_WAITINT_Pos (8U)
-#define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
-#define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
-#define SDIO_CMD_WAITPEND_Pos (9U)
-#define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
-#define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define SDIO_CMD_CPSMEN_Pos (10U)
-#define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
-#define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
-#define SDIO_CMD_SDIOSUSPEND_Pos (11U)
-#define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
-#define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
-#define SDIO_CMD_ENCMDCOMPL_Pos (12U)
-#define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
-#define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
-#define SDIO_CMD_NIEN_Pos (13U)
-#define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
-#define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
-#define SDIO_CMD_CEATACMD_Pos (14U)
-#define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
-#define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
-
-/***************** Bit definition for SDIO_RESPCMD register *****************/
-#define SDIO_RESPCMD_RESPCMD_Pos (0U)
-#define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
-#define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
-
-/****************** Bit definition for SDIO_RESP0 register ******************/
-#define SDIO_RESP0_CARDSTATUS0_Pos (0U)
-#define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
-
-/****************** Bit definition for SDIO_RESP1 register ******************/
-#define SDIO_RESP1_CARDSTATUS1_Pos (0U)
-#define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
-
-/****************** Bit definition for SDIO_RESP2 register ******************/
-#define SDIO_RESP2_CARDSTATUS2_Pos (0U)
-#define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
-
-/****************** Bit definition for SDIO_RESP3 register ******************/
-#define SDIO_RESP3_CARDSTATUS3_Pos (0U)
-#define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
-
-/****************** Bit definition for SDIO_RESP4 register ******************/
-#define SDIO_RESP4_CARDSTATUS4_Pos (0U)
-#define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
-
-/****************** Bit definition for SDIO_DTIMER register *****************/
-#define SDIO_DTIMER_DATATIME_Pos (0U)
-#define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
-
-/****************** Bit definition for SDIO_DLEN register *******************/
-#define SDIO_DLEN_DATALENGTH_Pos (0U)
-#define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
-#define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
-
-/****************** Bit definition for SDIO_DCTRL register ******************/
-#define SDIO_DCTRL_DTEN_Pos (0U)
-#define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
-#define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
-#define SDIO_DCTRL_DTDIR_Pos (1U)
-#define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
-#define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
-#define SDIO_DCTRL_DTMODE_Pos (2U)
-#define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
-#define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
-#define SDIO_DCTRL_DMAEN_Pos (3U)
-#define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
-#define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
-
-#define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
-#define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
-#define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
-#define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
-#define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
-#define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
-#define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
-
-#define SDIO_DCTRL_RWSTART_Pos (8U)
-#define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
-#define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
-#define SDIO_DCTRL_RWSTOP_Pos (9U)
-#define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
-#define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
-#define SDIO_DCTRL_RWMOD_Pos (10U)
-#define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
-#define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
-#define SDIO_DCTRL_SDIOEN_Pos (11U)
-#define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
-#define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
-
-/****************** Bit definition for SDIO_DCOUNT register *****************/
-#define SDIO_DCOUNT_DATACOUNT_Pos (0U)
-#define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
-#define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
-
-/****************** Bit definition for SDIO_STA register ********************/
-#define SDIO_STA_CCRCFAIL_Pos (0U)
-#define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
-#define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
-#define SDIO_STA_DCRCFAIL_Pos (1U)
-#define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
-#define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
-#define SDIO_STA_CTIMEOUT_Pos (2U)
-#define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
-#define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
-#define SDIO_STA_DTIMEOUT_Pos (3U)
-#define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
-#define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
-#define SDIO_STA_TXUNDERR_Pos (4U)
-#define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
-#define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
-#define SDIO_STA_RXOVERR_Pos (5U)
-#define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
-#define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
-#define SDIO_STA_CMDREND_Pos (6U)
-#define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
-#define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
-#define SDIO_STA_CMDSENT_Pos (7U)
-#define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
-#define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
-#define SDIO_STA_DATAEND_Pos (8U)
-#define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
-#define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
-#define SDIO_STA_STBITERR_Pos (9U)
-#define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
-#define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
-#define SDIO_STA_DBCKEND_Pos (10U)
-#define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
-#define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
-#define SDIO_STA_CMDACT_Pos (11U)
-#define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
-#define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
-#define SDIO_STA_TXACT_Pos (12U)
-#define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
-#define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
-#define SDIO_STA_RXACT_Pos (13U)
-#define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
-#define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
-#define SDIO_STA_TXFIFOHE_Pos (14U)
-#define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
-#define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define SDIO_STA_RXFIFOHF_Pos (15U)
-#define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
-#define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define SDIO_STA_TXFIFOF_Pos (16U)
-#define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
-#define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
-#define SDIO_STA_RXFIFOF_Pos (17U)
-#define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
-#define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
-#define SDIO_STA_TXFIFOE_Pos (18U)
-#define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
-#define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
-#define SDIO_STA_RXFIFOE_Pos (19U)
-#define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
-#define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
-#define SDIO_STA_TXDAVL_Pos (20U)
-#define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
-#define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
-#define SDIO_STA_RXDAVL_Pos (21U)
-#define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
-#define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
-#define SDIO_STA_SDIOIT_Pos (22U)
-#define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
-#define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
-#define SDIO_STA_CEATAEND_Pos (23U)
-#define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
-#define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
-
-/******************* Bit definition for SDIO_ICR register *******************/
-#define SDIO_ICR_CCRCFAILC_Pos (0U)
-#define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
-#define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
-#define SDIO_ICR_DCRCFAILC_Pos (1U)
-#define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
-#define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
-#define SDIO_ICR_CTIMEOUTC_Pos (2U)
-#define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
-#define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
-#define SDIO_ICR_DTIMEOUTC_Pos (3U)
-#define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
-#define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
-#define SDIO_ICR_TXUNDERRC_Pos (4U)
-#define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
-#define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
-#define SDIO_ICR_RXOVERRC_Pos (5U)
-#define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
-#define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
-#define SDIO_ICR_CMDRENDC_Pos (6U)
-#define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
-#define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
-#define SDIO_ICR_CMDSENTC_Pos (7U)
-#define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
-#define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
-#define SDIO_ICR_DATAENDC_Pos (8U)
-#define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
-#define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
-#define SDIO_ICR_STBITERRC_Pos (9U)
-#define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
-#define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
-#define SDIO_ICR_DBCKENDC_Pos (10U)
-#define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
-#define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
-#define SDIO_ICR_SDIOITC_Pos (22U)
-#define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
-#define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
-#define SDIO_ICR_CEATAENDC_Pos (23U)
-#define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
-#define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
-
-/****************** Bit definition for SDIO_MASK register *******************/
-#define SDIO_MASK_CCRCFAILIE_Pos (0U)
-#define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
-#define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
-#define SDIO_MASK_DCRCFAILIE_Pos (1U)
-#define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
-#define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
-#define SDIO_MASK_CTIMEOUTIE_Pos (2U)
-#define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
-#define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
-#define SDIO_MASK_DTIMEOUTIE_Pos (3U)
-#define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
-#define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
-#define SDIO_MASK_TXUNDERRIE_Pos (4U)
-#define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
-#define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
-#define SDIO_MASK_RXOVERRIE_Pos (5U)
-#define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
-#define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
-#define SDIO_MASK_CMDRENDIE_Pos (6U)
-#define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
-#define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
-#define SDIO_MASK_CMDSENTIE_Pos (7U)
-#define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
-#define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
-#define SDIO_MASK_DATAENDIE_Pos (8U)
-#define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
-#define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
-#define SDIO_MASK_STBITERRIE_Pos (9U)
-#define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
-#define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
-#define SDIO_MASK_DBCKENDIE_Pos (10U)
-#define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
-#define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
-#define SDIO_MASK_CMDACTIE_Pos (11U)
-#define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
-#define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
-#define SDIO_MASK_TXACTIE_Pos (12U)
-#define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
-#define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
-#define SDIO_MASK_RXACTIE_Pos (13U)
-#define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
-#define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
-#define SDIO_MASK_TXFIFOHEIE_Pos (14U)
-#define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
-#define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOHFIE_Pos (15U)
-#define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
-#define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
-#define SDIO_MASK_TXFIFOFIE_Pos (16U)
-#define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
-#define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
-#define SDIO_MASK_RXFIFOFIE_Pos (17U)
-#define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
-#define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
-#define SDIO_MASK_TXFIFOEIE_Pos (18U)
-#define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
-#define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
-#define SDIO_MASK_RXFIFOEIE_Pos (19U)
-#define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
-#define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
-#define SDIO_MASK_TXDAVLIE_Pos (20U)
-#define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
-#define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
-#define SDIO_MASK_RXDAVLIE_Pos (21U)
-#define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
-#define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
-#define SDIO_MASK_SDIOITIE_Pos (22U)
-#define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
-#define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
-#define SDIO_MASK_CEATAENDIE_Pos (23U)
-#define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
-#define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
-
-/***************** Bit definition for SDIO_FIFOCNT register *****************/
-#define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
-#define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
-#define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
-
-/****************** Bit definition for SDIO_FIFO register *******************/
-#define SDIO_FIFO_FIFODATA_Pos (0U)
-#define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
-
-/******************************************************************************/
-/* */
-/* USB Device FS */
-/* */
-/******************************************************************************/
-
-/*!< Endpoint-specific registers */
-#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
-#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
-#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
-#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
-#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
-#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
-#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
-#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
-
-/* bit positions */
-#define USB_EP_CTR_RX_Pos (15U)
-#define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos (14U)
-#define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos (12U)
-#define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
-#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos (11U)
-#define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos (9U)
-#define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
-#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
-#define USB_EP_KIND_Pos (8U)
-#define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
-#define USB_EP_CTR_TX_Pos (7U)
-#define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos (6U)
-#define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos (4U)
-#define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
-#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos (0U)
-#define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
-#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
- /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos (9U)
-#define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */
-#define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
-
-#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
- /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */
-#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
- /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/******************* Bit definition for USB_EP0R register *******************/
-#define USB_EP0R_EA_Pos (0U)
-#define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos (4U)
-#define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos (6U)
-#define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos (7U)
-#define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos (8U)
-#define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos (9U)
-#define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos (11U)
-#define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos (12U)
-#define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos (14U)
-#define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos (15U)
-#define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP1R register *******************/
-#define USB_EP1R_EA_Pos (0U)
-#define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos (4U)
-#define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos (6U)
-#define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos (7U)
-#define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos (8U)
-#define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos (9U)
-#define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos (11U)
-#define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos (12U)
-#define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos (14U)
-#define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos (15U)
-#define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP2R register *******************/
-#define USB_EP2R_EA_Pos (0U)
-#define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos (4U)
-#define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos (6U)
-#define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos (7U)
-#define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos (8U)
-#define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos (9U)
-#define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos (11U)
-#define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos (12U)
-#define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos (14U)
-#define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos (15U)
-#define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP3R register *******************/
-#define USB_EP3R_EA_Pos (0U)
-#define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos (4U)
-#define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos (6U)
-#define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos (7U)
-#define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos (8U)
-#define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos (9U)
-#define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos (11U)
-#define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos (12U)
-#define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos (14U)
-#define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos (15U)
-#define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP4R register *******************/
-#define USB_EP4R_EA_Pos (0U)
-#define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos (4U)
-#define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos (6U)
-#define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos (7U)
-#define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos (8U)
-#define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos (9U)
-#define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos (11U)
-#define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos (12U)
-#define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos (14U)
-#define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos (15U)
-#define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP5R register *******************/
-#define USB_EP5R_EA_Pos (0U)
-#define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos (4U)
-#define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos (6U)
-#define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos (7U)
-#define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos (8U)
-#define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos (9U)
-#define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos (11U)
-#define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos (12U)
-#define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos (14U)
-#define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos (15U)
-#define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP6R register *******************/
-#define USB_EP6R_EA_Pos (0U)
-#define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos (4U)
-#define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos (6U)
-#define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos (7U)
-#define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos (8U)
-#define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos (9U)
-#define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos (11U)
-#define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos (12U)
-#define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos (14U)
-#define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos (15U)
-#define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/******************* Bit definition for USB_EP7R register *******************/
-#define USB_EP7R_EA_Pos (0U)
-#define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */
-#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos (4U)
-#define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos (6U)
-#define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos (7U)
-#define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos (8U)
-#define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos (9U)
-#define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos (11U)
-#define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
-#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos (12U)
-#define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos (14U)
-#define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos (15U)
-#define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */
-
-/*!< Common registers */
-/******************* Bit definition for USB_CNTR register *******************/
-#define USB_CNTR_FRES_Pos (0U)
-#define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
-#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */
-#define USB_CNTR_PDWN_Pos (1U)
-#define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
-#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */
-#define USB_CNTR_LP_MODE_Pos (2U)
-#define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
-#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */
-#define USB_CNTR_FSUSP_Pos (3U)
-#define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
-#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */
-#define USB_CNTR_RESUME_Pos (4U)
-#define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
-#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */
-#define USB_CNTR_ESOFM_Pos (8U)
-#define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
-#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos (9U)
-#define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
-#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos (10U)
-#define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
-#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos (11U)
-#define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
-#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos (12U)
-#define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
-#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos (13U)
-#define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
-#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos (14U)
-#define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos (15U)
-#define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
-#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */
-
-/******************* Bit definition for USB_ISTR register *******************/
-#define USB_ISTR_EP_ID_Pos (0U)
-#define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
-#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */
-#define USB_ISTR_DIR_Pos (4U)
-#define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
-#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */
-#define USB_ISTR_ESOF_Pos (8U)
-#define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
-#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos (9U)
-#define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
-#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */
-#define USB_ISTR_RESET_Pos (10U)
-#define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
-#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */
-#define USB_ISTR_SUSP_Pos (11U)
-#define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
-#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */
-#define USB_ISTR_WKUP_Pos (12U)
-#define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
-#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */
-#define USB_ISTR_ERR_Pos (13U)
-#define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
-#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */
-#define USB_ISTR_PMAOVR_Pos (14U)
-#define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos (15U)
-#define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
-#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */
-
-/******************* Bit definition for USB_FNR register ********************/
-#define USB_FNR_FN_Pos (0U)
-#define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */
-#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */
-#define USB_FNR_LSOF_Pos (11U)
-#define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
-#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */
-#define USB_FNR_LCK_Pos (13U)
-#define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */
-#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */
-#define USB_FNR_RXDM_Pos (14U)
-#define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
-#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos (15U)
-#define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
-#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */
-
-/****************** Bit definition for USB_DADDR register *******************/
-#define USB_DADDR_ADD_Pos (0U)
-#define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
-#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos (0U)
-#define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
-#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */
-#define USB_DADDR_ADD1_Pos (1U)
-#define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
-#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */
-#define USB_DADDR_ADD2_Pos (2U)
-#define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
-#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */
-#define USB_DADDR_ADD3_Pos (3U)
-#define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
-#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */
-#define USB_DADDR_ADD4_Pos (4U)
-#define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
-#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */
-#define USB_DADDR_ADD5_Pos (5U)
-#define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
-#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */
-#define USB_DADDR_ADD6_Pos (6U)
-#define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
-#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */
-
-#define USB_DADDR_EF_Pos (7U)
-#define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */
-#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */
-
-/****************** Bit definition for USB_BTABLE register ******************/
-#define USB_BTABLE_BTABLE_Pos (3U)
-#define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */
-
-/*!< Buffer descriptor table */
-/***************** Bit definition for USB_ADDR0_TX register *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
-#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
-
-/***************** Bit definition for USB_ADDR1_TX register *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
-#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
-
-/***************** Bit definition for USB_ADDR2_TX register *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
-#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
-
-/***************** Bit definition for USB_ADDR3_TX register *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
-#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
-
-/***************** Bit definition for USB_ADDR4_TX register *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
-#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
-
-/***************** Bit definition for USB_ADDR5_TX register *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
-#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
-
-/***************** Bit definition for USB_ADDR6_TX register *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
-#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
-
-/***************** Bit definition for USB_ADDR7_TX register *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
-#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/***************** Bit definition for USB_COUNT0_TX register ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
-#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
-
-/***************** Bit definition for USB_COUNT1_TX register ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
-#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
-
-/***************** Bit definition for USB_COUNT2_TX register ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
-#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
-
-/***************** Bit definition for USB_COUNT3_TX register ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
-#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
-
-/***************** Bit definition for USB_COUNT4_TX register ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
-#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
-
-/***************** Bit definition for USB_COUNT5_TX register ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
-#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
-
-/***************** Bit definition for USB_COUNT6_TX register ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
-#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
-
-/***************** Bit definition for USB_COUNT7_TX register ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
-#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */
-
-/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */
-
-/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */
-
-/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */
-
-/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */
-
-/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */
-
-/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */
-
-/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */
-
-/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */
-
-/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */
-
-/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */
-
-/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */
-
-/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */
-
-/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */
-
-/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */
-
-/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/***************** Bit definition for USB_ADDR0_RX register *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
-#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
-
-/***************** Bit definition for USB_ADDR1_RX register *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
-#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
-
-/***************** Bit definition for USB_ADDR2_RX register *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
-#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
-
-/***************** Bit definition for USB_ADDR3_RX register *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
-#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
-
-/***************** Bit definition for USB_ADDR4_RX register *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
-#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
-
-/***************** Bit definition for USB_ADDR5_RX register *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
-#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
-
-/***************** Bit definition for USB_ADDR6_RX register *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
-#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
-
-/***************** Bit definition for USB_ADDR7_RX register *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
-#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/***************** Bit definition for USB_COUNT0_RX register ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
-#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos (15U)
-#define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT1_RX register ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
-#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos (15U)
-#define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT2_RX register ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
-#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos (15U)
-#define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT3_RX register ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
-#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos (15U)
-#define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT4_RX register ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
-#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos (15U)
-#define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT5_RX register ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
-#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos (15U)
-#define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT6_RX register ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
-#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos (15U)
-#define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/***************** Bit definition for USB_COUNT7_RX register ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
-#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
-#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos (15U)
-#define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
-
-/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
-
-#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/* */
-/* Controller Area Network */
-/* */
-/******************************************************************************/
-
-/*!< CAN control and status registers */
-/******************* Bit definition for CAN_MCR register ********************/
-#define CAN_MCR_INRQ_Pos (0U)
-#define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
-#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */
-#define CAN_MCR_SLEEP_Pos (1U)
-#define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
-#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */
-#define CAN_MCR_TXFP_Pos (2U)
-#define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
-#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */
-#define CAN_MCR_RFLM_Pos (3U)
-#define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
-#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */
-#define CAN_MCR_NART_Pos (4U)
-#define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
-#define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */
-#define CAN_MCR_AWUM_Pos (5U)
-#define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
-#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */
-#define CAN_MCR_ABOM_Pos (6U)
-#define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
-#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */
-#define CAN_MCR_TTCM_Pos (7U)
-#define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
-#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */
-#define CAN_MCR_RESET_Pos (15U)
-#define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
-#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */
-#define CAN_MCR_DBF_Pos (16U)
-#define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
-#define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */
-
-/******************* Bit definition for CAN_MSR register ********************/
-#define CAN_MSR_INAK_Pos (0U)
-#define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
-#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */
-#define CAN_MSR_SLAK_Pos (1U)
-#define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
-#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */
-#define CAN_MSR_ERRI_Pos (2U)
-#define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
-#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */
-#define CAN_MSR_WKUI_Pos (3U)
-#define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
-#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */
-#define CAN_MSR_SLAKI_Pos (4U)
-#define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
-#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */
-#define CAN_MSR_TXM_Pos (8U)
-#define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
-#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */
-#define CAN_MSR_RXM_Pos (9U)
-#define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
-#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */
-#define CAN_MSR_SAMP_Pos (10U)
-#define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
-#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */
-#define CAN_MSR_RX_Pos (11U)
-#define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
-#define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */
-
-/******************* Bit definition for CAN_TSR register ********************/
-#define CAN_TSR_RQCP0_Pos (0U)
-#define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
-#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */
-#define CAN_TSR_TXOK0_Pos (1U)
-#define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
-#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */
-#define CAN_TSR_ALST0_Pos (2U)
-#define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
-#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */
-#define CAN_TSR_TERR0_Pos (3U)
-#define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
-#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */
-#define CAN_TSR_ABRQ0_Pos (7U)
-#define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
-#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */
-#define CAN_TSR_RQCP1_Pos (8U)
-#define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
-#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */
-#define CAN_TSR_TXOK1_Pos (9U)
-#define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
-#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */
-#define CAN_TSR_ALST1_Pos (10U)
-#define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
-#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */
-#define CAN_TSR_TERR1_Pos (11U)
-#define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
-#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */
-#define CAN_TSR_ABRQ1_Pos (15U)
-#define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
-#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */
-#define CAN_TSR_RQCP2_Pos (16U)
-#define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
-#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */
-#define CAN_TSR_TXOK2_Pos (17U)
-#define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
-#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */
-#define CAN_TSR_ALST2_Pos (18U)
-#define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
-#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */
-#define CAN_TSR_TERR2_Pos (19U)
-#define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
-#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */
-#define CAN_TSR_ABRQ2_Pos (23U)
-#define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
-#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */
-#define CAN_TSR_CODE_Pos (24U)
-#define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
-#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */
-
-#define CAN_TSR_TME_Pos (26U)
-#define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
-#define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */
-#define CAN_TSR_TME0_Pos (26U)
-#define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
-#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */
-#define CAN_TSR_TME1_Pos (27U)
-#define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
-#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */
-#define CAN_TSR_TME2_Pos (28U)
-#define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
-#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */
-
-#define CAN_TSR_LOW_Pos (29U)
-#define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
-#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */
-#define CAN_TSR_LOW0_Pos (29U)
-#define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
-#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */
-#define CAN_TSR_LOW1_Pos (30U)
-#define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
-#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */
-#define CAN_TSR_LOW2_Pos (31U)
-#define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
-#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */
-
-/******************* Bit definition for CAN_RF0R register *******************/
-#define CAN_RF0R_FMP0_Pos (0U)
-#define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
-#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */
-#define CAN_RF0R_FULL0_Pos (3U)
-#define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
-#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */
-#define CAN_RF0R_FOVR0_Pos (4U)
-#define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
-#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */
-#define CAN_RF0R_RFOM0_Pos (5U)
-#define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
-#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */
-
-/******************* Bit definition for CAN_RF1R register *******************/
-#define CAN_RF1R_FMP1_Pos (0U)
-#define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
-#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */
-#define CAN_RF1R_FULL1_Pos (3U)
-#define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
-#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */
-#define CAN_RF1R_FOVR1_Pos (4U)
-#define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
-#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */
-#define CAN_RF1R_RFOM1_Pos (5U)
-#define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
-#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */
-
-/******************** Bit definition for CAN_IER register *******************/
-#define CAN_IER_TMEIE_Pos (0U)
-#define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
-#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */
-#define CAN_IER_FMPIE0_Pos (1U)
-#define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
-#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE0_Pos (2U)
-#define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
-#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE0_Pos (3U)
-#define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
-#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */
-#define CAN_IER_FMPIE1_Pos (4U)
-#define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
-#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE1_Pos (5U)
-#define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
-#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE1_Pos (6U)
-#define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
-#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */
-#define CAN_IER_EWGIE_Pos (8U)
-#define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
-#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */
-#define CAN_IER_EPVIE_Pos (9U)
-#define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
-#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */
-#define CAN_IER_BOFIE_Pos (10U)
-#define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
-#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */
-#define CAN_IER_LECIE_Pos (11U)
-#define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
-#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */
-#define CAN_IER_ERRIE_Pos (15U)
-#define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
-#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */
-#define CAN_IER_WKUIE_Pos (16U)
-#define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
-#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */
-#define CAN_IER_SLKIE_Pos (17U)
-#define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
-#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */
-
-/******************** Bit definition for CAN_ESR register *******************/
-#define CAN_ESR_EWGF_Pos (0U)
-#define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
-#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */
-#define CAN_ESR_EPVF_Pos (1U)
-#define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
-#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */
-#define CAN_ESR_BOFF_Pos (2U)
-#define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
-#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */
-
-#define CAN_ESR_LEC_Pos (4U)
-#define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
-#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */
-#define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
-#define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
-#define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
-
-#define CAN_ESR_TEC_Pos (16U)
-#define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
-#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */
-#define CAN_ESR_REC_Pos (24U)
-#define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
-#define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */
-
-/******************* Bit definition for CAN_BTR register ********************/
-#define CAN_BTR_BRP_Pos (0U)
-#define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
-#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
-#define CAN_BTR_TS1_Pos (16U)
-#define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
-#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
-#define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
-#define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
-#define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
-#define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
-#define CAN_BTR_TS2_Pos (20U)
-#define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
-#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
-#define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
-#define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
-#define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
-#define CAN_BTR_SJW_Pos (24U)
-#define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
-#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
-#define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
-#define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
-#define CAN_BTR_LBKM_Pos (30U)
-#define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
-#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
-#define CAN_BTR_SILM_Pos (31U)
-#define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
-#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
-
-/*!< Mailbox registers */
-/****************** Bit definition for CAN_TI0R register ********************/
-#define CAN_TI0R_TXRQ_Pos (0U)
-#define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
-#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */
-#define CAN_TI0R_RTR_Pos (1U)
-#define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
-#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */
-#define CAN_TI0R_IDE_Pos (2U)
-#define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
-#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */
-#define CAN_TI0R_EXID_Pos (3U)
-#define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
-#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */
-#define CAN_TI0R_STID_Pos (21U)
-#define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
-#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
-
-/****************** Bit definition for CAN_TDT0R register *******************/
-#define CAN_TDT0R_DLC_Pos (0U)
-#define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
-#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */
-#define CAN_TDT0R_TGT_Pos (8U)
-#define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
-#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */
-#define CAN_TDT0R_TIME_Pos (16U)
-#define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
-#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */
-
-/****************** Bit definition for CAN_TDL0R register *******************/
-#define CAN_TDL0R_DATA0_Pos (0U)
-#define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
-#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */
-#define CAN_TDL0R_DATA1_Pos (8U)
-#define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
-#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */
-#define CAN_TDL0R_DATA2_Pos (16U)
-#define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
-#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */
-#define CAN_TDL0R_DATA3_Pos (24U)
-#define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
-#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */
-
-/****************** Bit definition for CAN_TDH0R register *******************/
-#define CAN_TDH0R_DATA4_Pos (0U)
-#define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
-#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */
-#define CAN_TDH0R_DATA5_Pos (8U)
-#define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
-#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */
-#define CAN_TDH0R_DATA6_Pos (16U)
-#define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
-#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */
-#define CAN_TDH0R_DATA7_Pos (24U)
-#define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
-#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */
-
-/******************* Bit definition for CAN_TI1R register *******************/
-#define CAN_TI1R_TXRQ_Pos (0U)
-#define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
-#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */
-#define CAN_TI1R_RTR_Pos (1U)
-#define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
-#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */
-#define CAN_TI1R_IDE_Pos (2U)
-#define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
-#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */
-#define CAN_TI1R_EXID_Pos (3U)
-#define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
-#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */
-#define CAN_TI1R_STID_Pos (21U)
-#define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
-#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_TDT1R register ******************/
-#define CAN_TDT1R_DLC_Pos (0U)
-#define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
-#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */
-#define CAN_TDT1R_TGT_Pos (8U)
-#define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
-#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */
-#define CAN_TDT1R_TIME_Pos (16U)
-#define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
-#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */
-
-/******************* Bit definition for CAN_TDL1R register ******************/
-#define CAN_TDL1R_DATA0_Pos (0U)
-#define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
-#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */
-#define CAN_TDL1R_DATA1_Pos (8U)
-#define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
-#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */
-#define CAN_TDL1R_DATA2_Pos (16U)
-#define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
-#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */
-#define CAN_TDL1R_DATA3_Pos (24U)
-#define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
-#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */
-
-/******************* Bit definition for CAN_TDH1R register ******************/
-#define CAN_TDH1R_DATA4_Pos (0U)
-#define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
-#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */
-#define CAN_TDH1R_DATA5_Pos (8U)
-#define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
-#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */
-#define CAN_TDH1R_DATA6_Pos (16U)
-#define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
-#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */
-#define CAN_TDH1R_DATA7_Pos (24U)
-#define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
-#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */
-
-/******************* Bit definition for CAN_TI2R register *******************/
-#define CAN_TI2R_TXRQ_Pos (0U)
-#define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
-#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */
-#define CAN_TI2R_RTR_Pos (1U)
-#define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
-#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */
-#define CAN_TI2R_IDE_Pos (2U)
-#define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
-#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */
-#define CAN_TI2R_EXID_Pos (3U)
-#define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
-#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */
-#define CAN_TI2R_STID_Pos (21U)
-#define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
-#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_TDT2R register ******************/
-#define CAN_TDT2R_DLC_Pos (0U)
-#define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
-#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */
-#define CAN_TDT2R_TGT_Pos (8U)
-#define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
-#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */
-#define CAN_TDT2R_TIME_Pos (16U)
-#define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
-#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */
-
-/******************* Bit definition for CAN_TDL2R register ******************/
-#define CAN_TDL2R_DATA0_Pos (0U)
-#define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
-#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */
-#define CAN_TDL2R_DATA1_Pos (8U)
-#define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
-#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */
-#define CAN_TDL2R_DATA2_Pos (16U)
-#define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
-#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */
-#define CAN_TDL2R_DATA3_Pos (24U)
-#define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
-#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */
-
-/******************* Bit definition for CAN_TDH2R register ******************/
-#define CAN_TDH2R_DATA4_Pos (0U)
-#define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
-#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */
-#define CAN_TDH2R_DATA5_Pos (8U)
-#define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
-#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */
-#define CAN_TDH2R_DATA6_Pos (16U)
-#define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
-#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */
-#define CAN_TDH2R_DATA7_Pos (24U)
-#define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
-#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */
-
-/******************* Bit definition for CAN_RI0R register *******************/
-#define CAN_RI0R_RTR_Pos (1U)
-#define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
-#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */
-#define CAN_RI0R_IDE_Pos (2U)
-#define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
-#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */
-#define CAN_RI0R_EXID_Pos (3U)
-#define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
-#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */
-#define CAN_RI0R_STID_Pos (21U)
-#define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
-#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_RDT0R register ******************/
-#define CAN_RDT0R_DLC_Pos (0U)
-#define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
-#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */
-#define CAN_RDT0R_FMI_Pos (8U)
-#define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
-#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */
-#define CAN_RDT0R_TIME_Pos (16U)
-#define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
-#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */
-
-/******************* Bit definition for CAN_RDL0R register ******************/
-#define CAN_RDL0R_DATA0_Pos (0U)
-#define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
-#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */
-#define CAN_RDL0R_DATA1_Pos (8U)
-#define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
-#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */
-#define CAN_RDL0R_DATA2_Pos (16U)
-#define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
-#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */
-#define CAN_RDL0R_DATA3_Pos (24U)
-#define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
-#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */
-
-/******************* Bit definition for CAN_RDH0R register ******************/
-#define CAN_RDH0R_DATA4_Pos (0U)
-#define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
-#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */
-#define CAN_RDH0R_DATA5_Pos (8U)
-#define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
-#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */
-#define CAN_RDH0R_DATA6_Pos (16U)
-#define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
-#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */
-#define CAN_RDH0R_DATA7_Pos (24U)
-#define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
-#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */
-
-/******************* Bit definition for CAN_RI1R register *******************/
-#define CAN_RI1R_RTR_Pos (1U)
-#define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
-#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */
-#define CAN_RI1R_IDE_Pos (2U)
-#define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
-#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */
-#define CAN_RI1R_EXID_Pos (3U)
-#define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
-#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */
-#define CAN_RI1R_STID_Pos (21U)
-#define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
-#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_RDT1R register ******************/
-#define CAN_RDT1R_DLC_Pos (0U)
-#define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
-#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */
-#define CAN_RDT1R_FMI_Pos (8U)
-#define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
-#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */
-#define CAN_RDT1R_TIME_Pos (16U)
-#define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
-#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */
-
-/******************* Bit definition for CAN_RDL1R register ******************/
-#define CAN_RDL1R_DATA0_Pos (0U)
-#define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
-#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */
-#define CAN_RDL1R_DATA1_Pos (8U)
-#define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
-#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */
-#define CAN_RDL1R_DATA2_Pos (16U)
-#define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
-#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */
-#define CAN_RDL1R_DATA3_Pos (24U)
-#define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
-#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */
-
-/******************* Bit definition for CAN_RDH1R register ******************/
-#define CAN_RDH1R_DATA4_Pos (0U)
-#define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
-#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */
-#define CAN_RDH1R_DATA5_Pos (8U)
-#define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
-#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */
-#define CAN_RDH1R_DATA6_Pos (16U)
-#define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
-#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */
-#define CAN_RDH1R_DATA7_Pos (24U)
-#define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
-#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */
-
-/*!< CAN filter registers */
-/******************* Bit definition for CAN_FMR register ********************/
-#define CAN_FMR_FINIT_Pos (0U)
-#define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
-#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */
-#define CAN_FMR_CAN2SB_Pos (8U)
-#define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
-#define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */
-
-/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM_Pos (0U)
-#define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
-#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */
-#define CAN_FM1R_FBM0_Pos (0U)
-#define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
-#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */
-#define CAN_FM1R_FBM1_Pos (1U)
-#define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
-#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */
-#define CAN_FM1R_FBM2_Pos (2U)
-#define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
-#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */
-#define CAN_FM1R_FBM3_Pos (3U)
-#define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
-#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */
-#define CAN_FM1R_FBM4_Pos (4U)
-#define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
-#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */
-#define CAN_FM1R_FBM5_Pos (5U)
-#define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
-#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */
-#define CAN_FM1R_FBM6_Pos (6U)
-#define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
-#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */
-#define CAN_FM1R_FBM7_Pos (7U)
-#define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
-#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */
-#define CAN_FM1R_FBM8_Pos (8U)
-#define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
-#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */
-#define CAN_FM1R_FBM9_Pos (9U)
-#define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
-#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */
-#define CAN_FM1R_FBM10_Pos (10U)
-#define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
-#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */
-#define CAN_FM1R_FBM11_Pos (11U)
-#define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
-#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */
-#define CAN_FM1R_FBM12_Pos (12U)
-#define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
-#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */
-#define CAN_FM1R_FBM13_Pos (13U)
-#define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
-#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */
-
-/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC_Pos (0U)
-#define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
-#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */
-#define CAN_FS1R_FSC0_Pos (0U)
-#define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
-#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */
-#define CAN_FS1R_FSC1_Pos (1U)
-#define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
-#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */
-#define CAN_FS1R_FSC2_Pos (2U)
-#define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
-#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */
-#define CAN_FS1R_FSC3_Pos (3U)
-#define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
-#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */
-#define CAN_FS1R_FSC4_Pos (4U)
-#define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
-#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */
-#define CAN_FS1R_FSC5_Pos (5U)
-#define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
-#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */
-#define CAN_FS1R_FSC6_Pos (6U)
-#define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
-#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */
-#define CAN_FS1R_FSC7_Pos (7U)
-#define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
-#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */
-#define CAN_FS1R_FSC8_Pos (8U)
-#define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
-#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */
-#define CAN_FS1R_FSC9_Pos (9U)
-#define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
-#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */
-#define CAN_FS1R_FSC10_Pos (10U)
-#define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
-#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */
-#define CAN_FS1R_FSC11_Pos (11U)
-#define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
-#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */
-#define CAN_FS1R_FSC12_Pos (12U)
-#define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
-#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */
-#define CAN_FS1R_FSC13_Pos (13U)
-#define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
-#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */
-
-/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA_Pos (0U)
-#define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
-#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0_Pos (0U)
-#define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
-#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */
-#define CAN_FFA1R_FFA1_Pos (1U)
-#define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
-#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */
-#define CAN_FFA1R_FFA2_Pos (2U)
-#define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
-#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */
-#define CAN_FFA1R_FFA3_Pos (3U)
-#define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
-#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */
-#define CAN_FFA1R_FFA4_Pos (4U)
-#define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
-#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */
-#define CAN_FFA1R_FFA5_Pos (5U)
-#define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
-#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */
-#define CAN_FFA1R_FFA6_Pos (6U)
-#define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
-#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */
-#define CAN_FFA1R_FFA7_Pos (7U)
-#define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
-#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */
-#define CAN_FFA1R_FFA8_Pos (8U)
-#define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
-#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */
-#define CAN_FFA1R_FFA9_Pos (9U)
-#define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
-#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */
-#define CAN_FFA1R_FFA10_Pos (10U)
-#define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
-#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */
-#define CAN_FFA1R_FFA11_Pos (11U)
-#define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
-#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */
-#define CAN_FFA1R_FFA12_Pos (12U)
-#define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
-#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */
-#define CAN_FFA1R_FFA13_Pos (13U)
-#define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
-#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */
-
-/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT_Pos (0U)
-#define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
-#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */
-#define CAN_FA1R_FACT0_Pos (0U)
-#define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
-#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */
-#define CAN_FA1R_FACT1_Pos (1U)
-#define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
-#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */
-#define CAN_FA1R_FACT2_Pos (2U)
-#define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
-#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */
-#define CAN_FA1R_FACT3_Pos (3U)
-#define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
-#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */
-#define CAN_FA1R_FACT4_Pos (4U)
-#define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
-#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */
-#define CAN_FA1R_FACT5_Pos (5U)
-#define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
-#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */
-#define CAN_FA1R_FACT6_Pos (6U)
-#define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
-#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */
-#define CAN_FA1R_FACT7_Pos (7U)
-#define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
-#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */
-#define CAN_FA1R_FACT8_Pos (8U)
-#define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
-#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */
-#define CAN_FA1R_FACT9_Pos (9U)
-#define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
-#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */
-#define CAN_FA1R_FACT10_Pos (10U)
-#define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
-#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */
-#define CAN_FA1R_FACT11_Pos (11U)
-#define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
-#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */
-#define CAN_FA1R_FACT12_Pos (12U)
-#define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
-#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */
-#define CAN_FA1R_FACT13_Pos (13U)
-#define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
-#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */
-
-/******************* Bit definition for CAN_F0R1 register *******************/
-#define CAN_F0R1_FB0_Pos (0U)
-#define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F0R1_FB1_Pos (1U)
-#define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F0R1_FB2_Pos (2U)
-#define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F0R1_FB3_Pos (3U)
-#define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F0R1_FB4_Pos (4U)
-#define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F0R1_FB5_Pos (5U)
-#define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F0R1_FB6_Pos (6U)
-#define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F0R1_FB7_Pos (7U)
-#define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F0R1_FB8_Pos (8U)
-#define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F0R1_FB9_Pos (9U)
-#define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F0R1_FB10_Pos (10U)
-#define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F0R1_FB11_Pos (11U)
-#define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F0R1_FB12_Pos (12U)
-#define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F0R1_FB13_Pos (13U)
-#define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F0R1_FB14_Pos (14U)
-#define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F0R1_FB15_Pos (15U)
-#define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F0R1_FB16_Pos (16U)
-#define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F0R1_FB17_Pos (17U)
-#define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F0R1_FB18_Pos (18U)
-#define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F0R1_FB19_Pos (19U)
-#define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F0R1_FB20_Pos (20U)
-#define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F0R1_FB21_Pos (21U)
-#define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F0R1_FB22_Pos (22U)
-#define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F0R1_FB23_Pos (23U)
-#define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F0R1_FB24_Pos (24U)
-#define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F0R1_FB25_Pos (25U)
-#define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F0R1_FB26_Pos (26U)
-#define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F0R1_FB27_Pos (27U)
-#define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F0R1_FB28_Pos (28U)
-#define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F0R1_FB29_Pos (29U)
-#define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F0R1_FB30_Pos (30U)
-#define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F0R1_FB31_Pos (31U)
-#define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F1R1 register *******************/
-#define CAN_F1R1_FB0_Pos (0U)
-#define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F1R1_FB1_Pos (1U)
-#define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F1R1_FB2_Pos (2U)
-#define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F1R1_FB3_Pos (3U)
-#define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F1R1_FB4_Pos (4U)
-#define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F1R1_FB5_Pos (5U)
-#define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F1R1_FB6_Pos (6U)
-#define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F1R1_FB7_Pos (7U)
-#define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F1R1_FB8_Pos (8U)
-#define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F1R1_FB9_Pos (9U)
-#define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F1R1_FB10_Pos (10U)
-#define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F1R1_FB11_Pos (11U)
-#define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F1R1_FB12_Pos (12U)
-#define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F1R1_FB13_Pos (13U)
-#define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F1R1_FB14_Pos (14U)
-#define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F1R1_FB15_Pos (15U)
-#define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F1R1_FB16_Pos (16U)
-#define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F1R1_FB17_Pos (17U)
-#define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F1R1_FB18_Pos (18U)
-#define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F1R1_FB19_Pos (19U)
-#define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F1R1_FB20_Pos (20U)
-#define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F1R1_FB21_Pos (21U)
-#define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F1R1_FB22_Pos (22U)
-#define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F1R1_FB23_Pos (23U)
-#define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F1R1_FB24_Pos (24U)
-#define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F1R1_FB25_Pos (25U)
-#define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F1R1_FB26_Pos (26U)
-#define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F1R1_FB27_Pos (27U)
-#define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F1R1_FB28_Pos (28U)
-#define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F1R1_FB29_Pos (29U)
-#define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F1R1_FB30_Pos (30U)
-#define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F1R1_FB31_Pos (31U)
-#define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F2R1 register *******************/
-#define CAN_F2R1_FB0_Pos (0U)
-#define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F2R1_FB1_Pos (1U)
-#define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F2R1_FB2_Pos (2U)
-#define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F2R1_FB3_Pos (3U)
-#define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F2R1_FB4_Pos (4U)
-#define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F2R1_FB5_Pos (5U)
-#define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F2R1_FB6_Pos (6U)
-#define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F2R1_FB7_Pos (7U)
-#define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F2R1_FB8_Pos (8U)
-#define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F2R1_FB9_Pos (9U)
-#define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F2R1_FB10_Pos (10U)
-#define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F2R1_FB11_Pos (11U)
-#define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F2R1_FB12_Pos (12U)
-#define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F2R1_FB13_Pos (13U)
-#define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F2R1_FB14_Pos (14U)
-#define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F2R1_FB15_Pos (15U)
-#define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F2R1_FB16_Pos (16U)
-#define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F2R1_FB17_Pos (17U)
-#define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F2R1_FB18_Pos (18U)
-#define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F2R1_FB19_Pos (19U)
-#define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F2R1_FB20_Pos (20U)
-#define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F2R1_FB21_Pos (21U)
-#define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F2R1_FB22_Pos (22U)
-#define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F2R1_FB23_Pos (23U)
-#define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F2R1_FB24_Pos (24U)
-#define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F2R1_FB25_Pos (25U)
-#define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F2R1_FB26_Pos (26U)
-#define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F2R1_FB27_Pos (27U)
-#define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F2R1_FB28_Pos (28U)
-#define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F2R1_FB29_Pos (29U)
-#define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F2R1_FB30_Pos (30U)
-#define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F2R1_FB31_Pos (31U)
-#define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F3R1 register *******************/
-#define CAN_F3R1_FB0_Pos (0U)
-#define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F3R1_FB1_Pos (1U)
-#define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F3R1_FB2_Pos (2U)
-#define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F3R1_FB3_Pos (3U)
-#define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F3R1_FB4_Pos (4U)
-#define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F3R1_FB5_Pos (5U)
-#define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F3R1_FB6_Pos (6U)
-#define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F3R1_FB7_Pos (7U)
-#define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F3R1_FB8_Pos (8U)
-#define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F3R1_FB9_Pos (9U)
-#define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F3R1_FB10_Pos (10U)
-#define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F3R1_FB11_Pos (11U)
-#define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F3R1_FB12_Pos (12U)
-#define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F3R1_FB13_Pos (13U)
-#define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F3R1_FB14_Pos (14U)
-#define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F3R1_FB15_Pos (15U)
-#define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F3R1_FB16_Pos (16U)
-#define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F3R1_FB17_Pos (17U)
-#define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F3R1_FB18_Pos (18U)
-#define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F3R1_FB19_Pos (19U)
-#define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F3R1_FB20_Pos (20U)
-#define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F3R1_FB21_Pos (21U)
-#define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F3R1_FB22_Pos (22U)
-#define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F3R1_FB23_Pos (23U)
-#define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F3R1_FB24_Pos (24U)
-#define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F3R1_FB25_Pos (25U)
-#define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F3R1_FB26_Pos (26U)
-#define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F3R1_FB27_Pos (27U)
-#define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F3R1_FB28_Pos (28U)
-#define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F3R1_FB29_Pos (29U)
-#define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F3R1_FB30_Pos (30U)
-#define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F3R1_FB31_Pos (31U)
-#define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F4R1 register *******************/
-#define CAN_F4R1_FB0_Pos (0U)
-#define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F4R1_FB1_Pos (1U)
-#define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F4R1_FB2_Pos (2U)
-#define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F4R1_FB3_Pos (3U)
-#define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F4R1_FB4_Pos (4U)
-#define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F4R1_FB5_Pos (5U)
-#define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F4R1_FB6_Pos (6U)
-#define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F4R1_FB7_Pos (7U)
-#define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F4R1_FB8_Pos (8U)
-#define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F4R1_FB9_Pos (9U)
-#define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F4R1_FB10_Pos (10U)
-#define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F4R1_FB11_Pos (11U)
-#define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F4R1_FB12_Pos (12U)
-#define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F4R1_FB13_Pos (13U)
-#define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F4R1_FB14_Pos (14U)
-#define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F4R1_FB15_Pos (15U)
-#define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F4R1_FB16_Pos (16U)
-#define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F4R1_FB17_Pos (17U)
-#define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F4R1_FB18_Pos (18U)
-#define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F4R1_FB19_Pos (19U)
-#define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F4R1_FB20_Pos (20U)
-#define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F4R1_FB21_Pos (21U)
-#define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F4R1_FB22_Pos (22U)
-#define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F4R1_FB23_Pos (23U)
-#define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F4R1_FB24_Pos (24U)
-#define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F4R1_FB25_Pos (25U)
-#define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F4R1_FB26_Pos (26U)
-#define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F4R1_FB27_Pos (27U)
-#define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F4R1_FB28_Pos (28U)
-#define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F4R1_FB29_Pos (29U)
-#define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F4R1_FB30_Pos (30U)
-#define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F4R1_FB31_Pos (31U)
-#define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F5R1 register *******************/
-#define CAN_F5R1_FB0_Pos (0U)
-#define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F5R1_FB1_Pos (1U)
-#define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F5R1_FB2_Pos (2U)
-#define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F5R1_FB3_Pos (3U)
-#define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F5R1_FB4_Pos (4U)
-#define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F5R1_FB5_Pos (5U)
-#define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F5R1_FB6_Pos (6U)
-#define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F5R1_FB7_Pos (7U)
-#define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F5R1_FB8_Pos (8U)
-#define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F5R1_FB9_Pos (9U)
-#define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F5R1_FB10_Pos (10U)
-#define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F5R1_FB11_Pos (11U)
-#define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F5R1_FB12_Pos (12U)
-#define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F5R1_FB13_Pos (13U)
-#define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F5R1_FB14_Pos (14U)
-#define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F5R1_FB15_Pos (15U)
-#define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F5R1_FB16_Pos (16U)
-#define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F5R1_FB17_Pos (17U)
-#define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F5R1_FB18_Pos (18U)
-#define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F5R1_FB19_Pos (19U)
-#define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F5R1_FB20_Pos (20U)
-#define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F5R1_FB21_Pos (21U)
-#define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F5R1_FB22_Pos (22U)
-#define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F5R1_FB23_Pos (23U)
-#define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F5R1_FB24_Pos (24U)
-#define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F5R1_FB25_Pos (25U)
-#define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F5R1_FB26_Pos (26U)
-#define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F5R1_FB27_Pos (27U)
-#define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F5R1_FB28_Pos (28U)
-#define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F5R1_FB29_Pos (29U)
-#define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F5R1_FB30_Pos (30U)
-#define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F5R1_FB31_Pos (31U)
-#define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F6R1 register *******************/
-#define CAN_F6R1_FB0_Pos (0U)
-#define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F6R1_FB1_Pos (1U)
-#define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F6R1_FB2_Pos (2U)
-#define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F6R1_FB3_Pos (3U)
-#define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F6R1_FB4_Pos (4U)
-#define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F6R1_FB5_Pos (5U)
-#define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F6R1_FB6_Pos (6U)
-#define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F6R1_FB7_Pos (7U)
-#define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F6R1_FB8_Pos (8U)
-#define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F6R1_FB9_Pos (9U)
-#define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F6R1_FB10_Pos (10U)
-#define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F6R1_FB11_Pos (11U)
-#define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F6R1_FB12_Pos (12U)
-#define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F6R1_FB13_Pos (13U)
-#define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F6R1_FB14_Pos (14U)
-#define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F6R1_FB15_Pos (15U)
-#define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F6R1_FB16_Pos (16U)
-#define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F6R1_FB17_Pos (17U)
-#define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F6R1_FB18_Pos (18U)
-#define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F6R1_FB19_Pos (19U)
-#define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F6R1_FB20_Pos (20U)
-#define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F6R1_FB21_Pos (21U)
-#define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F6R1_FB22_Pos (22U)
-#define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F6R1_FB23_Pos (23U)
-#define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F6R1_FB24_Pos (24U)
-#define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F6R1_FB25_Pos (25U)
-#define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F6R1_FB26_Pos (26U)
-#define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F6R1_FB27_Pos (27U)
-#define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F6R1_FB28_Pos (28U)
-#define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F6R1_FB29_Pos (29U)
-#define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F6R1_FB30_Pos (30U)
-#define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F6R1_FB31_Pos (31U)
-#define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F7R1 register *******************/
-#define CAN_F7R1_FB0_Pos (0U)
-#define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F7R1_FB1_Pos (1U)
-#define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F7R1_FB2_Pos (2U)
-#define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F7R1_FB3_Pos (3U)
-#define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F7R1_FB4_Pos (4U)
-#define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F7R1_FB5_Pos (5U)
-#define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F7R1_FB6_Pos (6U)
-#define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F7R1_FB7_Pos (7U)
-#define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F7R1_FB8_Pos (8U)
-#define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F7R1_FB9_Pos (9U)
-#define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F7R1_FB10_Pos (10U)
-#define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F7R1_FB11_Pos (11U)
-#define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F7R1_FB12_Pos (12U)
-#define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F7R1_FB13_Pos (13U)
-#define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F7R1_FB14_Pos (14U)
-#define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F7R1_FB15_Pos (15U)
-#define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F7R1_FB16_Pos (16U)
-#define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F7R1_FB17_Pos (17U)
-#define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F7R1_FB18_Pos (18U)
-#define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F7R1_FB19_Pos (19U)
-#define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F7R1_FB20_Pos (20U)
-#define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F7R1_FB21_Pos (21U)
-#define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F7R1_FB22_Pos (22U)
-#define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F7R1_FB23_Pos (23U)
-#define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F7R1_FB24_Pos (24U)
-#define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F7R1_FB25_Pos (25U)
-#define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F7R1_FB26_Pos (26U)
-#define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F7R1_FB27_Pos (27U)
-#define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F7R1_FB28_Pos (28U)
-#define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F7R1_FB29_Pos (29U)
-#define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F7R1_FB30_Pos (30U)
-#define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F7R1_FB31_Pos (31U)
-#define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F8R1 register *******************/
-#define CAN_F8R1_FB0_Pos (0U)
-#define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F8R1_FB1_Pos (1U)
-#define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F8R1_FB2_Pos (2U)
-#define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F8R1_FB3_Pos (3U)
-#define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F8R1_FB4_Pos (4U)
-#define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F8R1_FB5_Pos (5U)
-#define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F8R1_FB6_Pos (6U)
-#define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F8R1_FB7_Pos (7U)
-#define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F8R1_FB8_Pos (8U)
-#define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F8R1_FB9_Pos (9U)
-#define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F8R1_FB10_Pos (10U)
-#define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F8R1_FB11_Pos (11U)
-#define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F8R1_FB12_Pos (12U)
-#define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F8R1_FB13_Pos (13U)
-#define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F8R1_FB14_Pos (14U)
-#define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F8R1_FB15_Pos (15U)
-#define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F8R1_FB16_Pos (16U)
-#define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F8R1_FB17_Pos (17U)
-#define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F8R1_FB18_Pos (18U)
-#define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F8R1_FB19_Pos (19U)
-#define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F8R1_FB20_Pos (20U)
-#define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F8R1_FB21_Pos (21U)
-#define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F8R1_FB22_Pos (22U)
-#define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F8R1_FB23_Pos (23U)
-#define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F8R1_FB24_Pos (24U)
-#define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F8R1_FB25_Pos (25U)
-#define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F8R1_FB26_Pos (26U)
-#define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F8R1_FB27_Pos (27U)
-#define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F8R1_FB28_Pos (28U)
-#define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F8R1_FB29_Pos (29U)
-#define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F8R1_FB30_Pos (30U)
-#define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F8R1_FB31_Pos (31U)
-#define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F9R1 register *******************/
-#define CAN_F9R1_FB0_Pos (0U)
-#define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F9R1_FB1_Pos (1U)
-#define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F9R1_FB2_Pos (2U)
-#define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F9R1_FB3_Pos (3U)
-#define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F9R1_FB4_Pos (4U)
-#define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F9R1_FB5_Pos (5U)
-#define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F9R1_FB6_Pos (6U)
-#define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F9R1_FB7_Pos (7U)
-#define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F9R1_FB8_Pos (8U)
-#define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F9R1_FB9_Pos (9U)
-#define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F9R1_FB10_Pos (10U)
-#define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F9R1_FB11_Pos (11U)
-#define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F9R1_FB12_Pos (12U)
-#define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F9R1_FB13_Pos (13U)
-#define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F9R1_FB14_Pos (14U)
-#define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F9R1_FB15_Pos (15U)
-#define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F9R1_FB16_Pos (16U)
-#define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F9R1_FB17_Pos (17U)
-#define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F9R1_FB18_Pos (18U)
-#define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F9R1_FB19_Pos (19U)
-#define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F9R1_FB20_Pos (20U)
-#define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F9R1_FB21_Pos (21U)
-#define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F9R1_FB22_Pos (22U)
-#define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F9R1_FB23_Pos (23U)
-#define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F9R1_FB24_Pos (24U)
-#define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F9R1_FB25_Pos (25U)
-#define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F9R1_FB26_Pos (26U)
-#define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F9R1_FB27_Pos (27U)
-#define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F9R1_FB28_Pos (28U)
-#define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F9R1_FB29_Pos (29U)
-#define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F9R1_FB30_Pos (30U)
-#define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F9R1_FB31_Pos (31U)
-#define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F10R1 register ******************/
-#define CAN_F10R1_FB0_Pos (0U)
-#define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F10R1_FB1_Pos (1U)
-#define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F10R1_FB2_Pos (2U)
-#define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F10R1_FB3_Pos (3U)
-#define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F10R1_FB4_Pos (4U)
-#define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F10R1_FB5_Pos (5U)
-#define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F10R1_FB6_Pos (6U)
-#define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F10R1_FB7_Pos (7U)
-#define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F10R1_FB8_Pos (8U)
-#define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F10R1_FB9_Pos (9U)
-#define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F10R1_FB10_Pos (10U)
-#define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F10R1_FB11_Pos (11U)
-#define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F10R1_FB12_Pos (12U)
-#define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F10R1_FB13_Pos (13U)
-#define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F10R1_FB14_Pos (14U)
-#define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F10R1_FB15_Pos (15U)
-#define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F10R1_FB16_Pos (16U)
-#define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F10R1_FB17_Pos (17U)
-#define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F10R1_FB18_Pos (18U)
-#define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F10R1_FB19_Pos (19U)
-#define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F10R1_FB20_Pos (20U)
-#define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F10R1_FB21_Pos (21U)
-#define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F10R1_FB22_Pos (22U)
-#define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F10R1_FB23_Pos (23U)
-#define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F10R1_FB24_Pos (24U)
-#define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F10R1_FB25_Pos (25U)
-#define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F10R1_FB26_Pos (26U)
-#define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F10R1_FB27_Pos (27U)
-#define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F10R1_FB28_Pos (28U)
-#define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F10R1_FB29_Pos (29U)
-#define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F10R1_FB30_Pos (30U)
-#define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F10R1_FB31_Pos (31U)
-#define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F11R1 register ******************/
-#define CAN_F11R1_FB0_Pos (0U)
-#define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F11R1_FB1_Pos (1U)
-#define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F11R1_FB2_Pos (2U)
-#define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F11R1_FB3_Pos (3U)
-#define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F11R1_FB4_Pos (4U)
-#define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F11R1_FB5_Pos (5U)
-#define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F11R1_FB6_Pos (6U)
-#define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F11R1_FB7_Pos (7U)
-#define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F11R1_FB8_Pos (8U)
-#define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F11R1_FB9_Pos (9U)
-#define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F11R1_FB10_Pos (10U)
-#define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F11R1_FB11_Pos (11U)
-#define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F11R1_FB12_Pos (12U)
-#define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F11R1_FB13_Pos (13U)
-#define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F11R1_FB14_Pos (14U)
-#define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F11R1_FB15_Pos (15U)
-#define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F11R1_FB16_Pos (16U)
-#define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F11R1_FB17_Pos (17U)
-#define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F11R1_FB18_Pos (18U)
-#define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F11R1_FB19_Pos (19U)
-#define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F11R1_FB20_Pos (20U)
-#define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F11R1_FB21_Pos (21U)
-#define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F11R1_FB22_Pos (22U)
-#define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F11R1_FB23_Pos (23U)
-#define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F11R1_FB24_Pos (24U)
-#define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F11R1_FB25_Pos (25U)
-#define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F11R1_FB26_Pos (26U)
-#define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F11R1_FB27_Pos (27U)
-#define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F11R1_FB28_Pos (28U)
-#define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F11R1_FB29_Pos (29U)
-#define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F11R1_FB30_Pos (30U)
-#define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F11R1_FB31_Pos (31U)
-#define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F12R1 register ******************/
-#define CAN_F12R1_FB0_Pos (0U)
-#define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F12R1_FB1_Pos (1U)
-#define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F12R1_FB2_Pos (2U)
-#define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F12R1_FB3_Pos (3U)
-#define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F12R1_FB4_Pos (4U)
-#define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F12R1_FB5_Pos (5U)
-#define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F12R1_FB6_Pos (6U)
-#define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F12R1_FB7_Pos (7U)
-#define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F12R1_FB8_Pos (8U)
-#define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F12R1_FB9_Pos (9U)
-#define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F12R1_FB10_Pos (10U)
-#define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F12R1_FB11_Pos (11U)
-#define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F12R1_FB12_Pos (12U)
-#define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F12R1_FB13_Pos (13U)
-#define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F12R1_FB14_Pos (14U)
-#define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F12R1_FB15_Pos (15U)
-#define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F12R1_FB16_Pos (16U)
-#define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F12R1_FB17_Pos (17U)
-#define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F12R1_FB18_Pos (18U)
-#define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F12R1_FB19_Pos (19U)
-#define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F12R1_FB20_Pos (20U)
-#define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F12R1_FB21_Pos (21U)
-#define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F12R1_FB22_Pos (22U)
-#define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F12R1_FB23_Pos (23U)
-#define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F12R1_FB24_Pos (24U)
-#define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F12R1_FB25_Pos (25U)
-#define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F12R1_FB26_Pos (26U)
-#define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F12R1_FB27_Pos (27U)
-#define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F12R1_FB28_Pos (28U)
-#define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F12R1_FB29_Pos (29U)
-#define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F12R1_FB30_Pos (30U)
-#define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F12R1_FB31_Pos (31U)
-#define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F13R1 register ******************/
-#define CAN_F13R1_FB0_Pos (0U)
-#define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F13R1_FB1_Pos (1U)
-#define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F13R1_FB2_Pos (2U)
-#define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F13R1_FB3_Pos (3U)
-#define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F13R1_FB4_Pos (4U)
-#define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F13R1_FB5_Pos (5U)
-#define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F13R1_FB6_Pos (6U)
-#define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F13R1_FB7_Pos (7U)
-#define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F13R1_FB8_Pos (8U)
-#define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F13R1_FB9_Pos (9U)
-#define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F13R1_FB10_Pos (10U)
-#define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F13R1_FB11_Pos (11U)
-#define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F13R1_FB12_Pos (12U)
-#define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F13R1_FB13_Pos (13U)
-#define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F13R1_FB14_Pos (14U)
-#define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F13R1_FB15_Pos (15U)
-#define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F13R1_FB16_Pos (16U)
-#define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F13R1_FB17_Pos (17U)
-#define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F13R1_FB18_Pos (18U)
-#define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F13R1_FB19_Pos (19U)
-#define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F13R1_FB20_Pos (20U)
-#define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F13R1_FB21_Pos (21U)
-#define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F13R1_FB22_Pos (22U)
-#define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F13R1_FB23_Pos (23U)
-#define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F13R1_FB24_Pos (24U)
-#define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F13R1_FB25_Pos (25U)
-#define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F13R1_FB26_Pos (26U)
-#define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F13R1_FB27_Pos (27U)
-#define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F13R1_FB28_Pos (28U)
-#define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F13R1_FB29_Pos (29U)
-#define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F13R1_FB30_Pos (30U)
-#define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F13R1_FB31_Pos (31U)
-#define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F0R2 register *******************/
-#define CAN_F0R2_FB0_Pos (0U)
-#define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F0R2_FB1_Pos (1U)
-#define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F0R2_FB2_Pos (2U)
-#define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F0R2_FB3_Pos (3U)
-#define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F0R2_FB4_Pos (4U)
-#define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F0R2_FB5_Pos (5U)
-#define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F0R2_FB6_Pos (6U)
-#define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F0R2_FB7_Pos (7U)
-#define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F0R2_FB8_Pos (8U)
-#define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F0R2_FB9_Pos (9U)
-#define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F0R2_FB10_Pos (10U)
-#define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F0R2_FB11_Pos (11U)
-#define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F0R2_FB12_Pos (12U)
-#define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F0R2_FB13_Pos (13U)
-#define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F0R2_FB14_Pos (14U)
-#define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F0R2_FB15_Pos (15U)
-#define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F0R2_FB16_Pos (16U)
-#define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F0R2_FB17_Pos (17U)
-#define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F0R2_FB18_Pos (18U)
-#define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F0R2_FB19_Pos (19U)
-#define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F0R2_FB20_Pos (20U)
-#define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F0R2_FB21_Pos (21U)
-#define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F0R2_FB22_Pos (22U)
-#define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F0R2_FB23_Pos (23U)
-#define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F0R2_FB24_Pos (24U)
-#define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F0R2_FB25_Pos (25U)
-#define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F0R2_FB26_Pos (26U)
-#define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F0R2_FB27_Pos (27U)
-#define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F0R2_FB28_Pos (28U)
-#define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F0R2_FB29_Pos (29U)
-#define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F0R2_FB30_Pos (30U)
-#define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F0R2_FB31_Pos (31U)
-#define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F1R2 register *******************/
-#define CAN_F1R2_FB0_Pos (0U)
-#define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F1R2_FB1_Pos (1U)
-#define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F1R2_FB2_Pos (2U)
-#define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F1R2_FB3_Pos (3U)
-#define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F1R2_FB4_Pos (4U)
-#define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F1R2_FB5_Pos (5U)
-#define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F1R2_FB6_Pos (6U)
-#define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F1R2_FB7_Pos (7U)
-#define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F1R2_FB8_Pos (8U)
-#define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F1R2_FB9_Pos (9U)
-#define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F1R2_FB10_Pos (10U)
-#define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F1R2_FB11_Pos (11U)
-#define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F1R2_FB12_Pos (12U)
-#define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F1R2_FB13_Pos (13U)
-#define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F1R2_FB14_Pos (14U)
-#define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F1R2_FB15_Pos (15U)
-#define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F1R2_FB16_Pos (16U)
-#define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F1R2_FB17_Pos (17U)
-#define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F1R2_FB18_Pos (18U)
-#define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F1R2_FB19_Pos (19U)
-#define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F1R2_FB20_Pos (20U)
-#define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F1R2_FB21_Pos (21U)
-#define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F1R2_FB22_Pos (22U)
-#define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F1R2_FB23_Pos (23U)
-#define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F1R2_FB24_Pos (24U)
-#define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F1R2_FB25_Pos (25U)
-#define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F1R2_FB26_Pos (26U)
-#define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F1R2_FB27_Pos (27U)
-#define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F1R2_FB28_Pos (28U)
-#define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F1R2_FB29_Pos (29U)
-#define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F1R2_FB30_Pos (30U)
-#define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F1R2_FB31_Pos (31U)
-#define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F2R2 register *******************/
-#define CAN_F2R2_FB0_Pos (0U)
-#define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F2R2_FB1_Pos (1U)
-#define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F2R2_FB2_Pos (2U)
-#define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F2R2_FB3_Pos (3U)
-#define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F2R2_FB4_Pos (4U)
-#define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F2R2_FB5_Pos (5U)
-#define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F2R2_FB6_Pos (6U)
-#define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F2R2_FB7_Pos (7U)
-#define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F2R2_FB8_Pos (8U)
-#define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F2R2_FB9_Pos (9U)
-#define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F2R2_FB10_Pos (10U)
-#define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F2R2_FB11_Pos (11U)
-#define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F2R2_FB12_Pos (12U)
-#define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F2R2_FB13_Pos (13U)
-#define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F2R2_FB14_Pos (14U)
-#define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F2R2_FB15_Pos (15U)
-#define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F2R2_FB16_Pos (16U)
-#define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F2R2_FB17_Pos (17U)
-#define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F2R2_FB18_Pos (18U)
-#define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F2R2_FB19_Pos (19U)
-#define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F2R2_FB20_Pos (20U)
-#define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F2R2_FB21_Pos (21U)
-#define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F2R2_FB22_Pos (22U)
-#define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F2R2_FB23_Pos (23U)
-#define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F2R2_FB24_Pos (24U)
-#define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F2R2_FB25_Pos (25U)
-#define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F2R2_FB26_Pos (26U)
-#define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F2R2_FB27_Pos (27U)
-#define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F2R2_FB28_Pos (28U)
-#define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F2R2_FB29_Pos (29U)
-#define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F2R2_FB30_Pos (30U)
-#define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F2R2_FB31_Pos (31U)
-#define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F3R2 register *******************/
-#define CAN_F3R2_FB0_Pos (0U)
-#define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F3R2_FB1_Pos (1U)
-#define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F3R2_FB2_Pos (2U)
-#define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F3R2_FB3_Pos (3U)
-#define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F3R2_FB4_Pos (4U)
-#define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F3R2_FB5_Pos (5U)
-#define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F3R2_FB6_Pos (6U)
-#define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F3R2_FB7_Pos (7U)
-#define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F3R2_FB8_Pos (8U)
-#define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F3R2_FB9_Pos (9U)
-#define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F3R2_FB10_Pos (10U)
-#define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F3R2_FB11_Pos (11U)
-#define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F3R2_FB12_Pos (12U)
-#define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F3R2_FB13_Pos (13U)
-#define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F3R2_FB14_Pos (14U)
-#define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F3R2_FB15_Pos (15U)
-#define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F3R2_FB16_Pos (16U)
-#define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F3R2_FB17_Pos (17U)
-#define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F3R2_FB18_Pos (18U)
-#define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F3R2_FB19_Pos (19U)
-#define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F3R2_FB20_Pos (20U)
-#define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F3R2_FB21_Pos (21U)
-#define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F3R2_FB22_Pos (22U)
-#define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F3R2_FB23_Pos (23U)
-#define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F3R2_FB24_Pos (24U)
-#define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F3R2_FB25_Pos (25U)
-#define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F3R2_FB26_Pos (26U)
-#define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F3R2_FB27_Pos (27U)
-#define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F3R2_FB28_Pos (28U)
-#define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F3R2_FB29_Pos (29U)
-#define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F3R2_FB30_Pos (30U)
-#define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F3R2_FB31_Pos (31U)
-#define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F4R2 register *******************/
-#define CAN_F4R2_FB0_Pos (0U)
-#define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F4R2_FB1_Pos (1U)
-#define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F4R2_FB2_Pos (2U)
-#define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F4R2_FB3_Pos (3U)
-#define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F4R2_FB4_Pos (4U)
-#define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F4R2_FB5_Pos (5U)
-#define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F4R2_FB6_Pos (6U)
-#define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F4R2_FB7_Pos (7U)
-#define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F4R2_FB8_Pos (8U)
-#define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F4R2_FB9_Pos (9U)
-#define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F4R2_FB10_Pos (10U)
-#define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F4R2_FB11_Pos (11U)
-#define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F4R2_FB12_Pos (12U)
-#define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F4R2_FB13_Pos (13U)
-#define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F4R2_FB14_Pos (14U)
-#define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F4R2_FB15_Pos (15U)
-#define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F4R2_FB16_Pos (16U)
-#define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F4R2_FB17_Pos (17U)
-#define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F4R2_FB18_Pos (18U)
-#define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F4R2_FB19_Pos (19U)
-#define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F4R2_FB20_Pos (20U)
-#define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F4R2_FB21_Pos (21U)
-#define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F4R2_FB22_Pos (22U)
-#define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F4R2_FB23_Pos (23U)
-#define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F4R2_FB24_Pos (24U)
-#define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F4R2_FB25_Pos (25U)
-#define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F4R2_FB26_Pos (26U)
-#define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F4R2_FB27_Pos (27U)
-#define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F4R2_FB28_Pos (28U)
-#define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F4R2_FB29_Pos (29U)
-#define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F4R2_FB30_Pos (30U)
-#define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F4R2_FB31_Pos (31U)
-#define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F5R2 register *******************/
-#define CAN_F5R2_FB0_Pos (0U)
-#define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F5R2_FB1_Pos (1U)
-#define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F5R2_FB2_Pos (2U)
-#define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F5R2_FB3_Pos (3U)
-#define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F5R2_FB4_Pos (4U)
-#define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F5R2_FB5_Pos (5U)
-#define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F5R2_FB6_Pos (6U)
-#define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F5R2_FB7_Pos (7U)
-#define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F5R2_FB8_Pos (8U)
-#define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F5R2_FB9_Pos (9U)
-#define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F5R2_FB10_Pos (10U)
-#define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F5R2_FB11_Pos (11U)
-#define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F5R2_FB12_Pos (12U)
-#define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F5R2_FB13_Pos (13U)
-#define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F5R2_FB14_Pos (14U)
-#define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F5R2_FB15_Pos (15U)
-#define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F5R2_FB16_Pos (16U)
-#define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F5R2_FB17_Pos (17U)
-#define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F5R2_FB18_Pos (18U)
-#define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F5R2_FB19_Pos (19U)
-#define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F5R2_FB20_Pos (20U)
-#define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F5R2_FB21_Pos (21U)
-#define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F5R2_FB22_Pos (22U)
-#define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F5R2_FB23_Pos (23U)
-#define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F5R2_FB24_Pos (24U)
-#define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F5R2_FB25_Pos (25U)
-#define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F5R2_FB26_Pos (26U)
-#define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F5R2_FB27_Pos (27U)
-#define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F5R2_FB28_Pos (28U)
-#define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F5R2_FB29_Pos (29U)
-#define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F5R2_FB30_Pos (30U)
-#define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F5R2_FB31_Pos (31U)
-#define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F6R2 register *******************/
-#define CAN_F6R2_FB0_Pos (0U)
-#define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F6R2_FB1_Pos (1U)
-#define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F6R2_FB2_Pos (2U)
-#define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F6R2_FB3_Pos (3U)
-#define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F6R2_FB4_Pos (4U)
-#define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F6R2_FB5_Pos (5U)
-#define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F6R2_FB6_Pos (6U)
-#define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F6R2_FB7_Pos (7U)
-#define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F6R2_FB8_Pos (8U)
-#define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F6R2_FB9_Pos (9U)
-#define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F6R2_FB10_Pos (10U)
-#define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F6R2_FB11_Pos (11U)
-#define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F6R2_FB12_Pos (12U)
-#define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F6R2_FB13_Pos (13U)
-#define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F6R2_FB14_Pos (14U)
-#define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F6R2_FB15_Pos (15U)
-#define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F6R2_FB16_Pos (16U)
-#define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F6R2_FB17_Pos (17U)
-#define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F6R2_FB18_Pos (18U)
-#define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F6R2_FB19_Pos (19U)
-#define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F6R2_FB20_Pos (20U)
-#define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F6R2_FB21_Pos (21U)
-#define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F6R2_FB22_Pos (22U)
-#define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F6R2_FB23_Pos (23U)
-#define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F6R2_FB24_Pos (24U)
-#define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F6R2_FB25_Pos (25U)
-#define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F6R2_FB26_Pos (26U)
-#define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F6R2_FB27_Pos (27U)
-#define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F6R2_FB28_Pos (28U)
-#define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F6R2_FB29_Pos (29U)
-#define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F6R2_FB30_Pos (30U)
-#define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F6R2_FB31_Pos (31U)
-#define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F7R2 register *******************/
-#define CAN_F7R2_FB0_Pos (0U)
-#define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F7R2_FB1_Pos (1U)
-#define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F7R2_FB2_Pos (2U)
-#define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F7R2_FB3_Pos (3U)
-#define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F7R2_FB4_Pos (4U)
-#define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F7R2_FB5_Pos (5U)
-#define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F7R2_FB6_Pos (6U)
-#define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F7R2_FB7_Pos (7U)
-#define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F7R2_FB8_Pos (8U)
-#define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F7R2_FB9_Pos (9U)
-#define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F7R2_FB10_Pos (10U)
-#define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F7R2_FB11_Pos (11U)
-#define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F7R2_FB12_Pos (12U)
-#define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F7R2_FB13_Pos (13U)
-#define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F7R2_FB14_Pos (14U)
-#define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F7R2_FB15_Pos (15U)
-#define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F7R2_FB16_Pos (16U)
-#define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F7R2_FB17_Pos (17U)
-#define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F7R2_FB18_Pos (18U)
-#define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F7R2_FB19_Pos (19U)
-#define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F7R2_FB20_Pos (20U)
-#define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F7R2_FB21_Pos (21U)
-#define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F7R2_FB22_Pos (22U)
-#define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F7R2_FB23_Pos (23U)
-#define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F7R2_FB24_Pos (24U)
-#define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F7R2_FB25_Pos (25U)
-#define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F7R2_FB26_Pos (26U)
-#define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F7R2_FB27_Pos (27U)
-#define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F7R2_FB28_Pos (28U)
-#define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F7R2_FB29_Pos (29U)
-#define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F7R2_FB30_Pos (30U)
-#define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F7R2_FB31_Pos (31U)
-#define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F8R2 register *******************/
-#define CAN_F8R2_FB0_Pos (0U)
-#define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F8R2_FB1_Pos (1U)
-#define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F8R2_FB2_Pos (2U)
-#define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F8R2_FB3_Pos (3U)
-#define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F8R2_FB4_Pos (4U)
-#define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F8R2_FB5_Pos (5U)
-#define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F8R2_FB6_Pos (6U)
-#define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F8R2_FB7_Pos (7U)
-#define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F8R2_FB8_Pos (8U)
-#define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F8R2_FB9_Pos (9U)
-#define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F8R2_FB10_Pos (10U)
-#define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F8R2_FB11_Pos (11U)
-#define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F8R2_FB12_Pos (12U)
-#define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F8R2_FB13_Pos (13U)
-#define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F8R2_FB14_Pos (14U)
-#define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F8R2_FB15_Pos (15U)
-#define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F8R2_FB16_Pos (16U)
-#define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F8R2_FB17_Pos (17U)
-#define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F8R2_FB18_Pos (18U)
-#define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F8R2_FB19_Pos (19U)
-#define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F8R2_FB20_Pos (20U)
-#define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F8R2_FB21_Pos (21U)
-#define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F8R2_FB22_Pos (22U)
-#define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F8R2_FB23_Pos (23U)
-#define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F8R2_FB24_Pos (24U)
-#define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F8R2_FB25_Pos (25U)
-#define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F8R2_FB26_Pos (26U)
-#define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F8R2_FB27_Pos (27U)
-#define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F8R2_FB28_Pos (28U)
-#define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F8R2_FB29_Pos (29U)
-#define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F8R2_FB30_Pos (30U)
-#define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F8R2_FB31_Pos (31U)
-#define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F9R2 register *******************/
-#define CAN_F9R2_FB0_Pos (0U)
-#define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F9R2_FB1_Pos (1U)
-#define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F9R2_FB2_Pos (2U)
-#define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F9R2_FB3_Pos (3U)
-#define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F9R2_FB4_Pos (4U)
-#define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F9R2_FB5_Pos (5U)
-#define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F9R2_FB6_Pos (6U)
-#define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F9R2_FB7_Pos (7U)
-#define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F9R2_FB8_Pos (8U)
-#define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F9R2_FB9_Pos (9U)
-#define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F9R2_FB10_Pos (10U)
-#define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F9R2_FB11_Pos (11U)
-#define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F9R2_FB12_Pos (12U)
-#define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F9R2_FB13_Pos (13U)
-#define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F9R2_FB14_Pos (14U)
-#define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F9R2_FB15_Pos (15U)
-#define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F9R2_FB16_Pos (16U)
-#define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F9R2_FB17_Pos (17U)
-#define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F9R2_FB18_Pos (18U)
-#define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F9R2_FB19_Pos (19U)
-#define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F9R2_FB20_Pos (20U)
-#define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F9R2_FB21_Pos (21U)
-#define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F9R2_FB22_Pos (22U)
-#define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F9R2_FB23_Pos (23U)
-#define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F9R2_FB24_Pos (24U)
-#define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F9R2_FB25_Pos (25U)
-#define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F9R2_FB26_Pos (26U)
-#define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F9R2_FB27_Pos (27U)
-#define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F9R2_FB28_Pos (28U)
-#define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F9R2_FB29_Pos (29U)
-#define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F9R2_FB30_Pos (30U)
-#define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F9R2_FB31_Pos (31U)
-#define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F10R2 register ******************/
-#define CAN_F10R2_FB0_Pos (0U)
-#define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F10R2_FB1_Pos (1U)
-#define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F10R2_FB2_Pos (2U)
-#define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F10R2_FB3_Pos (3U)
-#define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F10R2_FB4_Pos (4U)
-#define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F10R2_FB5_Pos (5U)
-#define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F10R2_FB6_Pos (6U)
-#define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F10R2_FB7_Pos (7U)
-#define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F10R2_FB8_Pos (8U)
-#define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F10R2_FB9_Pos (9U)
-#define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F10R2_FB10_Pos (10U)
-#define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F10R2_FB11_Pos (11U)
-#define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F10R2_FB12_Pos (12U)
-#define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F10R2_FB13_Pos (13U)
-#define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F10R2_FB14_Pos (14U)
-#define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F10R2_FB15_Pos (15U)
-#define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F10R2_FB16_Pos (16U)
-#define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F10R2_FB17_Pos (17U)
-#define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F10R2_FB18_Pos (18U)
-#define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F10R2_FB19_Pos (19U)
-#define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F10R2_FB20_Pos (20U)
-#define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F10R2_FB21_Pos (21U)
-#define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F10R2_FB22_Pos (22U)
-#define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F10R2_FB23_Pos (23U)
-#define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F10R2_FB24_Pos (24U)
-#define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F10R2_FB25_Pos (25U)
-#define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F10R2_FB26_Pos (26U)
-#define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F10R2_FB27_Pos (27U)
-#define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F10R2_FB28_Pos (28U)
-#define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F10R2_FB29_Pos (29U)
-#define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F10R2_FB30_Pos (30U)
-#define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F10R2_FB31_Pos (31U)
-#define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F11R2 register ******************/
-#define CAN_F11R2_FB0_Pos (0U)
-#define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F11R2_FB1_Pos (1U)
-#define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F11R2_FB2_Pos (2U)
-#define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F11R2_FB3_Pos (3U)
-#define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F11R2_FB4_Pos (4U)
-#define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F11R2_FB5_Pos (5U)
-#define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F11R2_FB6_Pos (6U)
-#define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F11R2_FB7_Pos (7U)
-#define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F11R2_FB8_Pos (8U)
-#define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F11R2_FB9_Pos (9U)
-#define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F11R2_FB10_Pos (10U)
-#define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F11R2_FB11_Pos (11U)
-#define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F11R2_FB12_Pos (12U)
-#define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F11R2_FB13_Pos (13U)
-#define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F11R2_FB14_Pos (14U)
-#define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F11R2_FB15_Pos (15U)
-#define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F11R2_FB16_Pos (16U)
-#define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F11R2_FB17_Pos (17U)
-#define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F11R2_FB18_Pos (18U)
-#define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F11R2_FB19_Pos (19U)
-#define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F11R2_FB20_Pos (20U)
-#define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F11R2_FB21_Pos (21U)
-#define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F11R2_FB22_Pos (22U)
-#define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F11R2_FB23_Pos (23U)
-#define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F11R2_FB24_Pos (24U)
-#define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F11R2_FB25_Pos (25U)
-#define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F11R2_FB26_Pos (26U)
-#define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F11R2_FB27_Pos (27U)
-#define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F11R2_FB28_Pos (28U)
-#define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F11R2_FB29_Pos (29U)
-#define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F11R2_FB30_Pos (30U)
-#define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F11R2_FB31_Pos (31U)
-#define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F12R2 register ******************/
-#define CAN_F12R2_FB0_Pos (0U)
-#define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F12R2_FB1_Pos (1U)
-#define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F12R2_FB2_Pos (2U)
-#define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F12R2_FB3_Pos (3U)
-#define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F12R2_FB4_Pos (4U)
-#define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F12R2_FB5_Pos (5U)
-#define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F12R2_FB6_Pos (6U)
-#define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F12R2_FB7_Pos (7U)
-#define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F12R2_FB8_Pos (8U)
-#define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F12R2_FB9_Pos (9U)
-#define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F12R2_FB10_Pos (10U)
-#define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F12R2_FB11_Pos (11U)
-#define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F12R2_FB12_Pos (12U)
-#define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F12R2_FB13_Pos (13U)
-#define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F12R2_FB14_Pos (14U)
-#define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F12R2_FB15_Pos (15U)
-#define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F12R2_FB16_Pos (16U)
-#define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F12R2_FB17_Pos (17U)
-#define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F12R2_FB18_Pos (18U)
-#define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F12R2_FB19_Pos (19U)
-#define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F12R2_FB20_Pos (20U)
-#define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F12R2_FB21_Pos (21U)
-#define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F12R2_FB22_Pos (22U)
-#define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F12R2_FB23_Pos (23U)
-#define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F12R2_FB24_Pos (24U)
-#define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F12R2_FB25_Pos (25U)
-#define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F12R2_FB26_Pos (26U)
-#define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F12R2_FB27_Pos (27U)
-#define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F12R2_FB28_Pos (28U)
-#define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F12R2_FB29_Pos (29U)
-#define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F12R2_FB30_Pos (30U)
-#define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F12R2_FB31_Pos (31U)
-#define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************* Bit definition for CAN_F13R2 register ******************/
-#define CAN_F13R2_FB0_Pos (0U)
-#define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
-#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */
-#define CAN_F13R2_FB1_Pos (1U)
-#define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
-#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */
-#define CAN_F13R2_FB2_Pos (2U)
-#define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
-#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */
-#define CAN_F13R2_FB3_Pos (3U)
-#define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
-#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */
-#define CAN_F13R2_FB4_Pos (4U)
-#define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
-#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */
-#define CAN_F13R2_FB5_Pos (5U)
-#define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
-#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */
-#define CAN_F13R2_FB6_Pos (6U)
-#define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
-#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */
-#define CAN_F13R2_FB7_Pos (7U)
-#define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
-#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */
-#define CAN_F13R2_FB8_Pos (8U)
-#define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
-#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */
-#define CAN_F13R2_FB9_Pos (9U)
-#define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
-#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */
-#define CAN_F13R2_FB10_Pos (10U)
-#define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
-#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */
-#define CAN_F13R2_FB11_Pos (11U)
-#define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
-#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */
-#define CAN_F13R2_FB12_Pos (12U)
-#define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
-#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */
-#define CAN_F13R2_FB13_Pos (13U)
-#define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
-#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */
-#define CAN_F13R2_FB14_Pos (14U)
-#define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
-#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */
-#define CAN_F13R2_FB15_Pos (15U)
-#define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
-#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */
-#define CAN_F13R2_FB16_Pos (16U)
-#define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
-#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */
-#define CAN_F13R2_FB17_Pos (17U)
-#define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
-#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */
-#define CAN_F13R2_FB18_Pos (18U)
-#define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
-#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */
-#define CAN_F13R2_FB19_Pos (19U)
-#define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
-#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */
-#define CAN_F13R2_FB20_Pos (20U)
-#define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
-#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */
-#define CAN_F13R2_FB21_Pos (21U)
-#define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
-#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */
-#define CAN_F13R2_FB22_Pos (22U)
-#define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
-#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */
-#define CAN_F13R2_FB23_Pos (23U)
-#define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
-#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */
-#define CAN_F13R2_FB24_Pos (24U)
-#define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
-#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */
-#define CAN_F13R2_FB25_Pos (25U)
-#define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
-#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */
-#define CAN_F13R2_FB26_Pos (26U)
-#define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
-#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */
-#define CAN_F13R2_FB27_Pos (27U)
-#define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
-#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */
-#define CAN_F13R2_FB28_Pos (28U)
-#define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
-#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */
-#define CAN_F13R2_FB29_Pos (29U)
-#define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
-#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */
-#define CAN_F13R2_FB30_Pos (30U)
-#define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
-#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */
-#define CAN_F13R2_FB31_Pos (31U)
-#define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
-#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */
-
-/******************************************************************************/
-/* */
-/* Serial Peripheral Interface */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for SPI_CR1 register ********************/
-#define SPI_CR1_CPHA_Pos (0U)
-#define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
-#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
-#define SPI_CR1_CPOL_Pos (1U)
-#define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
-#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
-#define SPI_CR1_MSTR_Pos (2U)
-#define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
-#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
-
-#define SPI_CR1_BR_Pos (3U)
-#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
-#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
-#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
-#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos (6U)
-#define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
-#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST_Pos (7U)
-#define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
-#define SPI_CR1_SSI_Pos (8U)
-#define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
-#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
-#define SPI_CR1_SSM_Pos (9U)
-#define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
-#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
-#define SPI_CR1_RXONLY_Pos (10U)
-#define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
-#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
-#define SPI_CR1_DFF_Pos (11U)
-#define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
-#define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT_Pos (12U)
-#define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN_Pos (13U)
-#define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
-#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE_Pos (14U)
-#define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos (15U)
-#define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
-
-/******************* Bit definition for SPI_CR2 register ********************/
-#define SPI_CR2_RXDMAEN_Pos (0U)
-#define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos (1U)
-#define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos (2U)
-#define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
-#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
-#define SPI_CR2_ERRIE_Pos (5U)
-#define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
-#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos (6U)
-#define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos (7U)
-#define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
-#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
-
-/******************** Bit definition for SPI_SR register ********************/
-#define SPI_SR_RXNE_Pos (0U)
-#define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
-#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos (1U)
-#define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
-#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos (2U)
-#define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
-#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
-#define SPI_SR_UDR_Pos (3U)
-#define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
-#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos (4U)
-#define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
-#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos (5U)
-#define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
-#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
-#define SPI_SR_OVR_Pos (6U)
-#define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
-#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
-#define SPI_SR_BSY_Pos (7U)
-#define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
-#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
-
-/******************** Bit definition for SPI_DR register ********************/
-#define SPI_DR_DR_Pos (0U)
-#define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
-#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
-
-/******************* Bit definition for SPI_CRCPR register ******************/
-#define SPI_CRCPR_CRCPOLY_Pos (0U)
-#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
-
-/****************** Bit definition for SPI_RXCRCR register ******************/
-#define SPI_RXCRCR_RXCRC_Pos (0U)
-#define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
-
-/****************** Bit definition for SPI_TXCRCR register ******************/
-#define SPI_TXCRCR_TXCRC_Pos (0U)
-#define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
-
-/****************** Bit definition for SPI_I2SCFGR register *****************/
-#define SPI_I2SCFGR_I2SMOD_Pos (11U)
-#define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
-
-
-/******************************************************************************/
-/* */
-/* Inter-integrated Circuit Interface */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for I2C_CR1 register ********************/
-#define I2C_CR1_PE_Pos (0U)
-#define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
-#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
-#define I2C_CR1_SMBUS_Pos (1U)
-#define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
-#define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
-#define I2C_CR1_SMBTYPE_Pos (3U)
-#define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
-#define I2C_CR1_ENARP_Pos (4U)
-#define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
-#define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
-#define I2C_CR1_ENPEC_Pos (5U)
-#define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
-#define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
-#define I2C_CR1_ENGC_Pos (6U)
-#define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
-#define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
-#define I2C_CR1_NOSTRETCH_Pos (7U)
-#define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
-#define I2C_CR1_START_Pos (8U)
-#define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
-#define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
-#define I2C_CR1_STOP_Pos (9U)
-#define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
-#define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
-#define I2C_CR1_ACK_Pos (10U)
-#define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
-#define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
-#define I2C_CR1_POS_Pos (11U)
-#define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
-#define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos (12U)
-#define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
-#define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
-#define I2C_CR1_ALERT_Pos (13U)
-#define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
-#define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
-#define I2C_CR1_SWRST_Pos (15U)
-#define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
-#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
-
-/******************* Bit definition for I2C_CR2 register ********************/
-#define I2C_CR2_FREQ_Pos (0U)
-#define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
-#define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos (8U)
-#define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
-#define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
-#define I2C_CR2_ITEVTEN_Pos (9U)
-#define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN_Pos (10U)
-#define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos (11U)
-#define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
-#define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
-#define I2C_CR2_LAST_Pos (12U)
-#define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
-#define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
-
-/******************* Bit definition for I2C_OAR1 register *******************/
-#define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
-#define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
-
-#define I2C_OAR1_ADD0_Pos (0U)
-#define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
-#define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
-#define I2C_OAR1_ADD1_Pos (1U)
-#define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
-#define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
-#define I2C_OAR1_ADD2_Pos (2U)
-#define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
-#define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
-#define I2C_OAR1_ADD3_Pos (3U)
-#define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
-#define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
-#define I2C_OAR1_ADD4_Pos (4U)
-#define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
-#define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
-#define I2C_OAR1_ADD5_Pos (5U)
-#define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
-#define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
-#define I2C_OAR1_ADD6_Pos (6U)
-#define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
-#define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
-#define I2C_OAR1_ADD7_Pos (7U)
-#define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
-#define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
-#define I2C_OAR1_ADD8_Pos (8U)
-#define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
-#define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
-#define I2C_OAR1_ADD9_Pos (9U)
-#define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
-#define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos (15U)
-#define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
-
-/******************* Bit definition for I2C_OAR2 register *******************/
-#define I2C_OAR2_ENDUAL_Pos (0U)
-#define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos (1U)
-#define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
-#define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
-
-/******************** Bit definition for I2C_DR register ********************/
-#define I2C_DR_DR_Pos (0U)
-#define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
-#define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
-
-/******************* Bit definition for I2C_SR1 register ********************/
-#define I2C_SR1_SB_Pos (0U)
-#define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
-#define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
-#define I2C_SR1_ADDR_Pos (1U)
-#define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
-#define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos (2U)
-#define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
-#define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
-#define I2C_SR1_ADD10_Pos (3U)
-#define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
-#define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
-#define I2C_SR1_STOPF_Pos (4U)
-#define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
-#define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
-#define I2C_SR1_RXNE_Pos (6U)
-#define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
-#define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
-#define I2C_SR1_TXE_Pos (7U)
-#define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
-#define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
-#define I2C_SR1_BERR_Pos (8U)
-#define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
-#define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
-#define I2C_SR1_ARLO_Pos (9U)
-#define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
-#define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
-#define I2C_SR1_AF_Pos (10U)
-#define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
-#define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
-#define I2C_SR1_OVR_Pos (11U)
-#define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
-#define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
-#define I2C_SR1_PECERR_Pos (12U)
-#define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
-#define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
-#define I2C_SR1_TIMEOUT_Pos (14U)
-#define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
-#define I2C_SR1_SMBALERT_Pos (15U)
-#define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
-
-/******************* Bit definition for I2C_SR2 register ********************/
-#define I2C_SR2_MSL_Pos (0U)
-#define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
-#define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
-#define I2C_SR2_BUSY_Pos (1U)
-#define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
-#define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
-#define I2C_SR2_TRA_Pos (2U)
-#define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
-#define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
-#define I2C_SR2_GENCALL_Pos (4U)
-#define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
-#define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
-#define I2C_SR2_SMBDEFAULT_Pos (5U)
-#define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
-#define I2C_SR2_SMBHOST_Pos (6U)
-#define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
-#define I2C_SR2_DUALF_Pos (7U)
-#define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
-#define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
-#define I2C_SR2_PEC_Pos (8U)
-#define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
-#define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
-
-/******************* Bit definition for I2C_CCR register ********************/
-#define I2C_CCR_CCR_Pos (0U)
-#define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
-#define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos (14U)
-#define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
-#define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
-#define I2C_CCR_FS_Pos (15U)
-#define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
-#define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
-
-/****************** Bit definition for I2C_TRISE register *******************/
-#define I2C_TRISE_TRISE_Pos (0U)
-#define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
-#define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/* */
-/* Universal Synchronous Asynchronous Receiver Transmitter */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for USART_SR register *******************/
-#define USART_SR_PE_Pos (0U)
-#define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
-#define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
-#define USART_SR_FE_Pos (1U)
-#define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
-#define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
-#define USART_SR_NE_Pos (2U)
-#define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
-#define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
-#define USART_SR_ORE_Pos (3U)
-#define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
-#define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
-#define USART_SR_IDLE_Pos (4U)
-#define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
-#define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
-#define USART_SR_RXNE_Pos (5U)
-#define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
-#define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
-#define USART_SR_TC_Pos (6U)
-#define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
-#define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
-#define USART_SR_TXE_Pos (7U)
-#define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
-#define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
-#define USART_SR_LBD_Pos (8U)
-#define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
-#define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
-#define USART_SR_CTS_Pos (9U)
-#define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
-#define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
-
-/******************* Bit definition for USART_DR register *******************/
-#define USART_DR_DR_Pos (0U)
-#define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
-#define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
-
-/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_Fraction_Pos (0U)
-#define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
-#define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_Mantissa_Pos (4U)
-#define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
-
-/****************** Bit definition for USART_CR1 register *******************/
-#define USART_CR1_SBK_Pos (0U)
-#define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
-#define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
-#define USART_CR1_RWU_Pos (1U)
-#define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
-#define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
-#define USART_CR1_RE_Pos (2U)
-#define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
-#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
-#define USART_CR1_TE_Pos (3U)
-#define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
-#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos (4U)
-#define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
-#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_Pos (5U)
-#define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
-#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE_Pos (6U)
-#define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
-#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos (7U)
-#define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
-#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
-#define USART_CR1_PEIE_Pos (8U)
-#define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
-#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos (9U)
-#define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
-#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
-#define USART_CR1_PCE_Pos (10U)
-#define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
-#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos (11U)
-#define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
-#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
-#define USART_CR1_M_Pos (12U)
-#define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
-#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
-#define USART_CR1_UE_Pos (13U)
-#define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
-#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
-
-/****************** Bit definition for USART_CR2 register *******************/
-#define USART_CR2_ADD_Pos (0U)
-#define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
-#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
-#define USART_CR2_LBDL_Pos (5U)
-#define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
-#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos (6U)
-#define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
-#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos (8U)
-#define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
-#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos (9U)
-#define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
-#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos (10U)
-#define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
-#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos (11U)
-#define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
-#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
-
-#define USART_CR2_STOP_Pos (12U)
-#define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
-#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
-#define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
-
-#define USART_CR2_LINEN_Pos (14U)
-#define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
-#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
-
-/****************** Bit definition for USART_CR3 register *******************/
-#define USART_CR3_EIE_Pos (0U)
-#define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
-#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos (1U)
-#define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
-#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos (2U)
-#define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
-#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos (3U)
-#define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
-#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos (4U)
-#define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
-#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
-#define USART_CR3_SCEN_Pos (5U)
-#define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
-#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
-#define USART_CR3_DMAR_Pos (6U)
-#define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
-#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos (7U)
-#define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
-#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos (8U)
-#define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
-#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos (9U)
-#define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
-#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos (10U)
-#define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
-#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
-
-/****************** Bit definition for USART_GTPR register ******************/
-#define USART_GTPR_PSC_Pos (0U)
-#define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
-#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
-#define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
-#define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
-#define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
-#define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
-#define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
-#define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
-#define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
-
-#define USART_GTPR_GT_Pos (8U)
-#define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
-#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
-
-/******************************************************************************/
-/* */
-/* Debug MCU */
-/* */
-/******************************************************************************/
-
-/**************** Bit definition for DBGMCU_IDCODE register *****************/
-#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
-#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID_Pos (16U)
-#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
-#define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
-#define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
-#define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
-#define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
-#define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
-#define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
-#define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
-#define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
-#define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
-#define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
-#define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
-#define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
-#define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
-#define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
-#define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
-
-/****************** Bit definition for DBGMCU_CR register *******************/
-#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
-#define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP_Pos (1U)
-#define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
-#define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
-#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
-#define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
-
-#define DBGMCU_CR_TRACE_MODE_Pos (6U)
-#define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-#define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
-#define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
-#define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
-#define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
-#define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
-#define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
-#define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
-#define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
-#define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
-#define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
-#define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
-#define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
-#define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
-#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
-#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************************************************************************/
-/* */
-/* FLASH and Option Bytes Registers */
-/* */
-/******************************************************************************/
-/******************* Bit definition for FLASH_ACR register ******************/
-#define FLASH_ACR_LATENCY_Pos (0U)
-#define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
-#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
-#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
-#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
-
-#define FLASH_ACR_HLFCYA_Pos (3U)
-#define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
-#define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
-#define FLASH_ACR_PRFTBE_Pos (4U)
-#define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
-#define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_PRFTBS_Pos (5U)
-#define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
-#define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
-
-/****************** Bit definition for FLASH_KEYR register ******************/
-#define FLASH_KEYR_FKEYR_Pos (0U)
-#define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
-
-#define RDP_KEY_Pos (0U)
-#define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
-#define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
-#define FLASH_KEY1_Pos (0U)
-#define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
-#define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
-#define FLASH_KEY2_Pos (0U)
-#define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
-#define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
-
-/***************** Bit definition for FLASH_OPTKEYR register ****************/
-#define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
-#define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
-
-#define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
-#define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
-
-/****************** Bit definition for FLASH_SR register ********************/
-#define FLASH_SR_BSY_Pos (0U)
-#define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
-#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
-#define FLASH_SR_PGERR_Pos (2U)
-#define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
-#define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
-#define FLASH_SR_WRPRTERR_Pos (4U)
-#define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
-#define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
-#define FLASH_SR_EOP_Pos (5U)
-#define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
-#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
-
-/******************* Bit definition for FLASH_CR register *******************/
-#define FLASH_CR_PG_Pos (0U)
-#define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
-#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
-#define FLASH_CR_PER_Pos (1U)
-#define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
-#define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
-#define FLASH_CR_MER_Pos (2U)
-#define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
-#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
-#define FLASH_CR_OPTPG_Pos (4U)
-#define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
-#define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
-#define FLASH_CR_OPTER_Pos (5U)
-#define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
-#define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
-#define FLASH_CR_STRT_Pos (6U)
-#define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
-#define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
-#define FLASH_CR_LOCK_Pos (7U)
-#define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
-#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
-#define FLASH_CR_OPTWRE_Pos (9U)
-#define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
-#define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
-#define FLASH_CR_ERRIE_Pos (10U)
-#define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
-#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
-#define FLASH_CR_EOPIE_Pos (12U)
-#define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
-#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
-
-/******************* Bit definition for FLASH_AR register *******************/
-#define FLASH_AR_FAR_Pos (0U)
-#define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
-
-/****************** Bit definition for FLASH_OBR register *******************/
-#define FLASH_OBR_OPTERR_Pos (0U)
-#define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
-#define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
-#define FLASH_OBR_RDPRT_Pos (1U)
-#define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
-#define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
-
-#define FLASH_OBR_IWDG_SW_Pos (2U)
-#define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
-#define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
-#define FLASH_OBR_nRST_STOP_Pos (3U)
-#define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
-#define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY_Pos (4U)
-#define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
-#define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
-#define FLASH_OBR_USER_Pos (2U)
-#define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
-#define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
-#define FLASH_OBR_DATA0_Pos (10U)
-#define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
-#define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
-#define FLASH_OBR_DATA1_Pos (18U)
-#define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
-#define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
-
-/****************** Bit definition for FLASH_WRPR register ******************/
-#define FLASH_WRPR_WRP_Pos (0U)
-#define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
-#define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
-
-/*----------------------------------------------------------------------------*/
-
-/****************** Bit definition for FLASH_RDP register *******************/
-#define FLASH_RDP_RDP_Pos (0U)
-#define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
-#define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
-#define FLASH_RDP_nRDP_Pos (8U)
-#define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
-#define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
-
-/****************** Bit definition for FLASH_USER register ******************/
-#define FLASH_USER_USER_Pos (16U)
-#define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
-#define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
-#define FLASH_USER_nUSER_Pos (24U)
-#define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
-#define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
-
-/****************** Bit definition for FLASH_Data0 register *****************/
-#define FLASH_DATA0_DATA0_Pos (0U)
-#define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
-#define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
-#define FLASH_DATA0_nDATA0_Pos (8U)
-#define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
-#define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
-
-/****************** Bit definition for FLASH_Data1 register *****************/
-#define FLASH_DATA1_DATA1_Pos (16U)
-#define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
-#define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
-#define FLASH_DATA1_nDATA1_Pos (24U)
-#define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
-#define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
-
-/****************** Bit definition for FLASH_WRP0 register ******************/
-#define FLASH_WRP0_WRP0_Pos (0U)
-#define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
-#define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
-#define FLASH_WRP0_nWRP0_Pos (8U)
-#define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
-#define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
-
-/****************** Bit definition for FLASH_WRP1 register ******************/
-#define FLASH_WRP1_WRP1_Pos (16U)
-#define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
-#define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
-#define FLASH_WRP1_nWRP1_Pos (24U)
-#define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
-#define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
-
-/****************** Bit definition for FLASH_WRP2 register ******************/
-#define FLASH_WRP2_WRP2_Pos (0U)
-#define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
-#define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
-#define FLASH_WRP2_nWRP2_Pos (8U)
-#define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
-#define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
-
-/****************** Bit definition for FLASH_WRP3 register ******************/
-#define FLASH_WRP3_WRP3_Pos (16U)
-#define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
-#define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
-#define FLASH_WRP3_nWRP3_Pos (24U)
-#define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
-#define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
-
-
-
-/**
- * @}
-*/
-
-/**
- * @}
-*/
-
-/** @addtogroup Exported_macro
- * @{
- */
-
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
- ((INSTANCE) == ADC2))
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
-
-#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-/****************************** CAN Instances *********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
- ((INSTANCE) == DMA1_Channel2) || \
- ((INSTANCE) == DMA1_Channel3) || \
- ((INSTANCE) == DMA1_Channel4) || \
- ((INSTANCE) == DMA1_Channel5) || \
- ((INSTANCE) == DMA1_Channel6) || \
- ((INSTANCE) == DMA1_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
- ((INSTANCE) == GPIOB) || \
- ((INSTANCE) == GPIOC) || \
- ((INSTANCE) == GPIOD) || \
- ((INSTANCE) == GPIOE))
-
-/**************************** GPIO Alternate Function Instances ***************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
- ((INSTANCE) == I2C2))
-
-/******************************* SMBUS Instances ******************************/
-#define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
- ((INSTANCE) == SPI2))
-
-/****************************** START TIM Instances ***************************/
-/****************************** TIM Instances *********************************/
-#define IS_TIM_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
- ((INSTANCE) == TIM1)
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
- ((((INSTANCE) == TIM1) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))) \
- || \
- (((INSTANCE) == TIM2) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))) \
- || \
- (((INSTANCE) == TIM3) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))) \
- || \
- (((INSTANCE) == TIM4) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3) || \
- ((CHANNEL) == TIM_CHANNEL_4))))
-
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
- (((INSTANCE) == TIM1) && \
- (((CHANNEL) == TIM_CHANNEL_1) || \
- ((CHANNEL) == TIM_CHANNEL_2) || \
- ((CHANNEL) == TIM_CHANNEL_3)))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
- ((INSTANCE) == TIM1)
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
- (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
- ((INSTANCE) == TIM1)
-
-#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
- ((INSTANCE) == TIM2) || \
- ((INSTANCE) == TIM3) || \
- ((INSTANCE) == TIM4))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
-
-/****************************** END TIM Instances *****************************/
-
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/***************** UART Instances : DMA mode available **********************/
-#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
- ((INSTANCE) == USART2) || \
- ((INSTANCE) == USART3))
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
-
-/**************************** WWDG Instances *****************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-
-
-
-#define RCC_HSE_MIN 4000000U
-#define RCC_HSE_MAX 16000000U
-
-#define RCC_MAX_FREQUENCY 72000000U
-
-/**
- * @}
- */
-/******************************************************************************/
-/* For a painless codes migration between the STM32F1xx device product */
-/* lines, the aliases defined below are put in place to overcome the */
-/* differences in the interrupt handlers and IRQn definitions. */
-/* No need to update developed interrupt code when moving across */
-/* product lines within the same STM32F1 Family */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-#define ADC1_IRQn ADC1_2_IRQn
-#define TIM9_IRQn TIM1_BRK_IRQn
-#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
-#define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
-#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
-#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
-#define TIM11_IRQn TIM1_TRG_COM_IRQn
-#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
-#define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
-#define TIM10_IRQn TIM1_UP_IRQn
-#define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
-#define CEC_IRQn USBWakeUp_IRQn
-#define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
-#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
-#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
-#define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
-
-
-/* Aliases for __IRQHandler */
-#define ADC1_IRQHandler ADC1_2_IRQHandler
-#define TIM9_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
-#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
-#define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
-#define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
-#define TIM10_IRQHandler TIM1_UP_IRQHandler
-#define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
-#define CEC_IRQHandler USBWakeUp_IRQHandler
-#define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
-#define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
-#define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
-#define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
- }
-#endif /* __cplusplus */
-
-#endif /* __STM32F103xB_H */
-
-
-
- /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
deleted file mode 100644
index 64dbeb879d2d7a1e6be4f36cde972fb88154ecc6..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx.h
- * @author MCD Application Team
- * @version V4.2.0
- * @date 31-March-2017
- * @brief CMSIS STM32F1xx Device Peripheral Access Layer Header File.
- *
- * The file is the unique include file that the application programmer
- * is using in the C source code, usually in main.c. This file contains:
- * - Configuration section that allows to select:
- * - The STM32F1xx device used in the target application
- * - To use or not the peripheral�s drivers in application code(i.e.
- * code will be based on direct access to peripheral�s registers
- * rather than drivers API), this option is controlled by
- * "#define USE_HAL_DRIVER"
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f1xx
- * @{
- */
-
-#ifndef __STM32F1XX_H
-#define __STM32F1XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/**
- * @brief STM32 Family
- */
-#if !defined (STM32F1)
-#define STM32F1
-#endif /* STM32F1 */
-
-/* Uncomment the line below according to the target STM32L device used in your
- application
- */
-
-#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \
- !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \
- !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)
- /* #define STM32F100xB */ /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */
- /* #define STM32F100xE */ /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */
- /* #define STM32F101x6 */ /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */
- /* #define STM32F101xB */ /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */
- /* #define STM32F101xE */ /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */
- /* #define STM32F101xG */ /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */
- /* #define STM32F102x6 */ /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */
- /* #define STM32F102xB */ /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */
- /* #define STM32F103x6 */ /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */
- /* #define STM32F103xB */ /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */
- /* #define STM32F103xE */ /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */
- /* #define STM32F103xG */ /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */
- /* #define STM32F105xC */ /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */
- /* #define STM32F107xC */ /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */
-#endif
-
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler preprocessor.
- */
-
-#if !defined (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
- /*#define USE_HAL_DRIVER */
-#endif /* USE_HAL_DRIVER */
-
-/**
- * @brief CMSIS Device version number V4.2.0
- */
-#define __STM32F1_CMSIS_VERSION_MAIN (0x04) /*!< [31:24] main version */
-#define __STM32F1_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F1_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F1_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32F1_CMSIS_VERSION ((__STM32F1_CMSIS_VERSION_MAIN << 24)\
- |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\
- |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\
- |(__STM32F1_CMSIS_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Device_Included
- * @{
- */
-
-#if defined(STM32F100xB)
- #include "stm32f100xb.h"
-#elif defined(STM32F100xE)
- #include "stm32f100xe.h"
-#elif defined(STM32F101x6)
- #include "stm32f101x6.h"
-#elif defined(STM32F101xB)
- #include "stm32f101xb.h"
-#elif defined(STM32F101xE)
- #include "stm32f101xe.h"
-#elif defined(STM32F101xG)
- #include "stm32f101xg.h"
-#elif defined(STM32F102x6)
- #include "stm32f102x6.h"
-#elif defined(STM32F102xB)
- #include "stm32f102xb.h"
-#elif defined(STM32F103x6)
- #include "stm32f103x6.h"
-#elif defined(STM32F103xB)
- #include "stm32f103xb.h"
-#elif defined(STM32F103xE)
- #include "stm32f103xe.h"
-#elif defined(STM32F103xG)
- #include "stm32f103xg.h"
-#elif defined(STM32F105xC)
- #include "stm32f105xc.h"
-#elif defined(STM32F107xC)
- #include "stm32f107xc.h"
-#else
- #error "Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)"
-#endif
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_types
- * @{
- */
-typedef enum
-{
- RESET = 0,
- SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum
-{
- DISABLE = 0,
- ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum
-{
- ERROR = 0,
- SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
- * @}
- */
-
-
-/** @addtogroup Exported_macros
- * @{
- */
-#define SET_BIT(REG, BIT) ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT) ((REG) & (BIT))
-
-#define CLEAR_REG(REG) ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL) ((REG) = (VAL))
-
-#define READ_REG(REG) ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
-
-
-/**
- * @}
- */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32f1xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F1xx_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h b/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h
deleted file mode 100644
index 20628d85d5a117a5c1067662df6887a4d1a0d27e..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f10x.h
- * @author MCD Application Team
- * @version V4.2.0
- * @date 31-March-2017
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f10x_system
- * @{
- */
-
-/**
- * @brief Define to prevent recursive inclusion
- */
-#ifndef __SYSTEM_STM32F10X_H
-#define __SYSTEM_STM32F10X_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32F10x_System_Includes
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup STM32F10x_System_Exported_types
- * @{
- */
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-extern const uint8_t AHBPrescTable[16U]; /*!< AHB prescalers table values */
-extern const uint8_t APBPrescTable[8U]; /*!< APB prescalers table values */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F10x_System_Exported_Functions
- * @{
- */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F10X_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/CMSIS/Include/arm_common_tables.h b/Drivers/CMSIS/Include/arm_common_tables.h
deleted file mode 100644
index 8742a5699153c3d67e998d300ecb9045ec1b5962..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/arm_common_tables.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date: 19. October 2015
-* $Revision: V.1.4.5 a
-*
-* Project: CMSIS DSP Library
-* Title: arm_common_tables.h
-*
-* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-* - Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* - Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in
-* the documentation and/or other materials provided with the
-* distribution.
-* - Neither the name of ARM LIMITED nor the names of its contributors
-* may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
-/* extern const q31_t realCoefAQ31[1024]; */
-/* extern const q31_t realCoefBQ31[1024]; */
-extern const float32_t twiddleCoef_16[32];
-extern const float32_t twiddleCoef_32[64];
-extern const float32_t twiddleCoef_64[128];
-extern const float32_t twiddleCoef_128[256];
-extern const float32_t twiddleCoef_256[512];
-extern const float32_t twiddleCoef_512[1024];
-extern const float32_t twiddleCoef_1024[2048];
-extern const float32_t twiddleCoef_2048[4096];
-extern const float32_t twiddleCoef_4096[8192];
-#define twiddleCoef twiddleCoef_4096
-extern const q31_t twiddleCoef_16_q31[24];
-extern const q31_t twiddleCoef_32_q31[48];
-extern const q31_t twiddleCoef_64_q31[96];
-extern const q31_t twiddleCoef_128_q31[192];
-extern const q31_t twiddleCoef_256_q31[384];
-extern const q31_t twiddleCoef_512_q31[768];
-extern const q31_t twiddleCoef_1024_q31[1536];
-extern const q31_t twiddleCoef_2048_q31[3072];
-extern const q31_t twiddleCoef_4096_q31[6144];
-extern const q15_t twiddleCoef_16_q15[24];
-extern const q15_t twiddleCoef_32_q15[48];
-extern const q15_t twiddleCoef_64_q15[96];
-extern const q15_t twiddleCoef_128_q15[192];
-extern const q15_t twiddleCoef_256_q15[384];
-extern const q15_t twiddleCoef_512_q15[768];
-extern const q15_t twiddleCoef_1024_q15[1536];
-extern const q15_t twiddleCoef_2048_q15[3072];
-extern const q15_t twiddleCoef_4096_q15[6144];
-extern const float32_t twiddleCoef_rfft_32[32];
-extern const float32_t twiddleCoef_rfft_64[64];
-extern const float32_t twiddleCoef_rfft_128[128];
-extern const float32_t twiddleCoef_rfft_256[256];
-extern const float32_t twiddleCoef_rfft_512[512];
-extern const float32_t twiddleCoef_rfft_1024[1024];
-extern const float32_t twiddleCoef_rfft_2048[2048];
-extern const float32_t twiddleCoef_rfft_4096[4096];
-
-
-/* floating-point bit reversal tables */
-#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
-#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
-#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
-#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
-#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
-#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
-
-/* fixed-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
-#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
-#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
-#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
-#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
-#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
-#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
-#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
-
-/* Tables for Fast Math Sine and Cosine */
-extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
-
-#endif /* ARM_COMMON_TABLES_H */
diff --git a/Drivers/CMSIS/Include/arm_const_structs.h b/Drivers/CMSIS/Include/arm_const_structs.h
deleted file mode 100644
index 726d06eb692f0539165e4e0f675eab0b1f2b59c4..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/arm_const_structs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
-*
-* $Date: 19. March 2015
-* $Revision: V.1.4.5
-*
-* Project: CMSIS DSP Library
-* Title: arm_const_structs.h
-*
-* Description: This file has constant structs that are initialized for
-* user convenience. For example, some can be given as
-* arguments to the arm_cfft_f32() function.
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-* - Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* - Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in
-* the documentation and/or other materials provided with the
-* distribution.
-* - Neither the name of ARM LIMITED nor the names of its contributors
-* may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
- extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
-
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
- extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
-
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
- extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
-
-#endif
diff --git a/Drivers/CMSIS/Include/arm_math.h b/Drivers/CMSIS/Include/arm_math.h
deleted file mode 100644
index d33f8a9b3b57f9b146dc5da036b06281d17a4594..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/arm_math.h
+++ /dev/null
@@ -1,7154 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
-*
-* $Date: 20. October 2015
-* $Revision: V1.4.5 b
-*
-* Project: CMSIS DSP Library
-* Title: arm_math.h
-*
-* Description: Public header file for CMSIS DSP Library
-*
-* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-* - Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* - Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in
-* the documentation and/or other materials provided with the
-* distribution.
-* - Neither the name of ARM LIMITED nor the names of its contributors
-* may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
- * -------------------------------------------------------------------- */
-
-/**
- \mainpage CMSIS DSP Software Library
- *
- * Introduction
- * ------------
- *
- * This user manual describes the CMSIS DSP software library,
- * a suite of common signal processing functions for use on Cortex-M processor based devices.
- *
- * The library is divided into a number of functions each covering a specific category:
- * - Basic math functions
- * - Fast math functions
- * - Complex math functions
- * - Filters
- * - Matrix functions
- * - Transforms
- * - Motor control functions
- * - Statistical functions
- * - Support functions
- * - Interpolation functions
- *
- * The library has separate functions for operating on 8-bit integers, 16-bit integers,
- * 32-bit integer and 32-bit floating-point values.
- *
- * Using the Library
- * ------------
- *
- * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
- * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
- * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
- * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
- * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
- * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
- * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
- * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
- * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
- * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
- * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
- * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
- * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
- * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
- * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
- *
- * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
- * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
- * public header file <code> arm_math.h</code> for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
- * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
- * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
- *
- * Examples
- * --------
- *
- * The library ships with a number of examples which demonstrate how to use the library functions.
- *
- * Toolchain Support
- * ------------
- *
- * The library has been developed and tested with MDK-ARM version 5.14.0.0
- * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
- *
- * Building the Library
- * ------------
- *
- * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
- * - arm_cortexM_math.uvprojx
- *
- *
- * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
- *
- * Pre-processor Macros
- * ------------
- *
- * Each library project have differant pre-processor macros.
- *
- * - UNALIGNED_SUPPORT_DISABLE:
- *
- * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
- *
- * - ARM_MATH_BIG_ENDIAN:
- *
- * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
- *
- * - ARM_MATH_MATRIX_CHECK:
- *
- * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
- *
- * - ARM_MATH_ROUNDING:
- *
- * Define macro ARM_MATH_ROUNDING for rounding on support functions
- *
- * - ARM_MATH_CMx:
- *
- * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
- * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
- * ARM_MATH_CM7 for building the library on cortex-M7.
- *
- * - __FPU_PRESENT:
- *
- * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
- *
- * <hr>
- * CMSIS-DSP in ARM::CMSIS Pack
- * -----------------------------
- *
- * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
- * |File/Folder |Content |
- * |------------------------------|------------------------------------------------------------------------|
- * |\b CMSIS\\Documentation\\DSP | This documentation |
- * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
- * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
- * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
- *
- * <hr>
- * Revision History of CMSIS-DSP
- * ------------
- * Please refer to \ref ChangeLog_pg.
- *
- * Copyright Notice
- * ------------
- *
- * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
- */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures. For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- * typedef struct
- * {
- * uint16_t numRows; // number of rows of the matrix.
- * uint16_t numCols; // number of columns of the matrix.
- * float32_t *pData; // points to the data of the matrix.
- * } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data. The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order. That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- * pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure. For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices. For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns. If the size check fails the functions return:
- * <pre>
- * ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- * ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * <pre>
- * ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings. By default this macro is defined
- * and size checking is enabled. By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster. With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-/* ignore some GCC warnings */
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-#endif
-
-#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
-
-#if defined(ARM_MATH_CM7)
- #include "core_cm7.h"
-#elif defined (ARM_MATH_CM4)
- #include "core_cm4.h"
-#elif defined (ARM_MATH_CM3)
- #include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
- #include "core_cm0.h"
- #define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_CM0PLUS)
- #include "core_cm0plus.h"
- #define ARM_MATH_CM0_FAMILY
-#else
- #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
-#endif
-
-#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
- /**
- * @brief Macros required for reciprocal calculation in Normalized LMS
- */
-
-#define DELTA_Q31 (0x100)
-#define DELTA_Q15 0x5
-#define INDEX_MASK 0x0000003F
-#ifndef PI
-#define PI 3.14159265358979f
-#endif
-
- /**
- * @brief Macros required for SINE and COSINE Fast math approximations
- */
-
-#define FAST_MATH_TABLE_SIZE 512
-#define FAST_MATH_Q31_SHIFT (32 - 10)
-#define FAST_MATH_Q15_SHIFT (16 - 10)
-#define CONTROLLER_Q31_SHIFT (32 - 9)
-#define TABLE_SIZE 256
-#define TABLE_SPACING_Q31 0x400000
-#define TABLE_SPACING_Q15 0x80
-
- /**
- * @brief Macros required for SINE and COSINE Controller functions
- */
- /* 1.31(q31) Fixed value of 2/360 */
- /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING 0xB60B61
-
- /**
- * @brief Macro for Unaligned Support
- */
-#ifndef UNALIGNED_SUPPORT_DISABLE
- #define ALIGN4
-#else
- #if defined (__GNUC__)
- #define ALIGN4 __attribute__((aligned(4)))
- #else
- #define ALIGN4 __align(4)
- #endif
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /**
- * @brief Error status returned by some functions in the library.
- */
-
- typedef enum
- {
- ARM_MATH_SUCCESS = 0, /**< No error */
- ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
- ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
- ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
- ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
- ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
- ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
- } arm_status;
-
- /**
- * @brief 8-bit fractional data type in 1.7 format.
- */
- typedef int8_t q7_t;
-
- /**
- * @brief 16-bit fractional data type in 1.15 format.
- */
- typedef int16_t q15_t;
-
- /**
- * @brief 32-bit fractional data type in 1.31 format.
- */
- typedef int32_t q31_t;
-
- /**
- * @brief 64-bit fractional data type in 1.63 format.
- */
- typedef int64_t q63_t;
-
- /**
- * @brief 32-bit floating-point type definition.
- */
- typedef float float32_t;
-
- /**
- * @brief 64-bit floating-point type definition.
- */
- typedef double float64_t;
-
- /**
- * @brief definition to read/write two 16 bit values.
- */
-#if defined __CC_ARM
- #define __SIMD32_TYPE int32_t __packed
- #define CMSIS_UNUSED __attribute__((unused))
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #define __SIMD32_TYPE int32_t
- #define CMSIS_UNUSED __attribute__((unused))
-
-#elif defined __GNUC__
- #define __SIMD32_TYPE int32_t
- #define CMSIS_UNUSED __attribute__((unused))
-
-#elif defined __ICCARM__
- #define __SIMD32_TYPE int32_t __packed
- #define CMSIS_UNUSED
-
-#elif defined __CSMC__
- #define __SIMD32_TYPE int32_t
- #define CMSIS_UNUSED
-
-#elif defined __TASKING__
- #define __SIMD32_TYPE __unaligned int32_t
- #define CMSIS_UNUSED
-
-#else
- #error Unknown compiler
-#endif
-
-#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
-#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
-#define __SIMD64(addr) (*(int64_t **) & (addr))
-
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
- /**
- * @brief definition to pack two 16 bit values.
- */
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
- (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
- (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
-
-#endif
-
-
- /**
- * @brief definition to pack four 8 bit values.
- */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
- (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
- (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
- (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
- (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
- (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
- (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
-
-#endif
-
-
- /**
- * @brief Clips Q63 to Q31 values.
- */
- static __INLINE q31_t clip_q63_to_q31(
- q63_t x)
- {
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
- ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
- }
-
- /**
- * @brief Clips Q63 to Q15 values.
- */
- static __INLINE q15_t clip_q63_to_q15(
- q63_t x)
- {
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
- ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
- }
-
- /**
- * @brief Clips Q31 to Q7 values.
- */
- static __INLINE q7_t clip_q31_to_q7(
- q31_t x)
- {
- return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
- ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
- }
-
- /**
- * @brief Clips Q31 to Q15 values.
- */
- static __INLINE q15_t clip_q31_to_q15(
- q31_t x)
- {
- return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
- ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
- }
-
- /**
- * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
- */
-
- static __INLINE q63_t mult32x64(
- q63_t x,
- q31_t y)
- {
- return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
- (((q63_t) (x >> 32) * y)));
- }
-
-/*
- #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
- #define __CLZ __clz
- #endif
- */
-/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )
- static __INLINE uint32_t __CLZ(
- q31_t data);
-
- static __INLINE uint32_t __CLZ(
- q31_t data)
- {
- uint32_t count = 0;
- uint32_t mask = 0x80000000;
-
- while((data & mask) == 0)
- {
- count += 1u;
- mask = mask >> 1u;
- }
-
- return (count);
- }
-#endif
-
- /**
- * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
- */
-
- static __INLINE uint32_t arm_recip_q31(
- q31_t in,
- q31_t * dst,
- q31_t * pRecipTable)
- {
- q31_t out;
- uint32_t tempVal;
- uint32_t index, i;
- uint32_t signBits;
-
- if(in > 0)
- {
- signBits = ((uint32_t) (__CLZ( in) - 1));
- }
- else
- {
- signBits = ((uint32_t) (__CLZ(-in) - 1));
- }
-
- /* Convert input sample to 1.31 format */
- in = (in << signBits);
-
- /* calculation of index for initial approximated Val */
- index = (uint32_t)(in >> 24);
- index = (index & INDEX_MASK);
-
- /* 1.31 with exp 1 */
- out = pRecipTable[index];
-
- /* calculation of reciprocal value */
- /* running approximation for two iterations */
- for (i = 0u; i < 2u; i++)
- {
- tempVal = (uint32_t) (((q63_t) in * out) >> 31);
- tempVal = 0x7FFFFFFFu - tempVal;
- /* 1.31 with exp 1 */
- /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
- out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
- }
-
- /* write output */
- *dst = out;
-
- /* return num of signbits of out = 1/in value */
- return (signBits + 1u);
- }
-
-
- /**
- * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
- */
- static __INLINE uint32_t arm_recip_q15(
- q15_t in,
- q15_t * dst,
- q15_t * pRecipTable)
- {
- q15_t out = 0;
- uint32_t tempVal = 0;
- uint32_t index = 0, i = 0;
- uint32_t signBits = 0;
-
- if(in > 0)
- {
- signBits = ((uint32_t)(__CLZ( in) - 17));
- }
- else
- {
- signBits = ((uint32_t)(__CLZ(-in) - 17));
- }
-
- /* Convert input sample to 1.15 format */
- in = (in << signBits);
-
- /* calculation of index for initial approximated Val */
- index = (uint32_t)(in >> 8);
- index = (index & INDEX_MASK);
-
- /* 1.15 with exp 1 */
- out = pRecipTable[index];
-
- /* calculation of reciprocal value */
- /* running approximation for two iterations */
- for (i = 0u; i < 2u; i++)
- {
- tempVal = (uint32_t) (((q31_t) in * out) >> 15);
- tempVal = 0x7FFFu - tempVal;
- /* 1.15 with exp 1 */
- out = (q15_t) (((q31_t) out * tempVal) >> 14);
- /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
- }
-
- /* write output */
- *dst = out;
-
- /* return num of signbits of out = 1/in value */
- return (signBits + 1);
- }
-
-
- /*
- * @brief C custom defined intrinisic function for only M0 processors
- */
-#if defined(ARM_MATH_CM0_FAMILY)
- static __INLINE q31_t __SSAT(
- q31_t x,
- uint32_t y)
- {
- int32_t posMax, negMin;
- uint32_t i;
-
- posMax = 1;
- for (i = 0; i < (y - 1); i++)
- {
- posMax = posMax * 2;
- }
-
- if(x > 0)
- {
- posMax = (posMax - 1);
-
- if(x > posMax)
- {
- x = posMax;
- }
- }
- else
- {
- negMin = -posMax;
-
- if(x < negMin)
- {
- x = negMin;
- }
- }
- return (x);
- }
-#endif /* end of ARM_MATH_CM0_FAMILY */
-
-
- /*
- * @brief C custom defined intrinsic function for M3 and M0 processors
- */
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
-
- /*
- * @brief C custom defined QADD8 for M3 and M0 processors
- */
- static __INLINE uint32_t __QADD8(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s, t, u;
-
- r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
- s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
- t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
- u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
-
- return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
- }
-
-
- /*
- * @brief C custom defined QSUB8 for M3 and M0 processors
- */
- static __INLINE uint32_t __QSUB8(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s, t, u;
-
- r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
- s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
- t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
- u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
-
- return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
- }
-
-
- /*
- * @brief C custom defined QADD16 for M3 and M0 processors
- */
- static __INLINE uint32_t __QADD16(
- uint32_t x,
- uint32_t y)
- {
-/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
- q31_t r = 0, s = 0;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHADD16 for M3 and M0 processors
- */
- static __INLINE uint32_t __SHADD16(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined QSUB16 for M3 and M0 processors
- */
- static __INLINE uint32_t __QSUB16(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHSUB16 for M3 and M0 processors
- */
- static __INLINE uint32_t __SHSUB16(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined QASX for M3 and M0 processors
- */
- static __INLINE uint32_t __QASX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHASX for M3 and M0 processors
- */
- static __INLINE uint32_t __SHASX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined QSAX for M3 and M0 processors
- */
- static __INLINE uint32_t __QSAX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
- s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SHSAX for M3 and M0 processors
- */
- static __INLINE uint32_t __SHSAX(
- uint32_t x,
- uint32_t y)
- {
- q31_t r, s;
-
- r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
- s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
-
- return ((uint32_t)((s << 16) | (r )));
- }
-
-
- /*
- * @brief C custom defined SMUSDX for M3 and M0 processors
- */
- static __INLINE uint32_t __SMUSDX(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
- }
-
- /*
- * @brief C custom defined SMUADX for M3 and M0 processors
- */
- static __INLINE uint32_t __SMUADX(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
- }
-
-
- /*
- * @brief C custom defined QADD for M3 and M0 processors
- */
- static __INLINE int32_t __QADD(
- int32_t x,
- int32_t y)
- {
- return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
- }
-
-
- /*
- * @brief C custom defined QSUB for M3 and M0 processors
- */
- static __INLINE int32_t __QSUB(
- int32_t x,
- int32_t y)
- {
- return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
- }
-
-
- /*
- * @brief C custom defined SMLAD for M3 and M0 processors
- */
- static __INLINE uint32_t __SMLAD(
- uint32_t x,
- uint32_t y,
- uint32_t sum)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
- ( ((q31_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLADX for M3 and M0 processors
- */
- static __INLINE uint32_t __SMLADX(
- uint32_t x,
- uint32_t y,
- uint32_t sum)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
- ( ((q31_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLSDX for M3 and M0 processors
- */
- static __INLINE uint32_t __SMLSDX(
- uint32_t x,
- uint32_t y,
- uint32_t sum)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
- ( ((q31_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLALD for M3 and M0 processors
- */
- static __INLINE uint64_t __SMLALD(
- uint32_t x,
- uint32_t y,
- uint64_t sum)
- {
-/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
- return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
- ( ((q63_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMLALDX for M3 and M0 processors
- */
- static __INLINE uint64_t __SMLALDX(
- uint32_t x,
- uint32_t y,
- uint64_t sum)
- {
-/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
- return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
- ( ((q63_t)sum ) ) ));
- }
-
-
- /*
- * @brief C custom defined SMUAD for M3 and M0 processors
- */
- static __INLINE uint32_t __SMUAD(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
- }
-
-
- /*
- * @brief C custom defined SMUSD for M3 and M0 processors
- */
- static __INLINE uint32_t __SMUSD(
- uint32_t x,
- uint32_t y)
- {
- return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
- ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
- }
-
-
- /*
- * @brief C custom defined SXTB16 for M3 and M0 processors
- */
- static __INLINE uint32_t __SXTB16(
- uint32_t x)
- {
- return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
- ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
- }
-
-#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-
-
- /**
- * @brief Instance structure for the Q7 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- } arm_fir_instance_q7;
-
- /**
- * @brief Instance structure for the Q15 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- } arm_fir_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- } arm_fir_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- } arm_fir_instance_f32;
-
-
- /**
- * @brief Processing function for the Q7 FIR filter.
- * @param[in] S points to an instance of the Q7 FIR filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_q7(
- const arm_fir_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q7 FIR filter.
- * @param[in,out] S points to an instance of the Q7 FIR structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed.
- */
- void arm_fir_init_q7(
- arm_fir_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 FIR filter.
- * @param[in] S points to an instance of the Q15 FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q15 FIR filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_fast_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 FIR filter.
- * @param[in,out] S points to an instance of the Q15 FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
- * <code>numTaps</code> is not a supported value.
- */
- arm_status arm_fir_init_q15(
- arm_fir_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 FIR filter.
- * @param[in] S points to an instance of the Q31 FIR filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q31 FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_fast_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR filter.
- * @param[in,out] S points to an instance of the Q31 FIR structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- */
- void arm_fir_init_q31(
- arm_fir_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point FIR filter.
- * @param[in] S points to an instance of the floating-point FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_f32(
- const arm_fir_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point FIR filter.
- * @param[in,out] S points to an instance of the floating-point FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- */
- void arm_fir_init_f32(
- arm_fir_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 Biquad cascade filter.
- */
- typedef struct
- {
- int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
- } arm_biquad_casd_df1_inst_q15;
-
- /**
- * @brief Instance structure for the Q31 Biquad cascade filter.
- */
- typedef struct
- {
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
- } arm_biquad_casd_df1_inst_q31;
-
- /**
- * @brief Instance structure for the floating-point Biquad cascade filter.
- */
- typedef struct
- {
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_casd_df1_inst_f32;
-
-
- /**
- * @brief Processing function for the Q15 Biquad cascade filter.
- * @param[in] S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 Biquad cascade filter.
- * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
- */
- void arm_biquad_cascade_df1_init_q15(
- arm_biquad_casd_df1_inst_q15 * S,
- uint8_t numStages,
- q15_t * pCoeffs,
- q15_t * pState,
- int8_t postShift);
-
-
- /**
- * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_fast_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 Biquad cascade filter
- * @param[in] S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_fast_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 Biquad cascade filter.
- * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
- */
- void arm_biquad_cascade_df1_init_q31(
- arm_biquad_casd_df1_inst_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q31_t * pState,
- int8_t postShift);
-
-
- /**
- * @brief Processing function for the floating-point Biquad cascade filter.
- * @param[in] S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df1_f32(
- const arm_biquad_casd_df1_inst_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point Biquad cascade filter.
- * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_df1_init_f32(
- arm_biquad_casd_df1_inst_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Instance structure for the floating-point matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- float32_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_f32;
-
-
- /**
- * @brief Instance structure for the floating-point matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- float64_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_f64;
-
- /**
- * @brief Instance structure for the Q15 matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- q15_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 matrix structure.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- q31_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_q31;
-
-
- /**
- * @brief Floating-point matrix addition.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_add_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix addition.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_add_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
-
-
- /**
- * @brief Q31 matrix addition.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_add_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point, complex, matrix multiplication.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_cmplx_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15, complex, matrix multiplication.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_cmplx_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pScratch);
-
-
- /**
- * @brief Q31, complex, matrix multiplication.
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_cmplx_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix transpose.
- * @param[in] pSrc points to the input matrix
- * @param[out] pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_trans_f32(
- const arm_matrix_instance_f32 * pSrc,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix transpose.
- * @param[in] pSrc points to the input matrix
- * @param[out] pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_trans_q15(
- const arm_matrix_instance_q15 * pSrc,
- arm_matrix_instance_q15 * pDst);
-
-
- /**
- * @brief Q31 matrix transpose.
- * @param[in] pSrc points to the input matrix
- * @param[out] pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_trans_q31(
- const arm_matrix_instance_q31 * pSrc,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix multiplication
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix multiplication
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @param[in] pState points to the array for storing intermediate results
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
-
-
- /**
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @param[in] pState points to the array for storing intermediate results
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_mult_fast_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
-
-
- /**
- * @brief Q31 matrix multiplication
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_mult_fast_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix subtraction
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_sub_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix subtraction
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_sub_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
-
-
- /**
- * @brief Q31 matrix subtraction
- * @param[in] pSrcA points to the first input matrix structure
- * @param[in] pSrcB points to the second input matrix structure
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_sub_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix scaling.
- * @param[in] pSrc points to the input matrix
- * @param[in] scale scale factor
- * @param[out] pDst points to the output matrix
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_scale_f32(
- const arm_matrix_instance_f32 * pSrc,
- float32_t scale,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix scaling.
- * @param[in] pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to output matrix
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_scale_q15(
- const arm_matrix_instance_q15 * pSrc,
- q15_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q15 * pDst);
-
-
- /**
- * @brief Q31 matrix scaling.
- * @param[in] pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
- arm_status arm_mat_scale_q31(
- const arm_matrix_instance_q31 * pSrc,
- q31_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Q31 matrix initialization.
- * @param[in,out] S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] pData points to the matrix data array.
- */
- void arm_mat_init_q31(
- arm_matrix_instance_q31 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q31_t * pData);
-
-
- /**
- * @brief Q15 matrix initialization.
- * @param[in,out] S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] pData points to the matrix data array.
- */
- void arm_mat_init_q15(
- arm_matrix_instance_q15 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q15_t * pData);
-
-
- /**
- * @brief Floating-point matrix initialization.
- * @param[in,out] S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] pData points to the matrix data array.
- */
- void arm_mat_init_f32(
- arm_matrix_instance_f32 * S,
- uint16_t nRows,
- uint16_t nColumns,
- float32_t * pData);
-
-
-
- /**
- * @brief Instance structure for the Q15 PID Control.
- */
- typedef struct
- {
- q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
-#ifdef ARM_MATH_CM0_FAMILY
- q15_t A1;
- q15_t A2;
-#else
- q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
- q15_t state[3]; /**< The state array of length 3. */
- q15_t Kp; /**< The proportional gain. */
- q15_t Ki; /**< The integral gain. */
- q15_t Kd; /**< The derivative gain. */
- } arm_pid_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 PID Control.
- */
- typedef struct
- {
- q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
- q31_t A2; /**< The derived gain, A2 = Kd . */
- q31_t state[3]; /**< The state array of length 3. */
- q31_t Kp; /**< The proportional gain. */
- q31_t Ki; /**< The integral gain. */
- q31_t Kd; /**< The derivative gain. */
- } arm_pid_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point PID Control.
- */
- typedef struct
- {
- float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
- float32_t A2; /**< The derived gain, A2 = Kd . */
- float32_t state[3]; /**< The state array of length 3. */
- float32_t Kp; /**< The proportional gain. */
- float32_t Ki; /**< The integral gain. */
- float32_t Kd; /**< The derivative gain. */
- } arm_pid_instance_f32;
-
-
-
- /**
- * @brief Initialization function for the floating-point PID Control.
- * @param[in,out] S points to an instance of the PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- */
- void arm_pid_init_f32(
- arm_pid_instance_f32 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the floating-point PID Control.
- * @param[in,out] S is an instance of the floating-point PID Control structure
- */
- void arm_pid_reset_f32(
- arm_pid_instance_f32 * S);
-
-
- /**
- * @brief Initialization function for the Q31 PID Control.
- * @param[in,out] S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- */
- void arm_pid_init_q31(
- arm_pid_instance_q31 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the Q31 PID Control.
- * @param[in,out] S points to an instance of the Q31 PID Control structure
- */
-
- void arm_pid_reset_q31(
- arm_pid_instance_q31 * S);
-
-
- /**
- * @brief Initialization function for the Q15 PID Control.
- * @param[in,out] S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- */
- void arm_pid_init_q15(
- arm_pid_instance_q15 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the Q15 PID Control.
- * @param[in,out] S points to an instance of the q15 PID Control structure
- */
- void arm_pid_reset_q15(
- arm_pid_instance_q15 * S);
-
-
- /**
- * @brief Instance structure for the floating-point Linear Interpolate function.
- */
- typedef struct
- {
- uint32_t nValues; /**< nValues */
- float32_t x1; /**< x1 */
- float32_t xSpacing; /**< xSpacing */
- float32_t *pYData; /**< pointer to the table of Y values */
- } arm_linear_interp_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- float32_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_f32;
-
- /**
- * @brief Instance structure for the Q31 bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q31_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q31;
-
- /**
- * @brief Instance structure for the Q15 bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q15_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q15;
-
- /**
- * @brief Instance structure for the Q15 bilinear interpolation function.
- */
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q7_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q7;
-
-
- /**
- * @brief Q7 vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point vector multiplication.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_mult_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix2_instance_q15;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_q15(
- arm_cfft_radix2_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_q15(
- const arm_cfft_radix2_instance_q15 * S,
- q15_t * pSrc);
-
-
- /**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q15_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix4_instance_q15;
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_q15(
- arm_cfft_radix4_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix4_q15(
- const arm_cfft_radix4_instance_q15 * S,
- q15_t * pSrc);
-
- /**
- * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q31_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix2_instance_q31;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_q31(
- arm_cfft_radix2_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_q31(
- const arm_cfft_radix2_instance_q31 * S,
- q31_t * pSrc);
-
- /**
- * @brief Instance structure for the Q31 CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q31_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix4_instance_q31;
-
-/* Deprecated */
- void arm_cfft_radix4_q31(
- const arm_cfft_radix4_instance_q31 * S,
- q31_t * pSrc);
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_q31(
- arm_cfft_radix4_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- float32_t onebyfftLen; /**< value of 1/fftLen. */
- } arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_f32(
- arm_cfft_radix2_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_f32(
- const arm_cfft_radix2_instance_f32 * S,
- float32_t * pSrc);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- float32_t onebyfftLen; /**< value of 1/fftLen. */
- } arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_f32(
- arm_cfft_radix4_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix4_f32(
- const arm_cfft_radix4_instance_f32 * S,
- float32_t * pSrc);
-
- /**
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_q15;
-
-void arm_cfft_q15(
- const arm_cfft_instance_q15 * S,
- q15_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the fixed-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_q31;
-
-void arm_cfft_q31(
- const arm_cfft_instance_q31 * S,
- q31_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_f32;
-
- void arm_cfft_f32(
- const arm_cfft_instance_f32 * S,
- float32_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the Q15 RFFT/RIFFT function.
- */
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_q15;
-
- arm_status arm_rfft_init_q15(
- arm_rfft_instance_q15 * S,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_q15(
- const arm_rfft_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst);
-
- /**
- * @brief Instance structure for the Q31 RFFT/RIFFT function.
- */
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_q31;
-
- arm_status arm_rfft_init_q31(
- arm_rfft_instance_q31 * S,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_q31(
- const arm_rfft_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst);
-
- /**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint16_t fftLenBy2; /**< length of the complex FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_f32;
-
- arm_status arm_rfft_init_f32(
- arm_rfft_instance_f32 * S,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_f32(
- const arm_rfft_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst);
-
- /**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
-typedef struct
- {
- arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
- uint16_t fftLenRFFT; /**< length of the real sequence */
- float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
- } arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
- arm_rfft_fast_instance_f32 * S,
- uint16_t fftLen);
-
-void arm_rfft_fast_f32(
- arm_rfft_fast_instance_f32 * S,
- float32_t * p, float32_t * pOut,
- uint8_t ifftFlag);
-
- /**
- * @brief Instance structure for the floating-point DCT4/IDCT4 function.
- */
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- float32_t normalize; /**< normalizing factor. */
- float32_t *pTwiddle; /**< points to the twiddle factor table. */
- float32_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_f32;
-
-
- /**
- * @brief Initialization function for the floating-point DCT4/IDCT4.
- * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
- * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
- * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
- */
- arm_status arm_dct4_init_f32(
- arm_dct4_instance_f32 * S,
- arm_rfft_instance_f32 * S_RFFT,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- float32_t normalize);
-
-
- /**
- * @brief Processing function for the floating-point DCT4/IDCT4.
- * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
- * @param[in] pState points to state buffer.
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
- */
- void arm_dct4_f32(
- const arm_dct4_instance_f32 * S,
- float32_t * pState,
- float32_t * pInlineBuffer);
-
-
- /**
- * @brief Instance structure for the Q31 DCT4/IDCT4 function.
- */
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- q31_t normalize; /**< normalizing factor. */
- q31_t *pTwiddle; /**< points to the twiddle factor table. */
- q31_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_q31;
-
-
- /**
- * @brief Initialization function for the Q31 DCT4/IDCT4.
- * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
- * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
- * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
- */
- arm_status arm_dct4_init_q31(
- arm_dct4_instance_q31 * S,
- arm_rfft_instance_q31 * S_RFFT,
- arm_cfft_radix4_instance_q31 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q31_t normalize);
-
-
- /**
- * @brief Processing function for the Q31 DCT4/IDCT4.
- * @param[in] S points to an instance of the Q31 DCT4 structure.
- * @param[in] pState points to state buffer.
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
- */
- void arm_dct4_q31(
- const arm_dct4_instance_q31 * S,
- q31_t * pState,
- q31_t * pInlineBuffer);
-
-
- /**
- * @brief Instance structure for the Q15 DCT4/IDCT4 function.
- */
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- q15_t normalize; /**< normalizing factor. */
- q15_t *pTwiddle; /**< points to the twiddle factor table. */
- q15_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_q15;
-
-
- /**
- * @brief Initialization function for the Q15 DCT4/IDCT4.
- * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
- * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
- * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
- */
- arm_status arm_dct4_init_q15(
- arm_dct4_instance_q15 * S,
- arm_rfft_instance_q15 * S_RFFT,
- arm_cfft_radix4_instance_q15 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q15_t normalize);
-
-
- /**
- * @brief Processing function for the Q15 DCT4/IDCT4.
- * @param[in] S points to an instance of the Q15 DCT4 structure.
- * @param[in] pState points to state buffer.
- * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
- */
- void arm_dct4_q15(
- const arm_dct4_instance_q15 * S,
- q15_t * pState,
- q15_t * pInlineBuffer);
-
-
- /**
- * @brief Floating-point vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q7 vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector addition.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_add_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q7 vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector subtraction.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- */
- void arm_sub_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a floating-point vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scale scale factor to be applied
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_f32(
- float32_t * pSrc,
- float32_t scale,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a Q7 vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_q7(
- q7_t * pSrc,
- q7_t scaleFract,
- int8_t shift,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a Q15 vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_q15(
- q15_t * pSrc,
- q15_t scaleFract,
- int8_t shift,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Multiplies a Q31 vector by a scalar.
- * @param[in] pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_scale_q31(
- q31_t * pSrc,
- q31_t scaleFract,
- int8_t shift,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q7 vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q15 vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Q31 vector absolute value.
- * @param[in] pSrc points to the input buffer
- * @param[out] pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- */
- void arm_abs_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Dot product of floating-point vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t blockSize,
- float32_t * result);
-
-
- /**
- * @brief Dot product of Q7 vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- uint32_t blockSize,
- q31_t * result);
-
-
- /**
- * @brief Dot product of Q15 vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
-
-
- /**
- * @brief Dot product of Q31 vectors.
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] result output result returned here
- */
- void arm_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
-
-
- /**
- * @brief Shifts the elements of a Q7 vector a specified number of bits.
- * @param[in] pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_shift_q7(
- q7_t * pSrc,
- int8_t shiftBits,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Shifts the elements of a Q15 vector a specified number of bits.
- * @param[in] pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_shift_q15(
- q15_t * pSrc,
- int8_t shiftBits,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Shifts the elements of a Q31 vector a specified number of bits.
- * @param[in] pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_shift_q31(
- q31_t * pSrc,
- int8_t shiftBits,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a floating-point vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_f32(
- float32_t * pSrc,
- float32_t offset,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a Q7 vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_q7(
- q7_t * pSrc,
- q7_t offset,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a Q15 vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_q15(
- q15_t * pSrc,
- q15_t offset,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Adds a constant offset to a Q31 vector.
- * @param[in] pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_offset_q31(
- q31_t * pSrc,
- q31_t offset,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a floating-point vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a Q7 vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a Q15 vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Negates the elements of a Q31 vector.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- */
- void arm_negate_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a floating-point vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a Q7 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a Q15 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Copies the elements of a Q31 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_copy_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a floating-point vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_f32(
- float32_t value,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a Q7 vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_q7(
- q7_t value,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a Q15 vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_q15(
- q15_t value,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Fills a constant value into a Q31 vector.
- * @param[in] value input value to be filled
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_fill_q31(
- q31_t value,
- q31_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- */
- void arm_conv_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
-
-
- /**
- * @brief Convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- */
- void arm_conv_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- */
- void arm_conv_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
- /**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
- /**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- */
- void arm_conv_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Convolution of Q31 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Convolution of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- */
- void arm_conv_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Convolution of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
- */
- void arm_conv_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
-
-
- /**
- * @brief Partial convolution of floating-point sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Partial convolution of Q31 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q7 sequences
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-/**
- * @brief Partial convolution of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
- arm_status arm_conv_partial_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Instance structure for the Q15 FIR decimator.
- */
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR decimator.
- */
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR decimator.
- */
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_f32;
-
-
- /**
- * @brief Processing function for the floating-point FIR decimator.
- * @param[in] S points to an instance of the floating-point FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_f32(
- const arm_fir_decimate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point FIR decimator.
- * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
- arm_status arm_fir_decimate_init_f32(
- arm_fir_decimate_instance_f32 * S,
- uint16_t numTaps,
- uint8_t M,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 FIR decimator.
- * @param[in] S points to an instance of the Q15 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q15 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_fast_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 FIR decimator.
- * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
- arm_status arm_fir_decimate_init_q15(
- arm_fir_decimate_instance_q15 * S,
- uint16_t numTaps,
- uint8_t M,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 FIR decimator.
- * @param[in] S points to an instance of the Q31 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_q31(
- const arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] S points to an instance of the Q31 FIR decimator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_decimate_fast_q31(
- arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR decimator.
- * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
- arm_status arm_fir_decimate_init_q31(
- arm_fir_decimate_instance_q31 * S,
- uint16_t numTaps,
- uint8_t M,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 FIR interpolator.
- */
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
- } arm_fir_interpolate_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR interpolator.
- */
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
- } arm_fir_interpolate_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR interpolator.
- */
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
- } arm_fir_interpolate_instance_f32;
-
-
- /**
- * @brief Processing function for the Q15 FIR interpolator.
- * @param[in] S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_interpolate_q15(
- const arm_fir_interpolate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 FIR interpolator.
- * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
- arm_status arm_fir_interpolate_init_q15(
- arm_fir_interpolate_instance_q15 * S,
- uint8_t L,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 FIR interpolator.
- * @param[in] S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_interpolate_q31(
- const arm_fir_interpolate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR interpolator.
- * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
- arm_status arm_fir_interpolate_init_q31(
- arm_fir_interpolate_instance_q31 * S,
- uint8_t L,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point FIR interpolator.
- * @param[in] S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_interpolate_f32(
- const arm_fir_interpolate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point FIR interpolator.
- * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] pCoeffs points to the filter coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
- arm_status arm_fir_interpolate_init_f32(
- arm_fir_interpolate_instance_f32 * S,
- uint8_t L,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the high precision Q31 Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
- q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
- } arm_biquad_cas_df1_32x64_ins_q31;
-
-
- /**
- * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cas_df1_32x64_q31(
- const arm_biquad_cas_df1_32x64_ins_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
- */
- void arm_biquad_cas_df1_32x64_init_q31(
- arm_biquad_cas_df1_32x64_ins_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q63_t * pState,
- uint8_t postShift);
-
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_df2T_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_stereo_df2T_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
- float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_df2T_instance_f64;
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in] S points to an instance of the filter data structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df2T_f32(
- const arm_biquad_cascade_df2T_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
- * @param[in] S points to an instance of the filter data structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_stereo_df2T_f32(
- const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in] S points to an instance of the filter data structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_biquad_cascade_df2T_f64(
- const arm_biquad_cascade_df2T_instance_f64 * S,
- float64_t * pSrc,
- float64_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_df2T_init_f32(
- arm_biquad_cascade_df2T_instance_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_stereo_df2T_init_f32(
- arm_biquad_cascade_stereo_df2T_instance_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] pCoeffs points to the filter coefficients.
- * @param[in] pState points to the state buffer.
- */
- void arm_biquad_cascade_df2T_init_f64(
- arm_biquad_cascade_df2T_instance_f64 * S,
- uint8_t numStages,
- float64_t * pCoeffs,
- float64_t * pState);
-
-
- /**
- * @brief Instance structure for the Q15 FIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_f32;
-
-
- /**
- * @brief Initialization function for the Q15 FIR lattice filter.
- * @param[in] S points to an instance of the Q15 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] pState points to the state buffer. The array is of length numStages.
- */
- void arm_fir_lattice_init_q15(
- arm_fir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pCoeffs,
- q15_t * pState);
-
-
- /**
- * @brief Processing function for the Q15 FIR lattice filter.
- * @param[in] S points to an instance of the Q15 FIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_lattice_q15(
- const arm_fir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR lattice filter.
- * @param[in] S points to an instance of the Q31 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] pState points to the state buffer. The array is of length numStages.
- */
- void arm_fir_lattice_init_q31(
- arm_fir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pCoeffs,
- q31_t * pState);
-
-
- /**
- * @brief Processing function for the Q31 FIR lattice filter.
- * @param[in] S points to an instance of the Q31 FIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_lattice_q31(
- const arm_fir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] S points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] pState points to the state buffer. The array is of length numStages.
- */
- void arm_fir_lattice_init_f32(
- arm_fir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Processing function for the floating-point FIR lattice filter.
- * @param[in] S points to an instance of the floating-point FIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- */
- void arm_fir_lattice_f32(
- const arm_fir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_f32;
-
-
- /**
- * @brief Processing function for the floating-point IIR lattice filter.
- * @param[in] S points to an instance of the floating-point IIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_f32(
- const arm_iir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point IIR lattice filter.
- * @param[in] S points to an instance of the floating-point IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_init_f32(
- arm_iir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pkCoeffs,
- float32_t * pvCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 IIR lattice filter.
- * @param[in] S points to an instance of the Q31 IIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_q31(
- const arm_iir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 IIR lattice filter.
- * @param[in] S points to an instance of the Q31 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_init_q31(
- arm_iir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pkCoeffs,
- q31_t * pvCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 IIR lattice filter.
- * @param[in] S points to an instance of the Q15 IIR lattice structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_iir_lattice_q15(
- const arm_iir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
- * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process per call.
- */
- void arm_iir_lattice_init_q15(
- arm_iir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pkCoeffs,
- q15_t * pvCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the floating-point LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- float32_t mu; /**< step size that controls filter coefficient updates. */
- } arm_lms_instance_f32;
-
-
- /**
- * @brief Processing function for floating-point LMS filter.
- * @param[in] S points to an instance of the floating-point LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_f32(
- const arm_lms_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for floating-point LMS filter.
- * @param[in] S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to the coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_init_f32(
- arm_lms_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q15_t mu; /**< step size that controls filter coefficient updates. */
- uint32_t postShift; /**< bit shift applied to coefficients. */
- } arm_lms_instance_q15;
-
-
- /**
- * @brief Initialization function for the Q15 LMS filter.
- * @param[in] S points to an instance of the Q15 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to the coefficient buffer.
- * @param[in] pState points to the state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_init_q15(
- arm_lms_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint32_t postShift);
-
-
- /**
- * @brief Processing function for Q15 LMS filter.
- * @param[in] S points to an instance of the Q15 LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_q15(
- const arm_lms_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q31 LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q31_t mu; /**< step size that controls filter coefficient updates. */
- uint32_t postShift; /**< bit shift applied to coefficients. */
- } arm_lms_instance_q31;
-
-
- /**
- * @brief Processing function for Q31 LMS filter.
- * @param[in] S points to an instance of the Q15 LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_q31(
- const arm_lms_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q31 LMS filter.
- * @param[in] S points to an instance of the Q31 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_init_q31(
- arm_lms_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint32_t postShift);
-
-
- /**
- * @brief Instance structure for the floating-point normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- float32_t mu; /**< step size that control filter coefficient updates. */
- float32_t energy; /**< saves previous frame energy. */
- float32_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_f32;
-
-
- /**
- * @brief Processing function for floating-point normalized LMS filter.
- * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_f32(
- arm_lms_norm_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for floating-point normalized LMS filter.
- * @param[in] S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_init_f32(
- arm_lms_norm_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q31 normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q31_t mu; /**< step size that controls filter coefficient updates. */
- uint8_t postShift; /**< bit shift applied to coefficients. */
- q31_t *recipTable; /**< points to the reciprocal initial value table. */
- q31_t energy; /**< saves previous frame energy. */
- q31_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_q31;
-
-
- /**
- * @brief Processing function for Q31 normalized LMS filter.
- * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_q31(
- arm_lms_norm_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q31 normalized LMS filter.
- * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_norm_init_q31(
- arm_lms_norm_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint8_t postShift);
-
-
- /**
- * @brief Instance structure for the Q15 normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< Number of coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q15_t mu; /**< step size that controls filter coefficient updates. */
- uint8_t postShift; /**< bit shift applied to coefficients. */
- q15_t *recipTable; /**< Points to the reciprocal initial value table. */
- q15_t energy; /**< saves previous frame energy. */
- q15_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_q15;
-
-
- /**
- * @brief Processing function for Q15 normalized LMS filter.
- * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] pSrc points to the block of input data.
- * @param[in] pRef points to the block of reference data.
- * @param[out] pOut points to the block of output data.
- * @param[out] pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- */
- void arm_lms_norm_q15(
- arm_lms_norm_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q15 normalized LMS filter.
- * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] pCoeffs points to coefficient buffer.
- * @param[in] pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- */
- void arm_lms_norm_init_q15(
- arm_lms_norm_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint8_t postShift);
-
-
- /**
- * @brief Correlation of floating-point sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
-
-
- /**
- * @brief Correlation of Q15 sequences
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- */
- void arm_correlate_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch);
-
-
- /**
- * @brief Correlation of Q15 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
-
- void arm_correlate_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
- /**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
-
- void arm_correlate_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
- /**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- */
- void arm_correlate_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch);
-
-
- /**
- * @brief Correlation of Q31 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Correlation of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- */
- void arm_correlate_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Correlation of Q7 sequences.
- * @param[in] pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- */
- void arm_correlate_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
-
-
- /**
- * @brief Instance structure for the floating-point sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_f32;
-
- /**
- * @brief Instance structure for the Q31 sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q31;
-
- /**
- * @brief Instance structure for the Q15 sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q15;
-
- /**
- * @brief Instance structure for the Q7 sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q7;
-
-
- /**
- * @brief Processing function for the floating-point sparse FIR filter.
- * @param[in] S points to an instance of the floating-point sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_f32(
- arm_fir_sparse_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- float32_t * pScratchIn,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point sparse FIR filter.
- * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_f32(
- arm_fir_sparse_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 sparse FIR filter.
- * @param[in] S points to an instance of the Q31 sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_q31(
- arm_fir_sparse_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- q31_t * pScratchIn,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 sparse FIR filter.
- * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_q31(
- arm_fir_sparse_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 sparse FIR filter.
- * @param[in] S points to an instance of the Q15 sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_q15(
- arm_fir_sparse_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- q15_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 sparse FIR filter.
- * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_q15(
- arm_fir_sparse_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q7 sparse FIR filter.
- * @param[in] S points to an instance of the Q7 sparse FIR structure.
- * @param[in] pSrc points to the block of input data.
- * @param[out] pDst points to the block of output data
- * @param[in] pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- */
- void arm_fir_sparse_q7(
- arm_fir_sparse_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- q7_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q7 sparse FIR filter.
- * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] pCoeffs points to the array of filter coefficients.
- * @param[in] pState points to the state buffer.
- * @param[in] pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- */
- void arm_fir_sparse_init_q7(
- arm_fir_sparse_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /**
- * @brief Floating-point sin_cos function.
- * @param[in] theta input value in degrees
- * @param[out] pSinVal points to the processed sine output.
- * @param[out] pCosVal points to the processed cos output.
- */
- void arm_sin_cos_f32(
- float32_t theta,
- float32_t * pSinVal,
- float32_t * pCosVal);
-
-
- /**
- * @brief Q31 sin_cos function.
- * @param[in] theta scaled input value in degrees
- * @param[out] pSinVal points to the processed sine output.
- * @param[out] pCosVal points to the processed cosine output.
- */
- void arm_sin_cos_q31(
- q31_t theta,
- q31_t * pSinVal,
- q31_t * pCosVal);
-
-
- /**
- * @brief Floating-point complex conjugate.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_conj_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex conjugate.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_conj_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex conjugate.
- * @param[in] pSrc points to the input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_conj_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Floating-point complex magnitude squared
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_squared_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex magnitude squared
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_squared_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex magnitude squared
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_squared_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup PID PID Motor Control
- *
- * A Proportional Integral Derivative (PID) controller is a generic feedback control
- * loop mechanism widely used in industrial control systems.
- * A PID controller is the most commonly used type of feedback controller.
- *
- * This set of functions implements (PID) controllers
- * for Q15, Q31, and floating-point data types. The functions operate on a single sample
- * of data and each call to the function returns a single processed value.
- * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
- * is the input sample value. The functions return the output value.
- *
- * \par Algorithm:
- * <pre>
- * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
- * A0 = Kp + Ki + Kd
- * A1 = (-Kp ) - (2 * Kd )
- * A2 = Kd </pre>
- *
- * \par
- * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
- *
- * \par
- * \image html PID.gif "Proportional Integral Derivative Controller"
- *
- * \par
- * The PID controller calculates an "error" value as the difference between
- * the measured output and the reference input.
- * The controller attempts to minimize the error by adjusting the process control inputs.
- * The proportional value determines the reaction to the current error,
- * the integral value determines the reaction based on the sum of recent errors,
- * and the derivative value determines the reaction based on the rate at which the error has been changing.
- *
- * \par Instance Structure
- * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
- * A separate instance structure must be defined for each PID Controller.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Reset Functions
- * There is also an associated reset function for each data type which clears the state array.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
- * - Zeros out the values in the state buffer.
- *
- * \par
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
- *
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the PID Controller functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup PID
- * @{
- */
-
- /**
- * @brief Process function for the floating-point PID Control.
- * @param[in,out] S is an instance of the floating-point PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- */
- static __INLINE float32_t arm_pid_f32(
- arm_pid_instance_f32 * S,
- float32_t in)
- {
- float32_t out;
-
- /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
- out = (S->A0 * in) +
- (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- * @brief Process function for the Q31 PID Control.
- * @param[in,out] S points to an instance of the Q31 PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clip.
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
- */
- static __INLINE q31_t arm_pid_q31(
- arm_pid_instance_q31 * S,
- q31_t in)
- {
- q63_t acc;
- q31_t out;
-
- /* acc = A0 * x[n] */
- acc = (q63_t) S->A0 * in;
-
- /* acc += A1 * x[n-1] */
- acc += (q63_t) S->A1 * S->state[0];
-
- /* acc += A2 * x[n-2] */
- acc += (q63_t) S->A2 * S->state[1];
-
- /* convert output to 1.31 format to add y[n-1] */
- out = (q31_t) (acc >> 31u);
-
- /* out += y[n-1] */
- out += S->state[2];
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
- }
-
-
- /**
- * @brief Process function for the Q15 PID Control.
- * @param[in,out] S points to an instance of the Q15 PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.
- */
- static __INLINE q15_t arm_pid_q15(
- arm_pid_instance_q15 * S,
- q15_t in)
- {
- q63_t acc;
- q15_t out;
-
-#ifndef ARM_MATH_CM0_FAMILY
- __SIMD32_TYPE *vstate;
-
- /* Implementation of PID controller */
-
- /* acc = A0 * x[n] */
- acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- vstate = __SIMD32_CONST(S->state);
- acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
-#else
- /* acc = A0 * x[n] */
- acc = ((q31_t) S->A0) * in;
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- acc += (q31_t) S->A1 * S->state[0];
- acc += (q31_t) S->A2 * S->state[1];
-#endif
-
- /* acc += y[n-1] */
- acc += (q31_t) S->state[2] << 15;
-
- /* saturate the output */
- out = (q15_t) (__SSAT((acc >> 15), 16));
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
- }
-
- /**
- * @} end of PID group
- */
-
-
- /**
- * @brief Floating-point matrix inverse.
- * @param[in] src points to the instance of the input floating-point matrix structure.
- * @param[out] dst points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
- arm_status arm_mat_inverse_f32(
- const arm_matrix_instance_f32 * src,
- arm_matrix_instance_f32 * dst);
-
-
- /**
- * @brief Floating-point matrix inverse.
- * @param[in] src points to the instance of the input floating-point matrix structure.
- * @param[out] dst points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
- arm_status arm_mat_inverse_f64(
- const arm_matrix_instance_f64 * src,
- arm_matrix_instance_f64 * dst);
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup clarke Vector Clarke Transform
- * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
- * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
- * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
- * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
- * \image html clarke.gif Stator current space vector and its components in (a,b).
- * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
- * can be calculated using only <code>Ia</code> and <code>Ib</code>.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeFormula.gif
- * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
- * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup clarke
- * @{
- */
-
- /**
- *
- * @brief Floating-point Clarke transform
- * @param[in] Ia input three-phase coordinate <code>a</code>
- * @param[in] Ib input three-phase coordinate <code>b</code>
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- */
- static __INLINE void arm_clarke_f32(
- float32_t Ia,
- float32_t Ib,
- float32_t * pIalpha,
- float32_t * pIbeta)
- {
- /* Calculate pIalpha using the equation, pIalpha = Ia */
- *pIalpha = Ia;
-
- /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
- *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
- }
-
-
- /**
- * @brief Clarke transform for Q31 version
- * @param[in] Ia input three-phase coordinate <code>a</code>
- * @param[in] Ib input three-phase coordinate <code>b</code>
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
- static __INLINE void arm_clarke_q31(
- q31_t Ia,
- q31_t Ib,
- q31_t * pIalpha,
- q31_t * pIbeta)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
-
- /* Calculating pIalpha from Ia by equation pIalpha = Ia */
- *pIalpha = Ia;
-
- /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
- product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
- /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
- product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
- /* pIbeta is calculated by adding the intermediate products */
- *pIbeta = __QADD(product1, product2);
- }
-
- /**
- * @} end of clarke group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to Q31 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_q7_to_q31(
- q7_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup inv_clarke Vector Inverse Clarke Transform
- * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeInvFormula.gif
- * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
- * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup inv_clarke
- * @{
- */
-
- /**
- * @brief Floating-point Inverse Clarke transform
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha
- * @param[in] Ibeta input two-phase orthogonal vector axis beta
- * @param[out] pIa points to output three-phase coordinate <code>a</code>
- * @param[out] pIb points to output three-phase coordinate <code>b</code>
- */
- static __INLINE void arm_inv_clarke_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pIa,
- float32_t * pIb)
- {
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */
- *pIa = Ialpha;
-
- /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
- *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
- }
-
-
- /**
- * @brief Inverse Clarke transform for Q31 version
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha
- * @param[in] Ibeta input two-phase orthogonal vector axis beta
- * @param[out] pIa points to output three-phase coordinate <code>a</code>
- * @param[out] pIb points to output three-phase coordinate <code>b</code>
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the subtraction, hence there is no risk of overflow.
- */
- static __INLINE void arm_inv_clarke_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pIa,
- q31_t * pIb)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
-
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */
- *pIa = Ialpha;
-
- /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
- product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
- /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
- product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
- /* pIb is calculated by subtracting the products */
- *pIb = __QSUB(product2, product1);
- }
-
- /**
- * @} end of inv_clarke group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to Q15 vector.
- * @param[in] pSrc input pointer
- * @param[out] pDst output pointer
- * @param[in] blockSize number of samples to process
- */
- void arm_q7_to_q15(
- q7_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup park Vector Park Transform
- *
- * Forward Park transform converts the input two-coordinate vector to flux and torque components.
- * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
- * from the stationary to the moving reference frame and control the spatial relationship between
- * the stator vector current and rotor flux vector.
- * If we consider the d axis aligned with the rotor flux, the diagram below shows the
- * current vector and the relationship from the two reference frames:
- * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkFormula.gif
- * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
- * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup park
- * @{
- */
-
- /**
- * @brief Floating-point Park transform
- * @param[in] Ialpha input two-phase vector coordinate alpha
- * @param[in] Ibeta input two-phase vector coordinate beta
- * @param[out] pId points to output rotor reference frame d
- * @param[out] pIq points to output rotor reference frame q
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- *
- * The function implements the forward Park transform.
- *
- */
- static __INLINE void arm_park_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pId,
- float32_t * pIq,
- float32_t sinVal,
- float32_t cosVal)
- {
- /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
- *pId = Ialpha * cosVal + Ibeta * sinVal;
-
- /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
- *pIq = -Ialpha * sinVal + Ibeta * cosVal;
- }
-
-
- /**
- * @brief Park transform for Q31 version
- * @param[in] Ialpha input two-phase vector coordinate alpha
- * @param[in] Ibeta input two-phase vector coordinate beta
- * @param[out] pId points to output rotor reference frame d
- * @param[out] pIq points to output rotor reference frame q
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition and subtraction, hence there is no risk of overflow.
- */
- static __INLINE void arm_park_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pId,
- q31_t * pIq,
- q31_t sinVal,
- q31_t cosVal)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
- q31_t product3, product4; /* Temporary variables used to store intermediate results */
-
- /* Intermediate product is calculated by (Ialpha * cosVal) */
- product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
- /* Intermediate product is calculated by (Ibeta * sinVal) */
- product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
- /* Intermediate product is calculated by (Ialpha * sinVal) */
- product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
- /* Intermediate product is calculated by (Ibeta * cosVal) */
- product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
- /* Calculate pId by adding the two intermediate products 1 and 2 */
- *pId = __QADD(product1, product2);
-
- /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
- *pIq = __QSUB(product4, product3);
- }
-
- /**
- * @} end of park group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q7_to_float(
- q7_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup inv_park Vector Inverse Park transform
- * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkInvFormula.gif
- * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
- * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup inv_park
- * @{
- */
-
- /**
- * @brief Floating-point Inverse Park transform
- * @param[in] Id input coordinate of rotor reference frame d
- * @param[in] Iq input coordinate of rotor reference frame q
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- */
- static __INLINE void arm_inv_park_f32(
- float32_t Id,
- float32_t Iq,
- float32_t * pIalpha,
- float32_t * pIbeta,
- float32_t sinVal,
- float32_t cosVal)
- {
- /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
- *pIalpha = Id * cosVal - Iq * sinVal;
-
- /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
- *pIbeta = Id * sinVal + Iq * cosVal;
- }
-
-
- /**
- * @brief Inverse Park transform for Q31 version
- * @param[in] Id input coordinate of rotor reference frame d
- * @param[in] Iq input coordinate of rotor reference frame q
- * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
- static __INLINE void arm_inv_park_q31(
- q31_t Id,
- q31_t Iq,
- q31_t * pIalpha,
- q31_t * pIbeta,
- q31_t sinVal,
- q31_t cosVal)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
- q31_t product3, product4; /* Temporary variables used to store intermediate results */
-
- /* Intermediate product is calculated by (Id * cosVal) */
- product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
- /* Intermediate product is calculated by (Iq * sinVal) */
- product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
- /* Intermediate product is calculated by (Id * sinVal) */
- product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
- /* Intermediate product is calculated by (Iq * cosVal) */
- product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
- /* Calculate pIalpha by using the two intermediate products 1 and 2 */
- *pIalpha = __QSUB(product1, product2);
-
- /* Calculate pIbeta by using the two intermediate products 3 and 4 */
- *pIbeta = __QADD(product4, product3);
- }
-
- /**
- * @} end of Inverse park group
- */
-
-
- /**
- * @brief Converts the elements of the Q31 vector to floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q31_to_float(
- q31_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @ingroup groupInterpolation
- */
-
- /**
- * @defgroup LinearInterpolate Linear Interpolation
- *
- * Linear interpolation is a method of curve fitting using linear polynomials.
- * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
- *
- * \par
- * \image html LinearInterp.gif "Linear interpolation"
- *
- * \par
- * A Linear Interpolate function calculates an output value(y), for the input(x)
- * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
- *
- * \par Algorithm:
- * <pre>
- * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
- * where x0, x1 are nearest values of input x
- * y0, y1 are nearest values to output y
- * </pre>
- *
- * \par
- * This set of functions implements Linear interpolation process
- * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
- * sample of data and each call to the function returns a single processed value.
- * <code>S</code> points to an instance of the Linear Interpolate function data structure.
- * <code>x</code> is the input sample value. The functions returns the output value.
- *
- * \par
- * if x is outside of the table boundary, Linear interpolation returns first value of the table
- * if x is below input range and returns last value of table if x is above range.
- */
-
- /**
- * @addtogroup LinearInterpolate
- * @{
- */
-
- /**
- * @brief Process function for the floating-point Linear Interpolation Function.
- * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
- * @param[in] x input sample to process
- * @return y processed output sample.
- *
- */
- static __INLINE float32_t arm_linear_interp_f32(
- arm_linear_interp_instance_f32 * S,
- float32_t x)
- {
- float32_t y;
- float32_t x0, x1; /* Nearest input values */
- float32_t y0, y1; /* Nearest output values */
- float32_t xSpacing = S->xSpacing; /* spacing between input values */
- int32_t i; /* Index variable */
- float32_t *pYData = S->pYData; /* pointer to output table */
-
- /* Calculation of index */
- i = (int32_t) ((x - S->x1) / xSpacing);
-
- if(i < 0)
- {
- /* Iniatilize output for below specified range as least output value of table */
- y = pYData[0];
- }
- else if((uint32_t)i >= S->nValues)
- {
- /* Iniatilize output for above specified range as last output value of table */
- y = pYData[S->nValues - 1];
- }
- else
- {
- /* Calculation of nearest input values */
- x0 = S->x1 + i * xSpacing;
- x1 = S->x1 + (i + 1) * xSpacing;
-
- /* Read of nearest output values */
- y0 = pYData[i];
- y1 = pYData[i + 1];
-
- /* Calculation of output */
- y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
- }
-
- /* returns output value */
- return (y);
- }
-
-
- /**
- *
- * @brief Process function for the Q31 Linear Interpolation Function.
- * @param[in] pYData pointer to Q31 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
- static __INLINE q31_t arm_linear_interp_q31(
- q31_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q31_t y; /* output */
- q31_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & (q31_t)0xFFF00000) >> 20);
-
- if(index >= (int32_t)(nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else if(index < 0)
- {
- return (pYData[0]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* shift left by 11 to keep fract in 1.31 format */
- fract = (x & 0x000FFFFF) << 11;
-
- /* Read two nearest output values from the index in 1.31(q31) format */
- y0 = pYData[index];
- y1 = pYData[index + 1];
-
- /* Calculation of y0 * (1-fract) and y is in 2.30 format */
- y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
- /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
- y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
- /* Convert y to 1.31 format */
- return (y << 1u);
- }
- }
-
-
- /**
- *
- * @brief Process function for the Q15 Linear Interpolation Function.
- * @param[in] pYData pointer to Q15 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
- static __INLINE q15_t arm_linear_interp_q15(
- q15_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q63_t y; /* output */
- q15_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & (int32_t)0xFFF00000) >> 20);
-
- if(index >= (int32_t)(nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else if(index < 0)
- {
- return (pYData[0]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y0 = pYData[index];
- y1 = pYData[index + 1];
-
- /* Calculation of y0 * (1-fract) and y is in 13.35 format */
- y = ((q63_t) y0 * (0xFFFFF - fract));
-
- /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
- y += ((q63_t) y1 * (fract));
-
- /* convert y to 1.15 format */
- return (q15_t) (y >> 20);
- }
- }
-
-
- /**
- *
- * @brief Process function for the Q7 Linear Interpolation Function.
- * @param[in] pYData pointer to Q7 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- */
- static __INLINE q7_t arm_linear_interp_q7(
- q7_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q31_t y; /* output */
- q7_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- uint32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- if (x < 0)
- {
- return (pYData[0]);
- }
- index = (x >> 20) & 0xfff;
-
- if(index >= (nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index and are in 1.7(q7) format */
- y0 = pYData[index];
- y1 = pYData[index + 1];
-
- /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
- y = ((y0 * (0xFFFFF - fract)));
-
- /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
- y += (y1 * fract);
-
- /* convert y to 1.7(q7) format */
- return (q7_t) (y >> 20);
- }
- }
-
- /**
- * @} end of LinearInterpolate group
- */
-
- /**
- * @brief Fast approximation to the trigonometric sine function for floating-point data.
- * @param[in] x input value in radians.
- * @return sin(x).
- */
- float32_t arm_sin_f32(
- float32_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric sine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- */
- q31_t arm_sin_q31(
- q31_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric sine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- */
- q15_t arm_sin_q15(
- q15_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for floating-point data.
- * @param[in] x input value in radians.
- * @return cos(x).
- */
- float32_t arm_cos_f32(
- float32_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- */
- q31_t arm_cos_q31(
- q31_t x);
-
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- */
- q15_t arm_cos_q15(
- q15_t x);
-
-
- /**
- * @ingroup groupFastMath
- */
-
-
- /**
- * @defgroup SQRT Square Root
- *
- * Computes the square root of a number.
- * There are separate functions for Q15, Q31, and floating-point data types.
- * The square root function is computed using the Newton-Raphson algorithm.
- * This is an iterative algorithm of the form:
- * <pre>
- * x1 = x0 - f(x0)/f'(x0)
- * </pre>
- * where <code>x1</code> is the current estimate,
- * <code>x0</code> is the previous estimate, and
- * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
- * For the square root function, the algorithm reduces to:
- * <pre>
- * x0 = in/2 [initial guess]
- * x1 = 1/2 * ( x0 + in / x0) [each iteration]
- * </pre>
- */
-
-
- /**
- * @addtogroup SQRT
- * @{
- */
-
- /**
- * @brief Floating-point square root function.
- * @param[in] in input value.
- * @param[out] pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
- static __INLINE arm_status arm_sqrt_f32(
- float32_t in,
- float32_t * pOut)
- {
- if(in >= 0.0f)
- {
-
-#if (__FPU_USED == 1) && defined ( __CC_ARM )
- *pOut = __sqrtf(in);
-#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
- *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined(__GNUC__)
- *pOut = __builtin_sqrtf(in);
-#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
- __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
-#else
- *pOut = sqrtf(in);
-#endif
-
- return (ARM_MATH_SUCCESS);
- }
- else
- {
- *pOut = 0.0f;
- return (ARM_MATH_ARGUMENT_ERROR);
- }
- }
-
-
- /**
- * @brief Q31 square root function.
- * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
- * @param[out] pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
- arm_status arm_sqrt_q31(
- q31_t in,
- q31_t * pOut);
-
-
- /**
- * @brief Q15 square root function.
- * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
- * @param[out] pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
- arm_status arm_sqrt_q15(
- q15_t in,
- q15_t * pOut);
-
- /**
- * @} end of SQRT group
- */
-
-
- /**
- * @brief floating-point Circular write function.
- */
- static __INLINE void arm_circularWrite_f32(
- int32_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const int32_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = (uint16_t)wOffset;
- }
-
-
-
- /**
- * @brief floating-point Circular Read function.
- */
- static __INLINE void arm_circularRead_f32(
- int32_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- int32_t * dst,
- int32_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if(dst == (int32_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if(rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Q15 Circular write function.
- */
- static __INLINE void arm_circularWrite_q15(
- q15_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q15_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = (uint16_t)wOffset;
- }
-
-
- /**
- * @brief Q15 Circular Read function.
- */
- static __INLINE void arm_circularRead_q15(
- q15_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q15_t * dst,
- q15_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
-
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if(dst == (q15_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if(rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Q7 Circular write function.
- */
- static __INLINE void arm_circularWrite_q7(
- q7_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q7_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = (uint16_t)wOffset;
- }
-
-
- /**
- * @brief Q7 Circular Read function.
- */
- static __INLINE void arm_circularRead_q7(
- q7_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q7_t * dst,
- q7_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
-
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if(dst == (q7_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if(rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Sum of the squares of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
-
- /**
- * @brief Sum of the squares of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Sum of the squares of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
-
- /**
- * @brief Sum of the squares of the elements of a Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_power_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Mean value of a Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult);
-
-
- /**
- * @brief Mean value of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Mean value of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Mean value of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_mean_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Variance of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_var_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Variance of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_var_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Variance of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_var_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Root Mean Square of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_rms_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Root Mean Square of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_rms_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Root Mean Square of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_rms_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Standard deviation of the elements of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_std_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
-
- /**
- * @brief Standard deviation of the elements of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_std_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
-
- /**
- * @brief Standard deviation of the elements of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output value.
- */
- void arm_std_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
-
- /**
- * @brief Floating-point complex magnitude
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex magnitude
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex magnitude
- * @param[in] pSrc points to the complex input vector
- * @param[out] pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- */
- void arm_cmplx_mag_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q15 complex dot product
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] realResult real part of the result returned here
- * @param[out] imagResult imaginary part of the result returned here
- */
- void arm_cmplx_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t numSamples,
- q31_t * realResult,
- q31_t * imagResult);
-
-
- /**
- * @brief Q31 complex dot product
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] realResult real part of the result returned here
- * @param[out] imagResult imaginary part of the result returned here
- */
- void arm_cmplx_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t numSamples,
- q63_t * realResult,
- q63_t * imagResult);
-
-
- /**
- * @brief Floating-point complex dot product
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] realResult real part of the result returned here
- * @param[out] imagResult imaginary part of the result returned here
- */
- void arm_cmplx_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t numSamples,
- float32_t * realResult,
- float32_t * imagResult);
-
-
- /**
- * @brief Q15 complex-by-real multiplication
- * @param[in] pSrcCmplx points to the complex input vector
- * @param[in] pSrcReal points to the real input vector
- * @param[out] pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- */
- void arm_cmplx_mult_real_q15(
- q15_t * pSrcCmplx,
- q15_t * pSrcReal,
- q15_t * pCmplxDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex-by-real multiplication
- * @param[in] pSrcCmplx points to the complex input vector
- * @param[in] pSrcReal points to the real input vector
- * @param[out] pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- */
- void arm_cmplx_mult_real_q31(
- q31_t * pSrcCmplx,
- q31_t * pSrcReal,
- q31_t * pCmplxDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Floating-point complex-by-real multiplication
- * @param[in] pSrcCmplx points to the complex input vector
- * @param[in] pSrcReal points to the real input vector
- * @param[out] pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- */
- void arm_cmplx_mult_real_f32(
- float32_t * pSrcCmplx,
- float32_t * pSrcReal,
- float32_t * pCmplxDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Minimum value of a Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] result is output pointer
- * @param[in] index is the array index of the minimum value in the input buffer.
- */
- void arm_min_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * result,
- uint32_t * index);
-
-
- /**
- * @brief Minimum value of a Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output pointer
- * @param[in] pIndex is the array index of the minimum value in the input buffer.
- */
- void arm_min_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
-
-
- /**
- * @brief Minimum value of a Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output pointer
- * @param[out] pIndex is the array index of the minimum value in the input buffer.
- */
- void arm_min_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
-
-
- /**
- * @brief Minimum value of a floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] pResult is output pointer
- * @param[out] pIndex is the array index of the minimum value in the input buffer.
- */
- void arm_min_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
-
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in] pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] pResult maximum value returned here
- * @param[out] pIndex index of maximum value returned here
- */
- void arm_max_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
-
-
- /**
- * @brief Q15 complex-by-complex multiplication
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_mult_cmplx_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Q31 complex-by-complex multiplication
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_mult_cmplx_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Floating-point complex-by-complex multiplication
- * @param[in] pSrcA points to the first input vector
- * @param[in] pSrcB points to the second input vector
- * @param[out] pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- */
- void arm_cmplx_mult_cmplx_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @brief Converts the elements of the floating-point vector to Q31 vector.
- * @param[in] pSrc points to the floating-point input vector
- * @param[out] pDst points to the Q31 output vector
- * @param[in] blockSize length of the input vector
- */
- void arm_float_to_q31(
- float32_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the floating-point vector to Q15 vector.
- * @param[in] pSrc points to the floating-point input vector
- * @param[out] pDst points to the Q15 output vector
- * @param[in] blockSize length of the input vector
- */
- void arm_float_to_q15(
- float32_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the floating-point vector to Q7 vector.
- * @param[in] pSrc points to the floating-point input vector
- * @param[out] pDst points to the Q7 output vector
- * @param[in] blockSize length of the input vector
- */
- void arm_float_to_q7(
- float32_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q31 vector to Q15 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q31_to_q15(
- q31_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q31 vector to Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q31_to_q7(
- q31_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to floating-point vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q15_to_float(
- q15_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to Q31 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q15_to_q31(
- q15_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to Q7 vector.
- * @param[in] pSrc is input pointer
- * @param[out] pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- */
- void arm_q15_to_q7(
- q15_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @ingroup groupInterpolation
- */
-
- /**
- * @defgroup BilinearInterpolate Bilinear Interpolation
- *
- * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
- * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
- * determines values between the grid points.
- * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
- * Bilinear interpolation is often used in image processing to rescale images.
- * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
- *
- * <b>Algorithm</b>
- * \par
- * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
- * For floating-point, the instance structure is defined as:
- * <pre>
- * typedef struct
- * {
- * uint16_t numRows;
- * uint16_t numCols;
- * float32_t *pData;
- * } arm_bilinear_interp_instance_f32;
- * </pre>
- *
- * \par
- * where <code>numRows</code> specifies the number of rows in the table;
- * <code>numCols</code> specifies the number of columns in the table;
- * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
- * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
- * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
- *
- * \par
- * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
- * <pre>
- * XF = floor(x)
- * YF = floor(y)
- * </pre>
- * \par
- * The interpolated output point is computed as:
- * <pre>
- * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
- * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
- * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
- * + f(XF+1, YF+1) * (x-XF)*(y-YF)
- * </pre>
- * Note that the coordinates (x, y) contain integer and fractional components.
- * The integer components specify which portion of the table to use while the
- * fractional components control the interpolation processor.
- *
- * \par
- * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
- */
-
- /**
- * @addtogroup BilinearInterpolate
- * @{
- */
-
-
- /**
- *
- * @brief Floating-point bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate.
- * @param[in] Y interpolation coordinate.
- * @return out interpolated value.
- */
- static __INLINE float32_t arm_bilinear_interp_f32(
- const arm_bilinear_interp_instance_f32 * S,
- float32_t X,
- float32_t Y)
- {
- float32_t out;
- float32_t f00, f01, f10, f11;
- float32_t *pData = S->pData;
- int32_t xIndex, yIndex, index;
- float32_t xdiff, ydiff;
- float32_t b1, b2, b3, b4;
-
- xIndex = (int32_t) X;
- yIndex = (int32_t) Y;
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))
- {
- return (0);
- }
-
- /* Calculation of index for two nearest points in X-direction */
- index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
- /* Read two nearest points in X-direction */
- f00 = pData[index];
- f01 = pData[index + 1];
-
- /* Calculation of index for two nearest points in Y-direction */
- index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
- /* Read two nearest points in Y-direction */
- f10 = pData[index];
- f11 = pData[index + 1];
-
- /* Calculation of intermediate values */
- b1 = f00;
- b2 = f01 - f00;
- b3 = f10 - f00;
- b4 = f00 - f01 - f10 + f11;
-
- /* Calculation of fractional part in X */
- xdiff = X - xIndex;
-
- /* Calculation of fractional part in Y */
- ydiff = Y - yIndex;
-
- /* Calculation of bi-linear interpolated output */
- out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
- /* return to application */
- return (out);
- }
-
-
- /**
- *
- * @brief Q31 bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
- static __INLINE q31_t arm_bilinear_interp_q31(
- arm_bilinear_interp_instance_q31 * S,
- q31_t X,
- q31_t Y)
- {
- q31_t out; /* Temporary output */
- q31_t acc = 0; /* output */
- q31_t xfract, yfract; /* X, Y fractional parts */
- q31_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
- q31_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & (q31_t)0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* shift left xfract by 11 to keep 1.31 format */
- xfract = (X & 0x000FFFFF) << 11u;
-
- /* Read two nearest output values from the index */
- x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
- x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
-
- /* 20 bits for the fractional part */
- /* shift left yfract by 11 to keep 1.31 format */
- yfract = (Y & 0x000FFFFF) << 11u;
-
- /* Read two nearest output values from the index */
- y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
- y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
- out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
- acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
- /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
- /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
- /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
- /* Convert acc to 1.31(q31) format */
- return ((q31_t)(acc << 2));
- }
-
-
- /**
- * @brief Q15 bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
- static __INLINE q15_t arm_bilinear_interp_q15(
- arm_bilinear_interp_instance_q15 * S,
- q31_t X,
- q31_t Y)
- {
- q63_t acc = 0; /* output */
- q31_t out; /* Temporary output */
- q15_t x1, x2, y1, y2; /* Nearest output values */
- q31_t xfract, yfract; /* X, Y fractional parts */
- int32_t rI, cI; /* Row and column indices */
- q15_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & (q31_t)0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* xfract should be in 12.20 format */
- xfract = (X & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
- x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
- /* 20 bits for the fractional part */
- /* yfract should be in 12.20 format */
- yfract = (Y & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
- y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
- /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
- /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
- out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
- acc = ((q63_t) out * (0xFFFFF - yfract));
-
- /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
- acc += ((q63_t) out * (xfract));
-
- /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
- acc += ((q63_t) out * (yfract));
-
- /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
- acc += ((q63_t) out * (yfract));
-
- /* acc is in 13.51 format and down shift acc by 36 times */
- /* Convert out to 1.15 format */
- return ((q15_t)(acc >> 36));
- }
-
-
- /**
- * @brief Q7 bilinear interpolation.
- * @param[in,out] S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
- static __INLINE q7_t arm_bilinear_interp_q7(
- arm_bilinear_interp_instance_q7 * S,
- q31_t X,
- q31_t Y)
- {
- q63_t acc = 0; /* output */
- q31_t out; /* Temporary output */
- q31_t xfract, yfract; /* X, Y fractional parts */
- q7_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
- q7_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & (q31_t)0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & (q31_t)0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* xfract should be in 12.20 format */
- xfract = (X & (q31_t)0x000FFFFF);
-
- /* Read two nearest output values from the index */
- x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
- x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
-
- /* 20 bits for the fractional part */
- /* yfract should be in 12.20 format */
- yfract = (Y & (q31_t)0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
- y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
- out = ((x1 * (0xFFFFF - xfract)));
- acc = (((q63_t) out * (0xFFFFF - yfract)));
-
- /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
- out = ((x2 * (0xFFFFF - yfract)));
- acc += (((q63_t) out * (xfract)));
-
- /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
- out = ((y1 * (0xFFFFF - xfract)));
- acc += (((q63_t) out * (yfract)));
-
- /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
- out = ((y2 * (yfract)));
- acc += (((q63_t) out * (xfract)));
-
- /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
- return ((q7_t)(acc >> 40));
- }
-
- /**
- * @} end of BilinearInterpolate group
- */
-
-
-/* SMMLAR */
-#define multAcc_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMLSR */
-#define multSub_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-/* SMMULR */
-#define mult_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-/* SMMLA */
-#define multAcc_32x32_keep32(a, x, y) \
- a += (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMLS */
-#define multSub_32x32_keep32(a, x, y) \
- a -= (q31_t) (((q63_t) x * y) >> 32)
-
-/* SMMUL */
-#define mult_32x32_keep32(a, x, y) \
- a = (q31_t) (((q63_t) x * y ) >> 32)
-
-
-#if defined ( __CC_ARM )
- /* Enter low optimization region - place directly above function definition */
- #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
- #define LOW_OPTIMIZATION_ENTER \
- _Pragma ("push") \
- _Pragma ("O1")
- #else
- #define LOW_OPTIMIZATION_ENTER
- #endif
-
- /* Exit low optimization region - place directly after end of function definition */
- #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
- #define LOW_OPTIMIZATION_EXIT \
- _Pragma ("pop")
- #else
- #define LOW_OPTIMIZATION_EXIT
- #endif
-
- /* Enter low optimization region - place directly above function definition */
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
- /* Exit low optimization region - place directly after end of function definition */
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__GNUC__)
- #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__ICCARM__)
- /* Enter low optimization region - place directly above function definition */
- #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
- #define LOW_OPTIMIZATION_ENTER \
- _Pragma ("optimize=low")
- #else
- #define LOW_OPTIMIZATION_ENTER
- #endif
-
- /* Exit low optimization region - place directly after end of function definition */
- #define LOW_OPTIMIZATION_EXIT
-
- /* Enter low optimization region - place directly above function definition */
- #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
- _Pragma ("optimize=low")
- #else
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #endif
-
- /* Exit low optimization region - place directly after end of function definition */
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__CSMC__)
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__TASKING__)
- #define LOW_OPTIMIZATION_ENTER
- #define LOW_OPTIMIZATION_EXIT
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-#endif
-
-#endif /* _ARM_MATH_H */
-
-/**
- *
- * End of file.
- */
diff --git a/Drivers/CMSIS/Include/cmsis_armcc.h b/Drivers/CMSIS/Include/cmsis_armcc.h
deleted file mode 100644
index 74c49c67defb6382f28a359d5678c5996add541c..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/cmsis_armcc.h
+++ /dev/null
@@ -1,734 +0,0 @@
-/**************************************************************************//**
- * @file cmsis_armcc.h
- * @brief CMSIS Cortex-M Core Function/Instruction Header File
- * @version V4.30
- * @date 20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CMSIS_ARMCC_H
-#define __CMSIS_ARMCC_H
-
-
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
- register uint32_t __regIPSR __ASM("ipsr");
- return(__regIPSR);
-}
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
- \return xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
- register uint32_t __regXPSR __ASM("xpsr");
- return(__regXPSR);
-}
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- return(__regProcessStackPointer);
-}
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- __regProcessStackPointer = topOfProcStack;
-}
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- return(__regMainStackPointer);
-}
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- __regMainStackPointer = topOfMainStack;
-}
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
-
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xFFU);
-}
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
- register uint32_t __regBasePriMax __ASM("basepri_max");
- __regBasePriMax = (basePri & 0xFFU);
-}
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
-
-
-#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
-
-/**
- \brief Get FPSCR
- \details Returns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0U);
-#endif
-}
-
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-/**
- \brief No Operation
- \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __nop
-
-
-/**
- \brief Wait For Interrupt
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI __wfi
-
-
-/**
- \brief Wait For Event
- \details Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __wfe
-
-
-/**
- \brief Send Event
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __sev
-
-
-/**
- \brief Instruction Synchronization Barrier
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or memory,
- after the instruction has been completed.
- */
-#define __ISB() do {\
- __schedule_barrier();\
- __isb(0xF);\
- __schedule_barrier();\
- } while (0U)
-
-/**
- \brief Data Synchronization Barrier
- \details Acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
- __schedule_barrier();\
- __dsb(0xF);\
- __schedule_barrier();\
- } while (0U)
-
-/**
- \brief Data Memory Barrier
- \details Ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
- __schedule_barrier();\
- __dmb(0xF);\
- __schedule_barrier();\
- } while (0U)
-
-/**
- \brief Reverse byte order (32 bit)
- \details Reverses the byte order in integer value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV __rev
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order in two unsigned short values.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
- rev16 r0, r0
- bx lr
-}
-#endif
-
-/**
- \brief Reverse byte order in signed short value
- \details Reverses the byte order in a signed short value with sign extension to integer.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
- revsh r0, r0
- bx lr
-}
-#endif
-
-
-/**
- \brief Rotate Right in unsigned value (32 bit)
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-#define __ROR __ror
-
-
-/**
- \brief Breakpoint
- \details Causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __breakpoint(value)
-
-
-/**
- \brief Reverse bit order of value
- \details Reverses the bit order of the given value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
- #define __RBIT __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
- int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
-
- result = value; /* r will be reversed bits of v; first get LSB of v */
- for (value >>= 1U; value; value >>= 1U)
- {
- result <<= 1U;
- result |= value & 1U;
- s--;
- }
- result <<= s; /* shift when v's highest bits are zero */
- return(result);
-}
-#endif
-
-
-/**
- \brief Count leading zeros
- \details Counts the number of leading zeros of a data value.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __clz
-
-
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
-
-/**
- \brief LDR Exclusive (8 bit)
- \details Executes a exclusive LDR instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
-#else
- #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
-#endif
-
-
-/**
- \brief LDR Exclusive (16 bit)
- \details Executes a exclusive LDR instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
-#else
- #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
-#endif
-
-
-/**
- \brief LDR Exclusive (32 bit)
- \details Executes a exclusive LDR instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
-#else
- #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
-#endif
-
-
-/**
- \brief STR Exclusive (8 bit)
- \details Executes a exclusive STR instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __STREXB(value, ptr) __strex(value, ptr)
-#else
- #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
-#endif
-
-
-/**
- \brief STR Exclusive (16 bit)
- \details Executes a exclusive STR instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __STREXH(value, ptr) __strex(value, ptr)
-#else
- #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
-#endif
-
-
-/**
- \brief STR Exclusive (32 bit)
- \details Executes a exclusive STR instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
- #define __STREXW(value, ptr) __strex(value, ptr)
-#else
- #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
-#endif
-
-
-/**
- \brief Remove the exclusive lock
- \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX __clrex
-
-
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT __ssat
-
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT __usat
-
-
-/**
- \brief Rotate Right with Extend (32 bit)
- \details Moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to rotate
- \return Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
- rrx r0, r0
- bx lr
-}
-#endif
-
-
-/**
- \brief LDRT Unprivileged (8 bit)
- \details Executes a Unprivileged LDRT instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
-
-
-/**
- \brief LDRT Unprivileged (16 bit)
- \details Executes a Unprivileged LDRT instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
-
-
-/**
- \brief LDRT Unprivileged (32 bit)
- \details Executes a Unprivileged LDRT instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
-
-
-/**
- \brief STRT Unprivileged (8 bit)
- \details Executes a Unprivileged STRT instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRBT(value, ptr) __strt(value, ptr)
-
-
-/**
- \brief STRT Unprivileged (16 bit)
- \details Executes a Unprivileged STRT instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRHT(value, ptr) __strt(value, ptr)
-
-
-/**
- \brief STRT Unprivileged (32 bit)
- \details Executes a Unprivileged STRT instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-#define __STRT(value, ptr) __strt(value, ptr)
-
-#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
-
-#define __SADD8 __sadd8
-#define __QADD8 __qadd8
-#define __SHADD8 __shadd8
-#define __UADD8 __uadd8
-#define __UQADD8 __uqadd8
-#define __UHADD8 __uhadd8
-#define __SSUB8 __ssub8
-#define __QSUB8 __qsub8
-#define __SHSUB8 __shsub8
-#define __USUB8 __usub8
-#define __UQSUB8 __uqsub8
-#define __UHSUB8 __uhsub8
-#define __SADD16 __sadd16
-#define __QADD16 __qadd16
-#define __SHADD16 __shadd16
-#define __UADD16 __uadd16
-#define __UQADD16 __uqadd16
-#define __UHADD16 __uhadd16
-#define __SSUB16 __ssub16
-#define __QSUB16 __qsub16
-#define __SHSUB16 __shsub16
-#define __USUB16 __usub16
-#define __UQSUB16 __uqsub16
-#define __UHSUB16 __uhsub16
-#define __SASX __sasx
-#define __QASX __qasx
-#define __SHASX __shasx
-#define __UASX __uasx
-#define __UQASX __uqasx
-#define __UHASX __uhasx
-#define __SSAX __ssax
-#define __QSAX __qsax
-#define __SHSAX __shsax
-#define __USAX __usax
-#define __UQSAX __uqsax
-#define __UHSAX __uhsax
-#define __USAD8 __usad8
-#define __USADA8 __usada8
-#define __SSAT16 __ssat16
-#define __USAT16 __usat16
-#define __UXTB16 __uxtb16
-#define __UXTAB16 __uxtab16
-#define __SXTB16 __sxtb16
-#define __SXTAB16 __sxtab16
-#define __SMUAD __smuad
-#define __SMUADX __smuadx
-#define __SMLAD __smlad
-#define __SMLADX __smladx
-#define __SMLALD __smlald
-#define __SMLALDX __smlaldx
-#define __SMUSD __smusd
-#define __SMUSDX __smusdx
-#define __SMLSD __smlsd
-#define __SMLSDX __smlsdx
-#define __SMLSLD __smlsld
-#define __SMLSLDX __smlsldx
-#define __SEL __sel
-#define __QADD __qadd
-#define __QSUB __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
- ((int64_t)(ARG3) << 32U) ) >> 32U))
-
-#endif /* (__CORTEX_M >= 0x04) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCC_H */
diff --git a/Drivers/CMSIS/Include/cmsis_armcc_V6.h b/Drivers/CMSIS/Include/cmsis_armcc_V6.h
deleted file mode 100644
index cd13240ce360250f496f1fd8c04df7ee23c0a8c9..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/cmsis_armcc_V6.h
+++ /dev/null
@@ -1,1800 +0,0 @@
-/**************************************************************************//**
- * @file cmsis_armcc_V6.h
- * @brief CMSIS Cortex-M Core Function/Instruction Header File
- * @version V4.30
- * @date 20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CMSIS_ARMCC_V6_H
-#define __CMSIS_ARMCC_V6_H
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-/**
- \brief Enable IRQ Interrupts
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/**
- \brief Disable IRQ Interrupts
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Control Register (non-secure)
- \details Returns the content of the non-secure Control Register when in secure mode.
- \return non-secure Control Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Set Control Register (non-secure)
- \details Writes the given value to the non-secure Control Register when in secure state.
- \param [in] control Control Register value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
- __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get IPSR Register (non-secure)
- \details Returns the content of the non-secure IPSR Register when in secure state.
- \return IPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get APSR Register (non-secure)
- \details Returns the content of the non-secure APSR Register when in secure state.
- \return APSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
- \return xPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get xPSR Register (non-secure)
- \details Returns the content of the non-secure xPSR Register when in secure state.
- \return xPSR Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp" : "=r" (result) );
- return(result);
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Process Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
- \return PSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp");
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp");
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp" : "=r" (result) );
- return(result);
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Main Stack Pointer (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
- \return MSP Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp");
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Set Main Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp");
-}
-#endif
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Priority Mask (non-secure)
- \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
- \return Priority Mask value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Set Priority Mask (non-secure)
- \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
- \param [in] priMask Priority Mask
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
- __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
-
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );
- return(result);
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Base Priority (non-secure)
- \details Returns the current value of the non-secure Base Priority register when in secure state.
- \return Base Priority register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Set Base Priority (non-secure)
- \details Assigns the given value to the non-secure Base Priority register when in secure state.
- \param [in] basePri Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t value)
-{
- __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory");
-}
-#endif
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
-{
- __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Set Base Priority with condition (non_secure)
- \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(uint32_t value)
-{
- __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory");
-}
-#endif
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get Fault Mask (non-secure)
- \details Returns the current value of the non-secure Fault Mask register when in secure state.
- \return Fault Mask register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Set Fault Mask (non-secure)
- \details Assigns the given value to the non-secure Fault Mask register when in secure state.
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-
-#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
-
-
-#if (__ARM_ARCH_8M__ == 1U)
-
-/**
- \brief Get Process Stack Pointer Limit
- \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
- \return PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psplim" : "=r" (result) );
- return(result);
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
-/**
- \brief Get Process Stack Pointer Limit (non-secure)
- \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \return PSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Process Stack Pointer Limit
- \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
- __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
-/**
- \brief Set Process Stack Pointer (non-secure)
- \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
- \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
- __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-}
-#endif
-
-
-/**
- \brief Get Main Stack Pointer Limit
- \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
- \return MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-
- return(result);
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
-/**
- \brief Get Main Stack Pointer Limit (non-secure)
- \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
- \return MSPLIM Register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Set Main Stack Pointer Limit
- \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
- \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
- __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-}
-
-
-#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
-/**
- \brief Set Main Stack Pointer Limit (non-secure)
- \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
- \param [in] MainStackPtrLimit Main Stack Pointer value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
- __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-}
-#endif
-
-#endif /* (__ARM_ARCH_8M__ == 1U) */
-
-
-#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */
-
-/**
- \brief Get FPSCR
- \details eturns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-#define __get_FPSCR __builtin_arm_get_fpscr
-#if 0
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
- uint32_t result;
-
- __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- __ASM volatile ("");
- return(result);
-#else
- return(0);
-#endif
-}
-#endif
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Get FPSCR (non-secure)
- \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.
- \return Floating Point Status/Control register value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void)
-{
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
- uint32_t result;
-
- __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) );
- __ASM volatile ("");
- return(result);
-#else
- return(0);
-#endif
-}
-#endif
-
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-#define __set_FPSCR __builtin_arm_set_fpscr
-#if 0
-__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
- __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
- __ASM volatile ("");
-#endif
-}
-#endif
-
-#if (__ARM_FEATURE_CMSE == 3U)
-/**
- \brief Set FPSCR (non-secure)
- \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
- __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc");
- __ASM volatile ("");
-#endif
-}
-#endif
-
-#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
- \brief No Operation
- \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __builtin_arm_nop
-
-/**
- \brief Wait For Interrupt
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI __builtin_arm_wfi
-
-
-/**
- \brief Wait For Event
- \details Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __builtin_arm_wfe
-
-
-/**
- \brief Send Event
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __builtin_arm_sev
-
-
-/**
- \brief Instruction Synchronization Barrier
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or memory,
- after the instruction has been completed.
- */
-#define __ISB() __builtin_arm_isb(0xF);
-
-/**
- \brief Data Synchronization Barrier
- \details Acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() __builtin_arm_dsb(0xF);
-
-
-/**
- \brief Data Memory Barrier
- \details Ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() __builtin_arm_dmb(0xF);
-
-
-/**
- \brief Reverse byte order (32 bit)
- \details Reverses the byte order in integer value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV __builtin_bswap32
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order in two unsigned short values.
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
-#if 0
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-#endif
-
-
-/**
- \brief Reverse byte order in signed short value
- \details Reverses the byte order in a signed short value with sign extension to integer.
- \param [in] value Value to reverse
- \return Reversed value
- */
- /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
- int32_t result;
-
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/**
- \brief Rotate Right in unsigned value (32 bit)
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
- \param [in] op1 Value to rotate
- \param [in] op2 Number of Bits to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
- \brief Breakpoint
- \details Causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-/**
- \brief Reverse bit order of value
- \details Reverses the bit order of the given value.
- \param [in] value Value to reverse
- \return Reversed value
- */
- /* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
-#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
- int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
-
- result = value; /* r will be reversed bits of v; first get LSB of v */
- for (value >>= 1U; value; value >>= 1U)
- {
- result <<= 1U;
- result |= value & 1U;
- s--;
- }
- result <<= s; /* shift when v's highest bits are zero */
-#endif
- return(result);
-}
-
-
-/**
- \brief Count leading zeros
- \details Counts the number of leading zeros of a data value.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __builtin_clz
-
-
-#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
-
-/**
- \brief LDR Exclusive (8 bit)
- \details Executes a exclusive LDR instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDREXB (uint8_t)__builtin_arm_ldrex
-
-
-/**
- \brief LDR Exclusive (16 bit)
- \details Executes a exclusive LDR instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDREXH (uint16_t)__builtin_arm_ldrex
-
-
-/**
- \brief LDR Exclusive (32 bit)
- \details Executes a exclusive LDR instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDREXW (uint32_t)__builtin_arm_ldrex
-
-
-/**
- \brief STR Exclusive (8 bit)
- \details Executes a exclusive STR instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXB (uint32_t)__builtin_arm_strex
-
-
-/**
- \brief STR Exclusive (16 bit)
- \details Executes a exclusive STR instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXH (uint32_t)__builtin_arm_strex
-
-
-/**
- \brief STR Exclusive (32 bit)
- \details Executes a exclusive STR instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXW (uint32_t)__builtin_arm_strex
-
-
-/**
- \brief Remove the exclusive lock
- \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX __builtin_arm_clrex
-
-
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-/*#define __SSAT __builtin_arm_ssat*/
-#define __SSAT(ARG1,ARG2) \
-({ \
- int32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT __builtin_arm_usat
-#if 0
-#define __USAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-#endif
-
-
-/**
- \brief Rotate Right with Extend (32 bit)
- \details Moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/**
- \brief LDRT Unprivileged (8 bit)
- \details Executes a Unprivileged LDRT instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (16 bit)
- \details Executes a Unprivileged LDRT instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (32 bit)
- \details Executes a Unprivileged LDRT instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief STRT Unprivileged (8 bit)
- \details Executes a Unprivileged STRT instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
- __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (16 bit)
- \details Executes a Unprivileged STRT instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
- __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (32 bit)
- \details Executes a Unprivileged STRT instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
- __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
-
-
-#if (__ARM_ARCH_8M__ == 1U)
-
-/**
- \brief Load-Acquire (8 bit)
- \details Executes a LDAB instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint8_t) result);
-}
-
-
-/**
- \brief Load-Acquire (16 bit)
- \details Executes a LDAH instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
- return ((uint16_t) result);
-}
-
-
-/**
- \brief Load-Acquire (32 bit)
- \details Executes a LDA instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
- uint32_t result;
-
- __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
- return(result);
-}
-
-
-/**
- \brief Store-Release (8 bit)
- \details Executes a STLB instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
- __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Store-Release (16 bit)
- \details Executes a STLH instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
- __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Store-Release (32 bit)
- \details Executes a STL instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
- __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief Load-Acquire Exclusive (8 bit)
- \details Executes a LDAB exclusive instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDAEXB (uint8_t)__builtin_arm_ldaex
-
-
-/**
- \brief Load-Acquire Exclusive (16 bit)
- \details Executes a LDAH exclusive instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDAEXH (uint16_t)__builtin_arm_ldaex
-
-
-/**
- \brief Load-Acquire Exclusive (32 bit)
- \details Executes a LDA exclusive instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDAEX (uint32_t)__builtin_arm_ldaex
-
-
-/**
- \brief Store-Release Exclusive (8 bit)
- \details Executes a STLB exclusive instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STLEXB (uint32_t)__builtin_arm_stlex
-
-
-/**
- \brief Store-Release Exclusive (16 bit)
- \details Executes a STLH exclusive instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STLEXH (uint32_t)__builtin_arm_stlex
-
-
-/**
- \brief Store-Release Exclusive (32 bit)
- \details Executes a STL exclusive instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STLEX (uint32_t)__builtin_arm_stlex
-
-#endif /* (__ARM_ARCH_8M__ == 1U) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- if (ARG3 == 0) \
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1U) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCC_V6_H */
diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Drivers/CMSIS/Include/cmsis_gcc.h
deleted file mode 100644
index bb89fbba9e40005859e15a8d584e998cbdb6ae59..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/cmsis_gcc.h
+++ /dev/null
@@ -1,1373 +0,0 @@
-/**************************************************************************//**
- * @file cmsis_gcc.h
- * @brief CMSIS Cortex-M Core Function/Instruction Header File
- * @version V4.30
- * @date 20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CMSIS_GCC_H
-#define __CMSIS_GCC_H
-
-/* ignore some GCC warnings */
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-#endif
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-/**
- \brief Enable IRQ Interrupts
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/**
- \brief Disable IRQ Interrupts
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
- \brief Get Control Register
- \details Returns the content of the Control Register.
- \return Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Set Control Register
- \details Writes the given value to the Control Register.
- \param [in] control Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-/**
- \brief Get IPSR Register
- \details Returns the content of the IPSR Register.
- \return IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get APSR Register
- \details Returns the content of the APSR Register.
- \return APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get xPSR Register
- \details Returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Get Process Stack Pointer
- \details Returns the current value of the Process Stack Pointer (PSP).
- \return PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Set Process Stack Pointer
- \details Assigns the given value to the Process Stack Pointer (PSP).
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
-}
-
-
-/**
- \brief Get Main Stack Pointer
- \details Returns the current value of the Main Stack Pointer (MSP).
- \return MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Set Main Stack Pointer
- \details Assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
-}
-
-
-/**
- \brief Get Priority Mask
- \details Returns the current state of the priority mask bit from the Priority Mask Register.
- \return Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Set Priority Mask
- \details Assigns the given value to the Priority Mask Register.
- \param [in] priMask Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (__CORTEX_M >= 0x03U)
-
-/**
- \brief Enable FIQ
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
- \brief Disable FIQ
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
- \brief Get Base Priority
- \details Returns the current value of the Base Priority register.
- \return Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Set Base Priority
- \details Assigns the given value to the Base Priority register.
- \param [in] basePri Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-/**
- \brief Set Base Priority with condition
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
- or the new value increases the BASEPRI priority level.
- \param [in] basePri Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
-{
- __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
-}
-
-
-/**
- \brief Get Fault Mask
- \details Returns the current value of the Fault Mask register.
- \return Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-/**
- \brief Set Fault Mask
- \details Assigns the given value to the Fault Mask register.
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-#endif /* (__CORTEX_M >= 0x03U) */
-
-
-#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
-
-/**
- \brief Get FPSCR
- \details Returns the current value of the Floating Point Status/Control register.
- \return Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
- uint32_t result;
-
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- __ASM volatile ("");
- return(result);
-#else
- return(0);
-#endif
-}
-
-
-/**
- \brief Set FPSCR
- \details Assigns the given value to the Floating Point Status/Control register.
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
- __ASM volatile ("");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
-
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
- \brief No Operation
- \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
-{
- __ASM volatile ("nop");
-}
-
-
-/**
- \brief Wait For Interrupt
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
-{
- __ASM volatile ("wfi");
-}
-
-
-/**
- \brief Wait For Event
- \details Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
-{
- __ASM volatile ("wfe");
-}
-
-
-/**
- \brief Send Event
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
-{
- __ASM volatile ("sev");
-}
-
-
-/**
- \brief Instruction Synchronization Barrier
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or memory,
- after the instruction has been completed.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
-{
- __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/**
- \brief Data Synchronization Barrier
- \details Acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
-{
- __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/**
- \brief Data Memory Barrier
- \details Ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
-{
- __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/**
- \brief Reverse byte order (32 bit)
- \details Reverses the byte order in integer value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
- return __builtin_bswap32(value);
-#else
- uint32_t result;
-
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/**
- \brief Reverse byte order (16 bit)
- \details Reverses the byte order in two unsigned short values.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/**
- \brief Reverse byte order in signed short value
- \details Reverses the byte order in a signed short value with sign extension to integer.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- return (short)__builtin_bswap16(value);
-#else
- int32_t result;
-
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/**
- \brief Rotate Right in unsigned value (32 bit)
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
- \brief Breakpoint
- \details Causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-/**
- \brief Reverse bit order of value
- \details Reverses the bit order of the given value.
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
- int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
-
- result = value; /* r will be reversed bits of v; first get LSB of v */
- for (value >>= 1U; value; value >>= 1U)
- {
- result <<= 1U;
- result |= value & 1U;
- s--;
- }
- result <<= s; /* shift when v's highest bits are zero */
-#endif
- return(result);
-}
-
-
-/**
- \brief Count leading zeros
- \details Counts the number of leading zeros of a data value.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __builtin_clz
-
-
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
-
-/**
- \brief LDR Exclusive (8 bit)
- \details Executes a exclusive LDR instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDR Exclusive (16 bit)
- \details Executes a exclusive LDR instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDR Exclusive (32 bit)
- \details Executes a exclusive LDR instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (8 bit)
- \details Executes a exclusive STR instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (16 bit)
- \details Executes a exclusive STR instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
- return(result);
-}
-
-
-/**
- \brief STR Exclusive (32 bit)
- \details Executes a exclusive STR instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/**
- \brief Remove the exclusive lock
- \details Removes the exclusive lock which is created by LDREX.
- */
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
-{
- __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/**
- \brief Signed Saturate
- \details Saturates a signed value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/**
- \brief Unsigned Saturate
- \details Saturates an unsigned value.
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/**
- \brief Rotate Right with Extend (32 bit)
- \details Moves each bit of a bitstring right by one bit.
- The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to rotate
- \return Rotated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/**
- \brief LDRT Unprivileged (8 bit)
- \details Executes a Unprivileged LDRT instruction for 8 bit value.
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint8_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (16 bit)
- \details Executes a Unprivileged LDRT instruction for 16 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return ((uint16_t) result); /* Add explicit type cast here */
-}
-
-
-/**
- \brief LDRT Unprivileged (32 bit)
- \details Executes a Unprivileged LDRT instruction for 32 bit values.
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/**
- \brief STRT Unprivileged (8 bit)
- \details Executes a Unprivileged STRT instruction for 8 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
-{
- __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (16 bit)
- \details Executes a Unprivileged STRT instruction for 16 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
-{
- __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/**
- \brief STRT Unprivileged (32 bit)
- \details Executes a Unprivileged STRT instruction for 32 bit values.
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- */
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
-{
- __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
-}
-
-#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({ \
- int32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
- union llreg_u{
- uint32_t w32[2];
- uint64_t w64;
- } llr;
- llr.w64 = acc;
-
-#ifndef __ARMEB__ /* Little endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else /* Big endian */
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
- return(llr.w64);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
-{
- int32_t result;
-
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- if (ARG3 == 0) \
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x04) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#if defined ( __GNUC__ )
-#pragma GCC diagnostic pop
-#endif
-
-#endif /* __CMSIS_GCC_H */
diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h
deleted file mode 100644
index 711dad551702720712e7933bb693699e5ea745fa..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/core_cm0.h
+++ /dev/null
@@ -1,798 +0,0 @@
-/**************************************************************************//**
- * @file core_cm0.h
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version V4.30
- * @date 20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M0
- @{
- */
-
-/* CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
- __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __CSMC__ )
- #define __packed
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
- #define __STATIC_INLINE static inline
-
-#else
- #error Unknown compiler
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "core_cmInstr.h" /* Core Instruction Access */
-#include "core_cmFunc.h" /* Core Function Access */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM0_REV
- #define __CM0_REV 0x0000U
- #warning "__CM0_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:1; /*!< bit: 0 Reserved */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31U];
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31U];
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31U];
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31U];
- uint32_t RESERVED4[64U];
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- uint32_t RESERVED0;
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
- Therefore they are not covered by the Cortex-M0 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-
-/**
- \brief Enable External Interrupt
- \details Enables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Disable External Interrupt
- \details Disables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
- \param [in] IRQn Interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of an external interrupt.
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of an external interrupt.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of an interrupt.
- \note The priority cannot be set for every core interrupt.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) < 0)
- {
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of an interrupt.
- The interrupt number can be positive to specify an external (device specific) interrupt,
- or negative to specify an internal (core) interrupt.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) < 0)
- {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h
deleted file mode 100644
index b04aa3905323c5a0376c26989c1a3c9b8f3afe6a..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/core_cm0plus.h
+++ /dev/null
@@ -1,914 +0,0 @@
-/**************************************************************************//**
- * @file core_cm0plus.h
- * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version V4.30
- * @date 20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex-M0+
- @{
- */
-
-/* CMSIS CM0+ definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
-#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
-#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
- __CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __CSMC__ )
- #define __packed
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
- #define __STATIC_INLINE static inline
-
-#else
- #error Unknown compiler
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "core_cmInstr.h" /* Core Instruction Access */
-#include "core_cmFunc.h" /* Core Function Access */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM0PLUS_REV
- #define __CM0PLUS_REV 0x0000U
- #warning "__CM0PLUS_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __VTOR_PRESENT
- #define __VTOR_PRESENT 0U
- #warning "__VTOR_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core MPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31U];
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31U];
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31U];
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31U];
- uint32_t RESERVED4[64U];
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
-#if (__VTOR_PRESENT == 1U)
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
-#else
- uint32_t RESERVED0;
-#endif
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if (__VTOR_PRESENT == 1U)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
- Therefore they are not covered by the Cortex-M0+ header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M0+ Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-#if (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-
-/**
- \brief Enable External Interrupt
- \details Enables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Disable External Interrupt
- \details Disables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
- \param [in] IRQn Interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of an external interrupt.
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of an external interrupt.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of an interrupt.
- \note The priority cannot be set for every core interrupt.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) < 0)
- {
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of an interrupt.
- The interrupt number can be positive to specify an external (device specific) interrupt,
- or negative to specify an internal (core) interrupt.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) < 0)
- {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Drivers/CMSIS/Include/core_cm3.h
deleted file mode 100644
index b4ac4c7b05a799590575c0b5c8e24c51748ee20b..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/core_cm3.h
+++ /dev/null
@@ -1,1763 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.h
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V4.30
- * @date 20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M3
- @{
- */
-
-/* CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
- __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03U) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __CSMC__ )
- #define __packed
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
- #define __STATIC_INLINE static inline
-
-#else
- #error Unknown compiler
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "core_cmInstr.h" /* Core Instruction Access */
-#include "core_cmFunc.h" /* Core Function Access */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM3_REV
- #define __CM3_REV 0x0200U
- #warning "__CM3_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5U];
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if (__CM3_REV < 0x0201U) /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-#else
- uint32_t RESERVED1[1U];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable External Interrupt
- \details Enables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Disable External Interrupt
- \details Disables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
- \param [in] IRQn Interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of an external interrupt.
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of an external interrupt.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in NVIC and returns the active bit.
- \param [in] IRQn Interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of an interrupt.
- \note The priority cannot be set for every core interrupt.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) < 0)
- {
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of an interrupt.
- The interrupt number can be positive to specify an external (device specific) interrupt,
- or negative to specify an internal (core) interrupt.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) < 0)
- {
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Drivers/CMSIS/Include/core_cm4.h
deleted file mode 100644
index dc840ebf2221382b8ca8e9ed8ce72b99e4027ad1..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/core_cm4.h
+++ /dev/null
@@ -1,1937 +0,0 @@
-/**************************************************************************//**
- * @file core_cm4.h
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V4.30
- * @date 20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M4
- @{
- */
-
-/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
- __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x04U) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __CSMC__ )
- #define __packed
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
- #define __STATIC_INLINE static inline
-
-#else
- #error Unknown compiler
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1U
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#endif
-
-#include "core_cmInstr.h" /* Core Instruction Access */
-#include "core_cmFunc.h" /* Core Function Access */
-#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM4_REV
- #define __CM4_REV 0x0000U
- #warning "__CM4_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core FPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5U];
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/**
- \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-#if (__FPU_PRESENT == 1U)
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable External Interrupt
- \details Enables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Disable External Interrupt
- \details Disables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
- \param [in] IRQn Interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of an external interrupt.
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of an external interrupt.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in NVIC and returns the active bit.
- \param [in] IRQn Interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of an interrupt.
- \note The priority cannot be set for every core interrupt.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) < 0)
- {
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of an interrupt.
- The interrupt number can be positive to specify an external (device specific) interrupt,
- or negative to specify an internal (core) interrupt.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) < 0)
- {
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Drivers/CMSIS/Include/core_cm7.h
deleted file mode 100644
index 3b7530ad505b57d283cc6f07e7f51b9a54be9a0b..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/core_cm7.h
+++ /dev/null
@@ -1,2512 +0,0 @@
-/**************************************************************************//**
- * @file core_cm7.h
- * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version V4.30
- * @date 20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM7_H_GENERIC
-#define __CORE_CM7_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M7
- @{
- */
-
-/* CMSIS CM7 definitions */
-#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
-#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
-#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
- __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x07U) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __CSMC__ )
- #define __packed
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
- #define __STATIC_INLINE static inline
-
-#else
- #error Unknown compiler
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1U
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#endif
-
-#include "core_cmInstr.h" /* Core Instruction Access */
-#include "core_cmFunc.h" /* Core Function Access */
-#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM7_H_DEPENDANT
-#define __CORE_CM7_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM7_REV
- #define __CM7_REV 0x0000U
- #warning "__CM7_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __ICACHE_PRESENT
- #define __ICACHE_PRESENT 0U
- #warning "__ICACHE_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __DCACHE_PRESENT
- #define __DCACHE_PRESENT 0U
- #warning "__DCACHE_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __DTCM_PRESENT
- #define __DTCM_PRESENT 0U
- #warning "__DTCM_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 3U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M7 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core FPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[1U];
- __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
- __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
- __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
- __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
- uint32_t RESERVED3[93U];
- __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
- uint32_t RESERVED4[15U];
- __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
- __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
- uint32_t RESERVED5[1U];
- __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
- uint32_t RESERVED6[1U];
- __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
- __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
- __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
- __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
- __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
- __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
- __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
- __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
- uint32_t RESERVED7[6U];
- __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
- __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
- __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
- __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
- __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
- uint32_t RESERVED8[1U];
- __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */
-#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
-
-#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */
-#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
-
-#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */
-#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
-
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
-
-#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */
-#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
-
-#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */
-#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
- uint32_t RESERVED3[981U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/**
- \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
- __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/* Media and FP Feature Register 2 Definitions */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-#if (__FPU_PRESENT == 1U)
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable External Interrupt
- \details Enables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Disable External Interrupt
- \details Disables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
- \param [in] IRQn Interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of an external interrupt.
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of an external interrupt.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in NVIC and returns the active bit.
- \param [in] IRQn Interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of an interrupt.
- \note The priority cannot be set for every core interrupt.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) < 0)
- {
- SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of an interrupt.
- The interrupt number can be positive to specify an external (device specific) interrupt,
- or negative to specify an internal (core) interrupt.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) < 0)
- {
- return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ########################## FPU functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_FpuFunctions FPU Functions
- \brief Function that provides FPU type.
- @{
- */
-
-/**
- \brief get FPU type
- \details returns the FPU type
- \returns
- - \b 0: No FPU
- - \b 1: Single precision FPU
- - \b 2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
- uint32_t mvfr0;
-
- mvfr0 = SCB->MVFR0;
- if ((mvfr0 & 0x00000FF0UL) == 0x220UL)
- {
- return 2UL; /* Double + Single precision FPU */
- }
- else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)
- {
- return 1UL; /* Single precision FPU */
- }
- else
- {
- return 0UL; /* No FPU */
- }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ########################## Cache functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_CacheFunctions Cache Functions
- \brief Functions that configure Instruction and Data cache.
- @{
- */
-
-/* Cache Size ID Register Macros */
-#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
-#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
-
-
-/**
- \brief Enable I-Cache
- \details Turns on I-Cache
- */
-__STATIC_INLINE void SCB_EnableICache (void)
-{
- #if (__ICACHE_PRESENT == 1U)
- __DSB();
- __ISB();
- SCB->ICIALLU = 0UL; /* invalidate I-Cache */
- SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Disable I-Cache
- \details Turns off I-Cache
- */
-__STATIC_INLINE void SCB_DisableICache (void)
-{
- #if (__ICACHE_PRESENT == 1U)
- __DSB();
- __ISB();
- SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
- SCB->ICIALLU = 0UL; /* invalidate I-Cache */
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Invalidate I-Cache
- \details Invalidates I-Cache
- */
-__STATIC_INLINE void SCB_InvalidateICache (void)
-{
- #if (__ICACHE_PRESENT == 1U)
- __DSB();
- __ISB();
- SCB->ICIALLU = 0UL;
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Enable D-Cache
- \details Turns on D-Cache
- */
-__STATIC_INLINE void SCB_EnableDCache (void)
-{
- #if (__DCACHE_PRESENT == 1U)
- uint32_t ccsidr;
- uint32_t sets;
- uint32_t ways;
-
- SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- /* invalidate D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
- ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways--);
- } while(sets--);
- __DSB();
-
- SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Disable D-Cache
- \details Turns off D-Cache
- */
-__STATIC_INLINE void SCB_DisableDCache (void)
-{
- #if (__DCACHE_PRESENT == 1U)
- uint32_t ccsidr;
- uint32_t sets;
- uint32_t ways;
-
- SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
-
- /* clean & invalidate D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
- ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways--);
- } while(sets--);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Invalidate D-Cache
- \details Invalidates D-Cache
- */
-__STATIC_INLINE void SCB_InvalidateDCache (void)
-{
- #if (__DCACHE_PRESENT == 1U)
- uint32_t ccsidr;
- uint32_t sets;
- uint32_t ways;
-
- SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- /* invalidate D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
- ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways--);
- } while(sets--);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Clean D-Cache
- \details Cleans D-Cache
- */
-__STATIC_INLINE void SCB_CleanDCache (void)
-{
- #if (__DCACHE_PRESENT == 1U)
- uint32_t ccsidr;
- uint32_t sets;
- uint32_t ways;
-
- SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- /* clean D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
- ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways--);
- } while(sets--);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief Clean & Invalidate D-Cache
- \details Cleans and Invalidates D-Cache
- */
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
-{
- #if (__DCACHE_PRESENT == 1U)
- uint32_t ccsidr;
- uint32_t sets;
- uint32_t ways;
-
- SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */
- __DSB();
-
- ccsidr = SCB->CCSIDR;
-
- /* clean & invalidate D-Cache */
- sets = (uint32_t)(CCSIDR_SETS(ccsidr));
- do {
- ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
- do {
- SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
- ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
- #if defined ( __CC_ARM )
- __schedule_barrier();
- #endif
- } while (ways--);
- } while(sets--);
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief D-Cache Invalidate by address
- \details Invalidates D-Cache for the given address
- \param[in] addr address (aligned to 32-byte boundary)
- \param[in] dsize size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
- #if (__DCACHE_PRESENT == 1U)
- int32_t op_size = dsize;
- uint32_t op_addr = (uint32_t)addr;
- int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
- __DSB();
-
- while (op_size > 0) {
- SCB->DCIMVAC = op_addr;
- op_addr += linesize;
- op_size -= linesize;
- }
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief D-Cache Clean by address
- \details Cleans D-Cache for the given address
- \param[in] addr address (aligned to 32-byte boundary)
- \param[in] dsize size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
- #if (__DCACHE_PRESENT == 1)
- int32_t op_size = dsize;
- uint32_t op_addr = (uint32_t) addr;
- int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
- __DSB();
-
- while (op_size > 0) {
- SCB->DCCMVAC = op_addr;
- op_addr += linesize;
- op_size -= linesize;
- }
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/**
- \brief D-Cache Clean and Invalidate by address
- \details Cleans and invalidates D_Cache for the given address
- \param[in] addr address (aligned to 32-byte boundary)
- \param[in] dsize size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
- #if (__DCACHE_PRESENT == 1U)
- int32_t op_size = dsize;
- uint32_t op_addr = (uint32_t) addr;
- int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
- __DSB();
-
- while (op_size > 0) {
- SCB->DCCIMVAC = op_addr;
- op_addr += linesize;
- op_size -= linesize;
- }
-
- __DSB();
- __ISB();
- #endif
-}
-
-
-/*@} end of CMSIS_Core_CacheFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cmFunc.h b/Drivers/CMSIS/Include/core_cmFunc.h
deleted file mode 100644
index 652a48af07a93d9a48ea9bfa818eebd6429045da..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/core_cmFunc.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/**************************************************************************//**
- * @file core_cmFunc.h
- * @brief CMSIS Cortex-M Core Function Access Header File
- * @version V4.30
- * @date 20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
-*/
-
-/*------------------ RealView Compiler -----------------*/
-#if defined ( __CC_ARM )
- #include "cmsis_armcc.h"
-
-/*------------------ ARM Compiler V6 -------------------*/
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #include "cmsis_armcc_V6.h"
-
-/*------------------ GNU Compiler ----------------------*/
-#elif defined ( __GNUC__ )
- #include "cmsis_gcc.h"
-
-/*------------------ ICC Compiler ----------------------*/
-#elif defined ( __ICCARM__ )
- #include <cmsis_iar.h>
-
-/*------------------ TI CCS Compiler -------------------*/
-#elif defined ( __TMS470__ )
- #include <cmsis_ccs.h>
-
-/*------------------ TASKING Compiler ------------------*/
-#elif defined ( __TASKING__ )
- /*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-/*------------------ COSMIC Compiler -------------------*/
-#elif defined ( __CSMC__ )
- #include <cmsis_csm.h>
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-#endif /* __CORE_CMFUNC_H */
diff --git a/Drivers/CMSIS/Include/core_cmInstr.h b/Drivers/CMSIS/Include/core_cmInstr.h
deleted file mode 100644
index f474b0e6f362c73223e59af36ad30d2b87b9a61d..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/core_cmInstr.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/**************************************************************************//**
- * @file core_cmInstr.h
- * @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V4.30
- * @date 20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-/*------------------ RealView Compiler -----------------*/
-#if defined ( __CC_ARM )
- #include "cmsis_armcc.h"
-
-/*------------------ ARM Compiler V6 -------------------*/
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #include "cmsis_armcc_V6.h"
-
-/*------------------ GNU Compiler ----------------------*/
-#elif defined ( __GNUC__ )
- #include "cmsis_gcc.h"
-
-/*------------------ ICC Compiler ----------------------*/
-#elif defined ( __ICCARM__ )
- #include <cmsis_iar.h>
-
-/*------------------ TI CCS Compiler -------------------*/
-#elif defined ( __TMS470__ )
- #include <cmsis_ccs.h>
-
-/*------------------ TASKING Compiler ------------------*/
-#elif defined ( __TASKING__ )
- /*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-/*------------------ COSMIC Compiler -------------------*/
-#elif defined ( __CSMC__ )
- #include <cmsis_csm.h>
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */
diff --git a/Drivers/CMSIS/Include/core_cmSimd.h b/Drivers/CMSIS/Include/core_cmSimd.h
deleted file mode 100644
index 66bf5c2a725b6d1986ce32f2bd765ebe5aa481ea..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/core_cmSimd.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/**************************************************************************//**
- * @file core_cmSimd.h
- * @brief CMSIS Cortex-M SIMD Header File
- * @version V4.30
- * @date 20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CMSIMD_H
-#define __CORE_CMSIMD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-/*------------------ RealView Compiler -----------------*/
-#if defined ( __CC_ARM )
- #include "cmsis_armcc.h"
-
-/*------------------ ARM Compiler V6 -------------------*/
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #include "cmsis_armcc_V6.h"
-
-/*------------------ GNU Compiler ----------------------*/
-#elif defined ( __GNUC__ )
- #include "cmsis_gcc.h"
-
-/*------------------ ICC Compiler ----------------------*/
-#elif defined ( __ICCARM__ )
- #include <cmsis_iar.h>
-
-/*------------------ TI CCS Compiler -------------------*/
-#elif defined ( __TMS470__ )
- #include <cmsis_ccs.h>
-
-/*------------------ TASKING Compiler ------------------*/
-#elif defined ( __TASKING__ )
- /*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-/*------------------ COSMIC Compiler -------------------*/
-#elif defined ( __CSMC__ )
- #include <cmsis_csm.h>
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CMSIMD_H */
diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h
deleted file mode 100644
index 514dbd81b9f776af5e0f29e65d075866c05a4b5a..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/core_sc000.h
+++ /dev/null
@@ -1,926 +0,0 @@
-/**************************************************************************//**
- * @file core_sc000.h
- * @brief CMSIS SC000 Core Peripheral Access Layer Header File
- * @version V4.30
- * @date 20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC000_H_GENERIC
-#define __CORE_SC000_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup SC000
- @{
- */
-
-/* CMSIS SC000 definitions */
-#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
-#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
-#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
- __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_SC (000U) /*!< Cortex secure core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __CSMC__ )
- #define __packed
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
- #define __STATIC_INLINE static inline
-
-#else
- #error Unknown compiler
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "core_cmInstr.h" /* Core Instruction Access */
-#include "core_cmFunc.h" /* Core Function Access */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC000_H_DEPENDANT
-#define __CORE_SC000_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __SC000_REV
- #define __SC000_REV 0x0000U
- #warning "__SC000_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC000 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core MPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:1; /*!< bit: 0 Reserved */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31U];
- __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31U];
- __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31U];
- __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31U];
- uint32_t RESERVED4[64U];
- __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED0[1U];
- __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- uint32_t RESERVED1[154U];
- __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
- Therefore they are not covered by the SC000 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of SC000 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-#if (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
-#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
-#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
-
-
-/**
- \brief Enable External Interrupt
- \details Enables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Disable External Interrupt
- \details Disables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
- \param [in] IRQn Interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of an external interrupt.
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of an external interrupt.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of an interrupt.
- \note The priority cannot be set for every core interrupt.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) < 0)
- {
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
- else
- {
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of an interrupt.
- The interrupt number can be positive to specify an external (device specific) interrupt,
- or negative to specify an internal (core) interrupt.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) < 0)
- {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Drivers/CMSIS/Include/core_sc300.h
deleted file mode 100644
index 8bd18aa318a982b66863b4e413672eed272d2657..0000000000000000000000000000000000000000
--- a/Drivers/CMSIS/Include/core_sc300.h
+++ /dev/null
@@ -1,1745 +0,0 @@
-/**************************************************************************//**
- * @file core_sc300.h
- * @brief CMSIS SC300 Core Peripheral Access Layer Header File
- * @version V4.30
- * @date 20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC300_H_GENERIC
-#define __CORE_SC300_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup SC3000
- @{
- */
-
-/* CMSIS SC300 definitions */
-#define __SC300_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
-#define __SC300_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
-#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
- __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_SC (300U) /*!< Cortex secure core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __CSMC__ )
- #define __packed
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
- #define __STATIC_INLINE static inline
-
-#else
- #error Unknown compiler
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
- This core does not support an FPU at all
-*/
-#define __FPU_USED 0U
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#endif
-
-#include "core_cmInstr.h" /* Core Instruction Access */
-#include "core_cmFunc.h" /* Core Function Access */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC300_H_DEPENDANT
-#define __CORE_SC300_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __SC300_REV
- #define __SC300_REV 0x0000U
- #warning "__SC300_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC300 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5U];
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
- uint32_t RESERVED1[129U];
- __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- uint32_t RESERVED1[1U];
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable External Interrupt
- \details Enables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Disable External Interrupt
- \details Disables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
- \param [in] IRQn Interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of an external interrupt.
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of an external interrupt.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in NVIC and returns the active bit.
- \param [in] IRQn Interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of an interrupt.
- \note The priority cannot be set for every core interrupt.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) < 0)
- {
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of an interrupt.
- The interrupt number can be positive to specify an external (device specific) interrupt,
- or negative to specify an internal (core) interrupt.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) < 0)
- {
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h
deleted file mode 100644
index f7414df89d4bbeb5683dff23d1ace8e41b316fbb..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_bus.h
+++ /dev/null
@@ -1,1031 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_bus.h
- * @author MCD Application Team
- * @brief Header file of BUS LL module.
-
- @verbatim
- ##### RCC Limitations #####
- ==============================================================================
- [..]
- A delay between an RCC peripheral clock enable and the effective peripheral
- enabling should be taken into account in order to manage the peripheral read/write
- from/to registers.
- (+) This delay depends on the peripheral mapping.
- (++) AHB & APB peripherals, 1 dummy read is necessary
-
- [..]
- Workarounds:
- (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
- inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_BUS_H
-#define __STM32F1xx_LL_BUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined(RCC)
-
-/** @defgroup BUS_LL BUS
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-#if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST)
-#define RCC_AHBRSTR_SUPPORT
-#endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
- * @{
- */
-
-/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
- * @{
- */
-#define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
-#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
-#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
-#if defined(DMA2)
-#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
-#endif /*DMA2*/
-#if defined(ETH)
-#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN
-#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN
-#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN
-#endif /*ETH*/
-#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
-#if defined(FSMC_Bank1)
-#define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
-#endif /*FSMC_Bank1*/
-#if defined(USB_OTG_FS)
-#define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN
-#endif /*USB_OTG_FS*/
-#if defined(SDIO)
-#define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN
-#endif /*SDIO*/
-#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
- * @{
- */
-#define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
-#define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN
-#if defined(CAN1)
-#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
-#endif /*CAN1*/
-#if defined(CAN2)
-#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
-#endif /*CAN2*/
-#if defined(CEC)
-#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
-#endif /*CEC*/
-#if defined(DAC)
-#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
-#endif /*DAC*/
-#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
-#if defined(I2C2)
-#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
-#endif /*I2C2*/
-#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
-#if defined(SPI2)
-#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
-#endif /*SPI2*/
-#if defined(SPI3)
-#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
-#endif /*SPI3*/
-#if defined(TIM12)
-#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
-#endif /*TIM12*/
-#if defined(TIM13)
-#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
-#endif /*TIM13*/
-#if defined(TIM14)
-#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
-#endif /*TIM14*/
-#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
-#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
-#if defined(TIM4)
-#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
-#endif /*TIM4*/
-#if defined(TIM5)
-#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
-#endif /*TIM5*/
-#if defined(TIM6)
-#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
-#endif /*TIM6*/
-#if defined(TIM7)
-#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
-#endif /*TIM7*/
-#if defined(UART4)
-#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
-#endif /*UART4*/
-#if defined(UART5)
-#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
-#endif /*UART5*/
-#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
-#if defined(USART3)
-#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
-#endif /*USART3*/
-#if defined(USB)
-#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
-#endif /*USB*/
-#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
- * @{
- */
-#define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
-#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
-#if defined(ADC2)
-#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
-#endif /*ADC2*/
-#if defined(ADC3)
-#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
-#endif /*ADC3*/
-#define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN
-#define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN
-#define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN
-#define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN
-#define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN
-#if defined(GPIOE)
-#define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN
-#endif /*GPIOE*/
-#if defined(GPIOF)
-#define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN
-#endif /*GPIOF*/
-#if defined(GPIOG)
-#define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN
-#endif /*GPIOG*/
-#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
-#if defined(TIM10)
-#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
-#endif /*TIM10*/
-#if defined(TIM11)
-#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
-#endif /*TIM11*/
-#if defined(TIM15)
-#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
-#endif /*TIM15*/
-#if defined(TIM16)
-#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
-#endif /*TIM16*/
-#if defined(TIM17)
-#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
-#endif /*TIM17*/
-#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
-#if defined(TIM8)
-#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
-#endif /*TIM8*/
-#if defined(TIM9)
-#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
-#endif /*TIM9*/
-#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
- * @{
- */
-
-/** @defgroup BUS_LL_EF_AHB1 AHB1
- * @{
- */
-
-/**
- * @brief Enable AHB1 peripherals clock.
- * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
- * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
- * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n
- * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->AHBENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHBENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if AHB1 peripheral clock is enabled or not
- * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n
- * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
- return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
-}
-
-/**
- * @brief Disable AHB1 peripherals clock.
- * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
- * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
- * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n
- * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
- * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
- * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHBENR, Periphs);
-}
-
-#if defined(RCC_AHBRSTR_SUPPORT)
-/**
- * @brief Force AHB1 peripherals reset.
- * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
- * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
-{
- SET_BIT(RCC->AHBRSTR, Periphs);
-}
-
-/**
- * @brief Release AHB1 peripherals reset.
- * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
- * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
- * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
- * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*)
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->AHBRSTR, Periphs);
-}
-#endif /* RCC_AHBRSTR_SUPPORT */
-
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EF_APB1 APB1
- * @{
- */
-
-/**
- * @brief Enable APB1 peripherals clock.
- * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
- * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
- * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
- * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB1ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if APB1 peripheral clock is enabled or not
- * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
- * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
- return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
-}
-
-/**
- * @brief Disable APB1 peripherals clock.
- * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
- * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
- * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
- * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB1ENR, Periphs);
-}
-
-/**
- * @brief Force APB1 peripherals reset.
- * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
- * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_ALL
- * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
-{
- SET_BIT(RCC->APB1RSTR, Periphs);
-}
-
-/**
- * @brief Release APB1 peripherals reset.
- * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
- * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB1_GRP1_PERIPH_ALL
- * @arg @ref LL_APB1_GRP1_PERIPH_BKP
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
- * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_PWR
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USART2
- * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
- * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB1RSTR, Periphs);
-}
-
-/**
- * @}
- */
-
-/** @defgroup BUS_LL_EF_APB2 APB2
- * @{
- */
-
-/**
- * @brief Enable APB2 peripherals clock.
- * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
-{
- __IO uint32_t tmpreg;
- SET_BIT(RCC->APB2ENR, Periphs);
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
- (void)tmpreg;
-}
-
-/**
- * @brief Check if APB2 peripheral clock is enabled or not
- * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- *
- * (*) value not defined in all devices.
- * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
- return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
-}
-
-/**
- * @brief Disable APB2 peripherals clock.
- * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR AFIOEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR IOPAEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR IOPBEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR IOPCEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR IOPDEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR IOPEEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR IOPFEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR IOPGEN LL_APB2_GRP1_DisableClock\n
- * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
- * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB2ENR, Periphs);
-}
-
-/**
- * @brief Force APB2 peripherals reset.
- * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR AFIORST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR IOPARST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR IOPERST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
- * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_ALL
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
-{
- SET_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
- * @brief Release APB2 peripherals reset.
- * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
- * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_APB2_GRP1_PERIPH_ALL
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_AFIO
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*)
- * @arg @ref LL_APB2_GRP1_PERIPH_USART1
- *
- * (*) value not defined in all devices.
- * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
-{
- CLEAR_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RCC) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_BUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h
deleted file mode 100644
index 862eda18b2c7ca64c80177c04f2fe4d554189c52..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h
+++ /dev/null
@@ -1,656 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_cortex.h
- * @author MCD Application Team
- * @brief Header file of CORTEX LL module.
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LL CORTEX driver contains a set of generic APIs that can be
- used by user:
- (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
- functions
- (+) Low power mode configuration (SCB register of Cortex-MCU)
- (+) MPU API to configure and enable regions
- (MPU services provided only on some devices)
- (+) API to access to MCU info (CPUID register)
- (+) API to enable fault handler (SHCSR accesses)
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_CORTEX_H
-#define __STM32F1xx_LL_CORTEX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-/** @defgroup CORTEX_LL CORTEX
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
- * @{
- */
-
-/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
- * @{
- */
-#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
-#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
- * @{
- */
-#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
-#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
-#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
-/**
- * @}
- */
-
-#if __MPU_PRESENT
-
-/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
- * @{
- */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
-#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
-#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
- * @{
- */
-#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
-#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
-#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
-#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
-#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
-#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
-#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
-#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
- * @{
- */
-#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
- * @{
- */
-#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
-#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
-#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
-#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
-#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
-#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
- * @{
- */
-#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
-#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
-#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
-#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
- * @{
- */
-#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
-#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
- * @{
- */
-#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
-#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
- * @{
- */
-#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
-#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
- * @{
- */
-#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
-#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
-/**
- * @}
- */
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
- * @{
- */
-
-/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
- * @{
- */
-
-/**
- * @brief This function checks if the Systick counter flag is active or not.
- * @note It can be used in timeout function on application side.
- * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
-{
- return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
-}
-
-/**
- * @brief Configures the SysTick clock source
- * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
-{
- if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
- {
- SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
- }
- else
- {
- CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
- }
-}
-
-/**
- * @brief Get the SysTick clock source
- * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
- * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
-{
- return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-}
-
-/**
- * @brief Enable SysTick exception request
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
-{
- SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Disable SysTick exception request
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
- * @retval None
- */
-__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
-{
- CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
- * @brief Checks if the SYSTICK interrupt is enabled or disabled.
- * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
-{
- return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
- * @{
- */
-
-/**
- * @brief Processor uses sleep as its low power mode
- * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableSleep(void)
-{
- /* Clear SLEEPDEEP bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
- * @brief Processor uses deep sleep as its low power mode
- * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
-{
- /* Set SLEEPDEEP bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
- * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
- * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
- * empty main application.
- * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
-{
- /* Set SLEEPONEXIT bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
- * @brief Do not sleep when returning to Thread mode.
- * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
-{
- /* Clear SLEEPONEXIT bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
- * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
- * processor.
- * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
-{
- /* Set SEVEONPEND bit of Cortex System Control Register */
- SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
- * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
- * excluded
- * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
- * @retval None
- */
-__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
-{
- /* Clear SEVEONPEND bit of Cortex System Control Register */
- CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
- * @{
- */
-
-/**
- * @brief Enable a fault in System handler control register (SHCSR)
- * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
- * @param Fault This parameter can be a combination of the following values:
- * @arg @ref LL_HANDLER_FAULT_USG
- * @arg @ref LL_HANDLER_FAULT_BUS
- * @arg @ref LL_HANDLER_FAULT_MEM
- * @retval None
- */
-__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
-{
- /* Enable the system handler fault */
- SET_BIT(SCB->SHCSR, Fault);
-}
-
-/**
- * @brief Disable a fault in System handler control register (SHCSR)
- * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
- * @param Fault This parameter can be a combination of the following values:
- * @arg @ref LL_HANDLER_FAULT_USG
- * @arg @ref LL_HANDLER_FAULT_BUS
- * @arg @ref LL_HANDLER_FAULT_MEM
- * @retval None
- */
-__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
-{
- /* Disable the system handler fault */
- CLEAR_BIT(SCB->SHCSR, Fault);
-}
-
-/**
- * @}
- */
-
-/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
- * @{
- */
-
-/**
- * @brief Get Implementer code
- * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
- * @retval Value should be equal to 0x41 for ARM
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
-}
-
-/**
- * @brief Get Variant number (The r value in the rnpn product revision identifier)
- * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
- * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
-}
-
-/**
- * @brief Get Constant number
- * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
- * @retval Value should be equal to 0xF for Cortex-M3 devices
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
-}
-
-/**
- * @brief Get Part number
- * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
- * @retval Value should be equal to 0xC23 for Cortex-M3
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
-}
-
-/**
- * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
- * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
- * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
- */
-__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
-{
- return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
-}
-
-/**
- * @}
- */
-
-#if __MPU_PRESENT
-/** @defgroup CORTEX_LL_EF_MPU MPU
- * @{
- */
-
-/**
- * @brief Enable MPU with input options
- * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
- * @param Options This parameter can be one of the following values:
- * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
- * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
- * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
- * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
-{
- /* Enable the MPU*/
- WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
- /* Ensure MPU settings take effects */
- __DSB();
- /* Sequence instruction fetches using update settings */
- __ISB();
-}
-
-/**
- * @brief Disable MPU
- * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_Disable(void)
-{
- /* Make sure outstanding transfers are done */
- __DMB();
- /* Disable MPU*/
- WRITE_REG(MPU->CTRL, 0U);
-}
-
-/**
- * @brief Check if MPU is enabled or not
- * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
-{
- return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
-}
-
-/**
- * @brief Enable a MPU region
- * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
-{
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Enable the MPU region */
- SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
- * @brief Configure and enable a region
- * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
- * MPU_RBAR REGION LL_MPU_ConfigRegion\n
- * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
- * MPU_RASR XN LL_MPU_ConfigRegion\n
- * MPU_RASR AP LL_MPU_ConfigRegion\n
- * MPU_RASR S LL_MPU_ConfigRegion\n
- * MPU_RASR C LL_MPU_ConfigRegion\n
- * MPU_RASR B LL_MPU_ConfigRegion\n
- * MPU_RASR SIZE LL_MPU_ConfigRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @param Address Value of region base address
- * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
- * @param Attributes This parameter can be a combination of the following values:
- * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
- * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
- * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
- * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
- * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
- * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
- * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
- * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
- * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
- * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
- * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
- * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
- * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
-{
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Set base address */
- WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
- /* Configure MPU */
- WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
-}
-
-/**
- * @brief Disable a region
- * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
- * MPU_RASR ENABLE LL_MPU_DisableRegion
- * @param Region This parameter can be one of the following values:
- * @arg @ref LL_MPU_REGION_NUMBER0
- * @arg @ref LL_MPU_REGION_NUMBER1
- * @arg @ref LL_MPU_REGION_NUMBER2
- * @arg @ref LL_MPU_REGION_NUMBER3
- * @arg @ref LL_MPU_REGION_NUMBER4
- * @arg @ref LL_MPU_REGION_NUMBER5
- * @arg @ref LL_MPU_REGION_NUMBER6
- * @arg @ref LL_MPU_REGION_NUMBER7
- * @retval None
- */
-__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
-{
- /* Set Region number */
- WRITE_REG(MPU->RNR, Region);
- /* Disable the MPU region */
- CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
- * @}
- */
-
-#endif /* __MPU_PRESENT */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_CORTEX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h
deleted file mode 100644
index 5eb69aefe3d3a12dbcdcb1f287c627795d404dba..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_dma.h
+++ /dev/null
@@ -1,1976 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_dma.h
- * @author MCD Application Team
- * @brief Header file of DMA LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_DMA_H
-#define __STM32F1xx_LL_DMA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (DMA1) || defined (DMA2)
-
-/** @defgroup DMA_LL DMA
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Variables DMA Private Variables
- * @{
- */
-/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
-static const uint8_t CHANNEL_OFFSET_TAB[] =
-{
- (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
- (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
-};
-/**
- * @}
- */
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_Private_Macros DMA Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
- * @{
- */
-typedef struct
-{
- uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
- or as Source base address in case of memory to memory transfer direction.
-
- This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
- uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
- or as Destination base address in case of memory to memory transfer direction.
-
- This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
- uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
- from memory to memory or from peripheral to memory.
- This parameter can be a value of @ref DMA_LL_EC_DIRECTION
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
-
- uint32_t Mode; /*!< Specifies the normal or circular operation mode.
- This parameter can be a value of @ref DMA_LL_EC_MODE
- @note: The circular buffer mode cannot be used if the memory to memory
- data transfer direction is configured on the selected Channel
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
-
- uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
- is incremented or not.
- This parameter can be a value of @ref DMA_LL_EC_PERIPH
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
-
- uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
- is incremented or not.
- This parameter can be a value of @ref DMA_LL_EC_MEMORY
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
-
- uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
- in case of memory to memory transfer direction.
- This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
-
- uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
- in case of memory to memory transfer direction.
- This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
-
- uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
- The data unit is equal to the source buffer configuration set in PeripheralSize
- or MemorySize parameters depending in the transfer direction.
- This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
-
- uint32_t Priority; /*!< Specifies the channel priority level.
- This parameter can be a value of @ref DMA_LL_EC_PRIORITY
-
- This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
-
-} LL_DMA_InitTypeDef;
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
- * @{
- */
-/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_DMA_WriteReg function
- * @{
- */
-#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
-#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
-#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
-#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
-#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
-#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
-#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
-#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
-#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
-#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
-#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
-#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
-#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
-#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
-#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
-#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
-#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
-#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
-#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
-#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
-#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
-#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_DMA_ReadReg function
- * @{
- */
-#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
-#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
-#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
-#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
-#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
-#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
-#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
-#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
-#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
-#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
-#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
-#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
-#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
-#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
-#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
-#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
-#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
-#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
-#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
-#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
-#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
-#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
-#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
-#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
-#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
-#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
-#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
-#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
- * @{
- */
-#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
-#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
-#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
- * @{
- */
-#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
-#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
-#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
-#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
-#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
-#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
-#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
-#endif /*USE_FULL_LL_DRIVER*/
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
- * @{
- */
-#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MODE Transfer mode
- * @{
- */
-#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
-#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
- * @{
- */
-#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
-#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
- * @{
- */
-#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
-#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
- * @{
- */
-#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
-#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
-#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
- * @{
- */
-#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
-#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
-#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
- * @{
- */
-#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
-#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
-#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
-#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
- * @{
- */
-
-/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
- * @{
- */
-/**
- * @brief Write a value in DMA register
- * @param __INSTANCE__ DMA Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in DMA register
- * @param __INSTANCE__ DMA Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
- * @{
- */
-
-/**
- * @brief Convert DMAx_Channely into DMAx
- * @param __CHANNEL_INSTANCE__ DMAx_Channely
- * @retval DMAx
- */
-#if defined(DMA2)
-#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
-(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
-#else
-#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
-#endif
-
-/**
- * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
- * @param __CHANNEL_INSTANCE__ DMAx_Channely
- * @retval LL_DMA_CHANNEL_y
- */
-#if defined (DMA2)
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- LL_DMA_CHANNEL_7)
-#else
-#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
-(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
- ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
- LL_DMA_CHANNEL_7)
-#endif
-
-/**
- * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
- * @param __DMA_INSTANCE__ DMAx
- * @param __CHANNEL__ LL_DMA_CHANNEL_y
- * @retval DMAx_Channely
- */
-#if defined (DMA2)
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
- DMA1_Channel7)
-#else
-#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
- DMA1_Channel7)
-#endif
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
- * @{
- */
-
-/** @defgroup DMA_LL_EF_Configuration Configuration
- * @{
- */
-/**
- * @brief Enable DMA channel.
- * @rmtoll CCR EN LL_DMA_EnableChannel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
-}
-
-/**
- * @brief Disable DMA channel.
- * @rmtoll CCR EN LL_DMA_DisableChannel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
-}
-
-/**
- * @brief Check if DMA channel is enabled or disabled.
- * @rmtoll CCR EN LL_DMA_IsEnabledChannel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_EN) == (DMA_CCR_EN));
-}
-
-/**
- * @brief Configure all parameters link to DMA transfer.
- * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
- * CCR MEM2MEM LL_DMA_ConfigTransfer\n
- * CCR CIRC LL_DMA_ConfigTransfer\n
- * CCR PINC LL_DMA_ConfigTransfer\n
- * CCR MINC LL_DMA_ConfigTransfer\n
- * CCR PSIZE LL_DMA_ConfigTransfer\n
- * CCR MSIZE LL_DMA_ConfigTransfer\n
- * CCR PL LL_DMA_ConfigTransfer
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param Configuration This parameter must be a combination of all the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
- * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
- * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
- * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
- * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
- * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
- Configuration);
-}
-
-/**
- * @brief Set Data transfer direction (read from peripheral or from memory).
- * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
- * CCR MEM2MEM LL_DMA_SetDataTransferDirection
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param Direction This parameter can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
-}
-
-/**
- * @brief Get Data transfer direction (read from peripheral or from memory).
- * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
- * CCR MEM2MEM LL_DMA_GetDataTransferDirection
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- */
-__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_DIR | DMA_CCR_MEM2MEM));
-}
-
-/**
- * @brief Set DMA mode circular or normal.
- * @note The circular buffer mode cannot be used if the memory-to-memory
- * data transfer is configured on the selected Channel.
- * @rmtoll CCR CIRC LL_DMA_SetMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_DMA_MODE_NORMAL
- * @arg @ref LL_DMA_MODE_CIRCULAR
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
- Mode);
-}
-
-/**
- * @brief Get DMA mode circular or normal.
- * @rmtoll CCR CIRC LL_DMA_GetMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MODE_NORMAL
- * @arg @ref LL_DMA_MODE_CIRCULAR
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_CIRC));
-}
-
-/**
- * @brief Set Peripheral increment mode.
- * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
- * @arg @ref LL_DMA_PERIPH_INCREMENT
- * @arg @ref LL_DMA_PERIPH_NOINCREMENT
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
- PeriphOrM2MSrcIncMode);
-}
-
-/**
- * @brief Get Peripheral increment mode.
- * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PERIPH_INCREMENT
- * @arg @ref LL_DMA_PERIPH_NOINCREMENT
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_PINC));
-}
-
-/**
- * @brief Set Memory increment mode.
- * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
- * @arg @ref LL_DMA_MEMORY_INCREMENT
- * @arg @ref LL_DMA_MEMORY_NOINCREMENT
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
- MemoryOrM2MDstIncMode);
-}
-
-/**
- * @brief Get Memory increment mode.
- * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MEMORY_INCREMENT
- * @arg @ref LL_DMA_MEMORY_NOINCREMENT
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_MINC));
-}
-
-/**
- * @brief Set Peripheral size.
- * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
- * @arg @ref LL_DMA_PDATAALIGN_BYTE
- * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_PDATAALIGN_WORD
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
- PeriphOrM2MSrcDataSize);
-}
-
-/**
- * @brief Get Peripheral size.
- * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PDATAALIGN_BYTE
- * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_PDATAALIGN_WORD
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_PSIZE));
-}
-
-/**
- * @brief Set Memory size.
- * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
- * @arg @ref LL_DMA_MDATAALIGN_BYTE
- * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_MDATAALIGN_WORD
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
- MemoryOrM2MDstDataSize);
-}
-
-/**
- * @brief Get Memory size.
- * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_MDATAALIGN_BYTE
- * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
- * @arg @ref LL_DMA_MDATAALIGN_WORD
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_MSIZE));
-}
-
-/**
- * @brief Set Channel priority level.
- * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param Priority This parameter can be one of the following values:
- * @arg @ref LL_DMA_PRIORITY_LOW
- * @arg @ref LL_DMA_PRIORITY_MEDIUM
- * @arg @ref LL_DMA_PRIORITY_HIGH
- * @arg @ref LL_DMA_PRIORITY_VERYHIGH
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
- Priority);
-}
-
-/**
- * @brief Get Channel priority level.
- * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DMA_PRIORITY_LOW
- * @arg @ref LL_DMA_PRIORITY_MEDIUM
- * @arg @ref LL_DMA_PRIORITY_HIGH
- * @arg @ref LL_DMA_PRIORITY_VERYHIGH
- */
-__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_PL));
-}
-
-/**
- * @brief Set Number of data to transfer.
- * @note This action has no effect if
- * channel is enabled.
- * @rmtoll CNDTR NDT LL_DMA_SetDataLength
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
-{
- MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
- DMA_CNDTR_NDT, NbData);
-}
-
-/**
- * @brief Get Number of data to transfer.
- * @note Once the channel is enabled, the return value indicate the
- * remaining bytes to be transmitted.
- * @rmtoll CNDTR NDT LL_DMA_GetDataLength
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
- DMA_CNDTR_NDT));
-}
-
-/**
- * @brief Configure the Source and Destination addresses.
- * @note This API must not be called when the DMA channel is enabled.
- * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
- * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
- * CMAR MA LL_DMA_ConfigAddresses
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @param Direction This parameter can be one of the following values:
- * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
- * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
- uint32_t DstAddress, uint32_t Direction)
-{
- /* Direction Memory to Periph */
- if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
- {
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
- }
- /* Direction Periph to Memory and Memory to Memory */
- else
- {
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
- }
-}
-
-/**
- * @brief Set the Memory address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
-}
-
-/**
- * @brief Set the Peripheral address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
-{
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
-}
-
-/**
- * @brief Get Memory address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
-}
-
-/**
- * @brief Get Peripheral address.
- * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
- * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
-}
-
-/**
- * @brief Set the Memory to Memory Source address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
-}
-
-/**
- * @brief Set the Memory to Memory Destination address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @note This API must not be called when the DMA channel is enabled.
- * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
-{
- WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
-}
-
-/**
- * @brief Get the Memory to Memory Source address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
-}
-
-/**
- * @brief Get the Memory to Memory Destination address.
- * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
- * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
- */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Get Channel 1 global interrupt flag.
- * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
-}
-
-/**
- * @brief Get Channel 2 global interrupt flag.
- * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
-}
-
-/**
- * @brief Get Channel 3 global interrupt flag.
- * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
-}
-
-/**
- * @brief Get Channel 4 global interrupt flag.
- * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
-}
-
-/**
- * @brief Get Channel 5 global interrupt flag.
- * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
-}
-
-/**
- * @brief Get Channel 6 global interrupt flag.
- * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
-}
-
-/**
- * @brief Get Channel 7 global interrupt flag.
- * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
-}
-
-/**
- * @brief Get Channel 1 transfer complete flag.
- * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
-}
-
-/**
- * @brief Get Channel 2 transfer complete flag.
- * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
-}
-
-/**
- * @brief Get Channel 3 transfer complete flag.
- * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
-}
-
-/**
- * @brief Get Channel 4 transfer complete flag.
- * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
-}
-
-/**
- * @brief Get Channel 5 transfer complete flag.
- * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
-}
-
-/**
- * @brief Get Channel 6 transfer complete flag.
- * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
-}
-
-/**
- * @brief Get Channel 7 transfer complete flag.
- * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
-}
-
-/**
- * @brief Get Channel 1 half transfer flag.
- * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
-}
-
-/**
- * @brief Get Channel 2 half transfer flag.
- * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
-}
-
-/**
- * @brief Get Channel 3 half transfer flag.
- * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
-}
-
-/**
- * @brief Get Channel 4 half transfer flag.
- * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
-}
-
-/**
- * @brief Get Channel 5 half transfer flag.
- * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
-}
-
-/**
- * @brief Get Channel 6 half transfer flag.
- * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
-}
-
-/**
- * @brief Get Channel 7 half transfer flag.
- * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
-}
-
-/**
- * @brief Get Channel 1 transfer error flag.
- * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
-}
-
-/**
- * @brief Get Channel 2 transfer error flag.
- * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
-}
-
-/**
- * @brief Get Channel 3 transfer error flag.
- * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
-}
-
-/**
- * @brief Get Channel 4 transfer error flag.
- * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
-}
-
-/**
- * @brief Get Channel 5 transfer error flag.
- * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
-}
-
-/**
- * @brief Get Channel 6 transfer error flag.
- * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
-}
-
-/**
- * @brief Get Channel 7 transfer error flag.
- * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
- * @param DMAx DMAx Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
-{
- return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
-}
-
-/**
- * @brief Clear Channel 1 global interrupt flag.
- * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
-}
-
-/**
- * @brief Clear Channel 2 global interrupt flag.
- * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
-}
-
-/**
- * @brief Clear Channel 3 global interrupt flag.
- * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
-}
-
-/**
- * @brief Clear Channel 4 global interrupt flag.
- * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
-}
-
-/**
- * @brief Clear Channel 5 global interrupt flag.
- * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
-}
-
-/**
- * @brief Clear Channel 6 global interrupt flag.
- * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
-}
-
-/**
- * @brief Clear Channel 7 global interrupt flag.
- * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
-}
-
-/**
- * @brief Clear Channel 1 transfer complete flag.
- * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
-}
-
-/**
- * @brief Clear Channel 2 transfer complete flag.
- * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
-}
-
-/**
- * @brief Clear Channel 3 transfer complete flag.
- * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
-}
-
-/**
- * @brief Clear Channel 4 transfer complete flag.
- * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
-}
-
-/**
- * @brief Clear Channel 5 transfer complete flag.
- * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
-}
-
-/**
- * @brief Clear Channel 6 transfer complete flag.
- * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
-}
-
-/**
- * @brief Clear Channel 7 transfer complete flag.
- * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
-}
-
-/**
- * @brief Clear Channel 1 half transfer flag.
- * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
-}
-
-/**
- * @brief Clear Channel 2 half transfer flag.
- * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
-}
-
-/**
- * @brief Clear Channel 3 half transfer flag.
- * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
-}
-
-/**
- * @brief Clear Channel 4 half transfer flag.
- * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
-}
-
-/**
- * @brief Clear Channel 5 half transfer flag.
- * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
-}
-
-/**
- * @brief Clear Channel 6 half transfer flag.
- * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
-}
-
-/**
- * @brief Clear Channel 7 half transfer flag.
- * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
-}
-
-/**
- * @brief Clear Channel 1 transfer error flag.
- * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
-}
-
-/**
- * @brief Clear Channel 2 transfer error flag.
- * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
-}
-
-/**
- * @brief Clear Channel 3 transfer error flag.
- * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
-}
-
-/**
- * @brief Clear Channel 4 transfer error flag.
- * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
-}
-
-/**
- * @brief Clear Channel 5 transfer error flag.
- * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
-}
-
-/**
- * @brief Clear Channel 6 transfer error flag.
- * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
-}
-
-/**
- * @brief Clear Channel 7 transfer error flag.
- * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
- * @param DMAx DMAx Instance
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
-{
- WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable Transfer complete interrupt.
- * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
-}
-
-/**
- * @brief Enable Half transfer interrupt.
- * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
-}
-
-/**
- * @brief Enable Transfer error interrupt.
- * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
-}
-
-/**
- * @brief Disable Transfer complete interrupt.
- * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
-}
-
-/**
- * @brief Disable Half transfer interrupt.
- * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
-}
-
-/**
- * @brief Disable Transfer error interrupt.
- * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
-}
-
-/**
- * @brief Check if Transfer complete Interrupt is enabled.
- * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_TCIE) == (DMA_CCR_TCIE));
-}
-
-/**
- * @brief Check if Half transfer Interrupt is enabled.
- * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_HTIE) == (DMA_CCR_HTIE));
-}
-
-/**
- * @brief Check if Transfer error Interrupt is enabled.
- * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
- DMA_CCR_TEIE) == (DMA_CCR_TEIE));
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
-uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DMA1 || DMA2 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h
deleted file mode 100644
index dc4c3cef5911a6c82a42868abd903c509189c9a1..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_exti.h
+++ /dev/null
@@ -1,904 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_exti.h
- * @author MCD Application Team
- * @brief Header file of EXTI LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_EXTI_H
-#define __STM32F1xx_LL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private Macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
- * @{
- */
-typedef struct
-{
-
- uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
- This parameter can be any combination of @ref EXTI_LL_EC_LINE */
-
- FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
- This parameter can be set either to ENABLE or DISABLE */
-
- uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
- This parameter can be a value of @ref EXTI_LL_EC_MODE. */
-
- uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
- This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
-} LL_EXTI_InitTypeDef;
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
- * @{
- */
-
-/** @defgroup EXTI_LL_EC_LINE LINE
- * @{
- */
-#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */
-#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */
-#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */
-#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */
-#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */
-#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */
-#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */
-#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */
-#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */
-#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */
-#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */
-#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */
-#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */
-#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */
-#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */
-#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */
-#if defined(EXTI_IMR_IM16)
-#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */
-#endif
-#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */
-#if defined(EXTI_IMR_IM18)
-#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */
-#endif
-#if defined(EXTI_IMR_IM19)
-#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */
-#endif
-#if defined(EXTI_IMR_IM20)
-#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */
-#endif
-#if defined(EXTI_IMR_IM21)
-#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */
-#endif
-#if defined(EXTI_IMR_IM22)
-#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */
-#endif
-#if defined(EXTI_IMR_IM23)
-#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */
-#endif
-#if defined(EXTI_IMR_IM24)
-#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */
-#endif
-#if defined(EXTI_IMR_IM25)
-#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */
-#endif
-#if defined(EXTI_IMR_IM26)
-#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */
-#endif
-#if defined(EXTI_IMR_IM27)
-#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */
-#endif
-#if defined(EXTI_IMR_IM28)
-#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */
-#endif
-#if defined(EXTI_IMR_IM29)
-#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */
-#endif
-#if defined(EXTI_IMR_IM30)
-#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */
-#endif
-#if defined(EXTI_IMR_IM31)
-#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */
-#endif
-#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/
-
-
-#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
-
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup EXTI_LL_EC_MODE Mode
- * @{
- */
-#define LL_EXTI_MODE_IT ((uint8_t)0x00) /*!< Interrupt Mode */
-#define LL_EXTI_MODE_EVENT ((uint8_t)0x01) /*!< Event Mode */
-#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02) /*!< Interrupt & Event Mode */
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
- * @{
- */
-#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00) /*!< No Trigger Mode */
-#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01) /*!< Trigger Rising Mode */
-#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02) /*!< Trigger Falling Mode */
-#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03) /*!< Trigger Rising & Falling Mode */
-
-/**
- * @}
- */
-
-
-#endif /*USE_FULL_LL_DRIVER*/
-
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
- * @{
- */
-
-/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in EXTI register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in EXTI register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
- * @{
- */
-/** @defgroup EXTI_LL_EF_IT_Management IT_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->IMR, ExtiLine);
-}
-
-/**
- * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->IMR, ExtiLine);
-}
-
-
-/**
- * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
- * @note The reset value for the direct or internal lines (see RM)
- * is set to 1 in order to enable the interrupt by default.
- * Bits are set automatically at Power on.
- * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Event_Management Event_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Event request for Lines in range 0 to 31
- * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->EMR, ExtiLine);
-
-}
-
-
-/**
- * @brief Disable ExtiLine Event request for Lines in range 0 to 31
- * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->EMR, ExtiLine);
-}
-
-
-/**
- * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
- * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31
- * @param ExtiLine This parameter can be one of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_17
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @arg @ref LL_EXTI_LINE_ALL_0_31
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
-
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a rising edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_RTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->RTSR, ExtiLine);
-
-}
-
-
-/**
- * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a rising edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_RTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->RTSR, ExtiLine);
-
-}
-
-
-/**
- * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
- * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
- * @{
- */
-
-/**
- * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a falling edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_FTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for
- * the same interrupt line. In this case, both generate a trigger
- * condition.
- * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->FTSR, ExtiLine);
-}
-
-
-/**
- * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
- * @note The configurable wakeup lines are edge-triggered. No glitch must be
- * generated on these lines. If a Falling edge on a configurable interrupt
- * line occurs during a write operation in the EXTI_FTSR register, the
- * pending bit is not set.
- * Rising and falling edge triggers can be set for the same interrupt line.
- * In this case, both generate a trigger condition.
- * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
-{
- CLEAR_BIT(EXTI->FTSR, ExtiLine);
-}
-
-
-/**
- * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
- * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
- * @{
- */
-
-/**
- * @brief Generate a software Interrupt Event for Lines in range 0 to 31
- * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
- * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
- * resulting in an interrupt request generation.
- * This bit is cleared by clearing the corresponding bit in the EXTI_PR
- * register (by writing a 1 into the bit)
- * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
-{
- SET_BIT(EXTI->SWIER, ExtiLine);
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
- * @{
- */
-
-/**
- * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
-{
- return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
- * @brief Read ExtLine Combination Flag for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval @note This bit is set when the selected edge event arrives on the interrupt
- */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
-{
- return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
-}
-
-
-/**
- * @brief Clear ExtLine Flags for Lines in range 0 to 31
- * @note This bit is set when the selected edge event arrives on the interrupt
- * line. This bit is cleared by writing a 1 to the bit.
- * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31
- * @param ExtiLine This parameter can be a combination of the following values:
- * @arg @ref LL_EXTI_LINE_0
- * @arg @ref LL_EXTI_LINE_1
- * @arg @ref LL_EXTI_LINE_2
- * @arg @ref LL_EXTI_LINE_3
- * @arg @ref LL_EXTI_LINE_4
- * @arg @ref LL_EXTI_LINE_5
- * @arg @ref LL_EXTI_LINE_6
- * @arg @ref LL_EXTI_LINE_7
- * @arg @ref LL_EXTI_LINE_8
- * @arg @ref LL_EXTI_LINE_9
- * @arg @ref LL_EXTI_LINE_10
- * @arg @ref LL_EXTI_LINE_11
- * @arg @ref LL_EXTI_LINE_12
- * @arg @ref LL_EXTI_LINE_13
- * @arg @ref LL_EXTI_LINE_14
- * @arg @ref LL_EXTI_LINE_15
- * @arg @ref LL_EXTI_LINE_16
- * @arg @ref LL_EXTI_LINE_18
- * @arg @ref LL_EXTI_LINE_19
- * @note Please check each device line mapping for EXTI Line availability
- * @retval None
- */
-__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
-{
- WRITE_REG(EXTI->PR, ExtiLine);
-}
-
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-uint32_t LL_EXTI_DeInit(void);
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* EXTI */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_EXTI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h
deleted file mode 100644
index 69e5025d401c10aeb80b9933ad52f04c40d87fd9..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_gpio.h
+++ /dev/null
@@ -1,2377 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_gpio.h
- * @author MCD Application Team
- * @brief Header file of GPIO LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_GPIO_H
-#define __STM32F1xx_LL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
-
-/** @defgroup GPIO_LL GPIO
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-
-/** @defgroup GPIO_LL_Private_Constants GPIO Private Constants
- * @{
- */
-/* Defines used for Pin Mask Initialization */
-#define GPIO_PIN_MASK_POS 8U
-#define GPIO_PIN_NB 16U
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
- * @{
- */
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
- * @{
- */
-
-/**
- * @brief LL GPIO Init Structure definition
- */
-typedef struct
-{
- uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_LL_EC_PIN */
-
- uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_MODE.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
-
- uint32_t Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_SPEED.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
-
- uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
-
- uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
- This parameter can be a value of @ref GPIO_LL_EC_PULL.
-
- GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
-} LL_GPIO_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
- * @{
- */
-
-/** @defgroup GPIO_LL_EC_PIN PIN
- * @{
- */
-#define LL_GPIO_PIN_0 ((GPIO_BSRR_BS0 << GPIO_PIN_MASK_POS) | 0x00000001U) /*!< Select pin 0 */
-#define LL_GPIO_PIN_1 ((GPIO_BSRR_BS1 << GPIO_PIN_MASK_POS) | 0x00000002U) /*!< Select pin 1 */
-#define LL_GPIO_PIN_2 ((GPIO_BSRR_BS2 << GPIO_PIN_MASK_POS) | 0x00000004U) /*!< Select pin 2 */
-#define LL_GPIO_PIN_3 ((GPIO_BSRR_BS3 << GPIO_PIN_MASK_POS) | 0x00000008U) /*!< Select pin 3 */
-#define LL_GPIO_PIN_4 ((GPIO_BSRR_BS4 << GPIO_PIN_MASK_POS) | 0x00000010U) /*!< Select pin 4 */
-#define LL_GPIO_PIN_5 ((GPIO_BSRR_BS5 << GPIO_PIN_MASK_POS) | 0x00000020U) /*!< Select pin 5 */
-#define LL_GPIO_PIN_6 ((GPIO_BSRR_BS6 << GPIO_PIN_MASK_POS) | 0x00000040U) /*!< Select pin 6 */
-#define LL_GPIO_PIN_7 ((GPIO_BSRR_BS7 << GPIO_PIN_MASK_POS) | 0x00000080U) /*!< Select pin 7 */
-#define LL_GPIO_PIN_8 ((GPIO_BSRR_BS8 << GPIO_PIN_MASK_POS) | 0x04000001U) /*!< Select pin 8 */
-#define LL_GPIO_PIN_9 ((GPIO_BSRR_BS9 << GPIO_PIN_MASK_POS) | 0x04000002U) /*!< Select pin 9 */
-#define LL_GPIO_PIN_10 ((GPIO_BSRR_BS10 << GPIO_PIN_MASK_POS) | 0x04000004U) /*!< Select pin 10 */
-#define LL_GPIO_PIN_11 ((GPIO_BSRR_BS11 << GPIO_PIN_MASK_POS) | 0x04000008U) /*!< Select pin 11 */
-#define LL_GPIO_PIN_12 ((GPIO_BSRR_BS12 << GPIO_PIN_MASK_POS) | 0x04000010U) /*!< Select pin 12 */
-#define LL_GPIO_PIN_13 ((GPIO_BSRR_BS13 << GPIO_PIN_MASK_POS) | 0x04000020U) /*!< Select pin 13 */
-#define LL_GPIO_PIN_14 ((GPIO_BSRR_BS14 << GPIO_PIN_MASK_POS) | 0x04000040U) /*!< Select pin 14 */
-#define LL_GPIO_PIN_15 ((GPIO_BSRR_BS15 << GPIO_PIN_MASK_POS) | 0x04000080U) /*!< Select pin 15 */
-#define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \
- LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \
- LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \
- LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \
- LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \
- LL_GPIO_PIN_15) /*!< Select all pins */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_MODE Mode
- * @{
- */
-#define LL_GPIO_MODE_ANALOG 0x00000000U /*!< Select analog mode */
-#define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /*!< Select floating mode */
-#define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /*!< Select input mode */
-#define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /*!< Select general purpose output mode */
-#define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate function mode */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_OUTPUT Output Type
- * @{
- */
-#define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output type */
-#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /*!< Select open-drain as output type */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_SPEED Output Speed
- * @{
- */
-#define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /*!< Select Output mode, max speed 10 MHz */
-#define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /*!< Select Output mode, max speed 20 MHz */
-#define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /*!< Select Output mode, max speed 50 MHz */
-/**
- * @}
- */
-
-#define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /*!< Select I/O low output speed */
-#define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /*!< Select I/O medium output speed */
-#define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /*!< Select I/O high output speed */
-
-/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
- * @{
- */
-#define LL_GPIO_PULL_DOWN 0x00000000U /*!< Select I/O pull down */
-#define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /*!< Select I/O pull up */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin
- * @{
- */
-
-#define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */
-#define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */
-#define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */
-#define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */
-#define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */
-#define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */
-#define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */
-#define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */
-#define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */
-#define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */
-#define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */
-#define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */
-#define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */
-#define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */
-#define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */
-#define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port
- * @{
- */
-
-#define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */
-#define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */
-#define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */
-#define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */
-#define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT
- * @{
- */
-#define LL_GPIO_AF_EXTI_PORTA 0U /*!< EXTI PORT A */
-#define LL_GPIO_AF_EXTI_PORTB 1U /*!< EXTI PORT B */
-#define LL_GPIO_AF_EXTI_PORTC 2U /*!< EXTI PORT C */
-#define LL_GPIO_AF_EXTI_PORTD 3U /*!< EXTI PORT D */
-#define LL_GPIO_AF_EXTI_PORTE 4U /*!< EXTI PORT E */
-#define LL_GPIO_AF_EXTI_PORTF 5U /*!< EXTI PORT F */
-#define LL_GPIO_AF_EXTI_PORTG 6U /*!< EXTI PORT G */
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE
- * @{
- */
-#define LL_GPIO_AF_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
-#define LL_GPIO_AF_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
-#define LL_GPIO_AF_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
-#define LL_GPIO_AF_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
-#define LL_GPIO_AF_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
-#define LL_GPIO_AF_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
-#define LL_GPIO_AF_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
-#define LL_GPIO_AF_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
-#define LL_GPIO_AF_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
-#define LL_GPIO_AF_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
-#define LL_GPIO_AF_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
-#define LL_GPIO_AF_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
-#define LL_GPIO_AF_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
-#define LL_GPIO_AF_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
-#define LL_GPIO_AF_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
-#define LL_GPIO_AF_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
- * @{
- */
-
-/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in GPIO register
- * @param __INSTANCE__ GPIO Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in GPIO register
- * @param __INSTANCE__ GPIO Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
- * @{
- */
-
-/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
- * @{
- */
-
-/**
- * @brief Configure gpio mode for a dedicated pin on dedicated port.
- * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
- * Alternate function Output.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll CRL CNFy LL_GPIO_SetPinMode
- * @rmtoll CRL MODEy LL_GPIO_SetPinMode
- * @rmtoll CRH CNFy LL_GPIO_SetPinMode
- * @rmtoll CRH MODEy LL_GPIO_SetPinMode
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_GPIO_MODE_ANALOG
- * @arg @ref LL_GPIO_MODE_FLOATING
- * @arg @ref LL_GPIO_MODE_INPUT
- * @arg @ref LL_GPIO_MODE_OUTPUT
- * @arg @ref LL_GPIO_MODE_ALTERNATE
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
-{
- register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
- MODIFY_REG(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U)));
-}
-
-/**
- * @brief Return gpio mode for a dedicated pin on dedicated port.
- * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output,
- * Alternate function Output.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll CRL CNFy LL_GPIO_GetPinMode
- * @rmtoll CRL MODEy LL_GPIO_GetPinMode
- * @rmtoll CRH CNFy LL_GPIO_GetPinMode
- * @rmtoll CRH MODEy LL_GPIO_GetPinMode
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_MODE_ANALOG
- * @arg @ref LL_GPIO_MODE_FLOATING
- * @arg @ref LL_GPIO_MODE_INPUT
- * @arg @ref LL_GPIO_MODE_OUTPUT
- * @arg @ref LL_GPIO_MODE_ALTERNATE
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
- return (READ_BIT(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
-}
-
-/**
- * @brief Configure gpio speed for a dedicated pin on dedicated port.
- * @note I/O speed can be Low, Medium or Fast speed.
- * @note Warning: only one pin can be passed as parameter.
- * @note Refer to datasheet for frequency specifications and the power
- * supply and load conditions for each speed.
- * @rmtoll CRL MODEy LL_GPIO_SetPinSpeed
- * @rmtoll CRH MODEy LL_GPIO_SetPinSpeed
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Speed This parameter can be one of the following values:
- * @arg @ref LL_GPIO_SPEED_FREQ_LOW
- * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
- * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
-{
- register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
- MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)),
- (Speed << (POSITION_VAL(Pin) * 4U)));
-}
-
-/**
- * @brief Return gpio speed for a dedicated pin on dedicated port.
- * @note I/O speed can be Low, Medium, Fast or High speed.
- * @note Warning: only one pin can be passed as parameter.
- * @note Refer to datasheet for frequency specifications and the power
- * supply and load conditions for each speed.
- * @rmtoll CRL MODEy LL_GPIO_GetPinSpeed
- * @rmtoll CRH MODEy LL_GPIO_GetPinSpeed
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_SPEED_FREQ_LOW
- * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
- * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
- return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
-}
-
-/**
- * @brief Configure gpio output type for several pins on dedicated port.
- * @note Output type as to be set when gpio pin is in output or
- * alternate modes. Possible type are Push-pull or Open-drain.
- * @rmtoll CRL MODEy LL_GPIO_SetPinOutputType
- * @rmtoll CRH MODEy LL_GPIO_SetPinOutputType
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @param OutputType This parameter can be one of the following values:
- * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
- * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
-{
- register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
- MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)),
- (OutputType << (POSITION_VAL(Pin) * 4U)));
-}
-
-/**
- * @brief Return gpio output type for several pins on dedicated port.
- * @note Output type as to be set when gpio pin is in output or
- * alternate modes. Possible type are Push-pull or Open-drain.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll CRL MODEy LL_GPIO_GetPinOutputType
- * @rmtoll CRH MODEy LL_GPIO_GetPinOutputType
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
- * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
- return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
-
-}
-
-/**
- * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll ODR ODR LL_GPIO_SetPinPull
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @param Pull This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PULL_DOWN
- * @arg @ref LL_GPIO_PULL_UP
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
-{
- MODIFY_REG(GPIOx->ODR, (Pin >> GPIO_PIN_MASK_POS), Pull << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
-}
-
-/**
- * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
- * @note Warning: only one pin can be passed as parameter.
- * @rmtoll ODR ODR LL_GPIO_GetPinPull
- * @param GPIOx GPIO Port
- * @param Pin This parameter can be one of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_PULL_DOWN
- * @arg @ref LL_GPIO_PULL_UP
- */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
- return (READ_BIT(GPIOx->ODR, (GPIO_ODR_ODR0 << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)))) >> (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)));
-}
-
-/**
- * @brief Lock configuration of several pins for a dedicated port.
- * @note When the lock sequence has been applied on a port bit, the
- * value of this port bit can no longer be modified until the
- * next reset.
- * @note Each lock bit freezes a specific configuration register
- * (control and alternate function registers).
- * @rmtoll LCKR LCKK LL_GPIO_LockPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- __IO uint32_t temp;
- WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
- WRITE_REG(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
- WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
- temp = READ_REG(GPIOx->LCKR);
- (void) temp;
-}
-
-/**
- * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
- * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- return (READ_BIT(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
-}
-
-/**
- * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
- * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
- * @param GPIOx GPIO Port
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
-{
- return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_LL_EF_Data_Access Data Access
- * @{
- */
-
-/**
- * @brief Return full input data register value for a dedicated port.
- * @rmtoll IDR IDy LL_GPIO_ReadInputPort
- * @param GPIOx GPIO Port
- * @retval Input data register value of port
- */
-__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
-{
- return (READ_REG(GPIOx->IDR));
-}
-
-/**
- * @brief Return if input data level for several pins of dedicated port is high or low.
- * @rmtoll IDR IDy LL_GPIO_IsInputPinSet
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- return (READ_BIT(GPIOx->IDR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
-}
-
-/**
- * @brief Write output data register for the port.
- * @rmtoll ODR ODy LL_GPIO_WriteOutputPort
- * @param GPIOx GPIO Port
- * @param PortValue Level value for each pin of the port
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
-{
- WRITE_REG(GPIOx->ODR, PortValue);
-}
-
-/**
- * @brief Return full output data register value for a dedicated port.
- * @rmtoll ODR ODy LL_GPIO_ReadOutputPort
- * @param GPIOx GPIO Port
- * @retval Output data register value of port
- */
-__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
-{
- return (uint32_t)(READ_REG(GPIOx->ODR));
-}
-
-/**
- * @brief Return if input data level for several pins of dedicated port is high or low.
- * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- return (READ_BIT(GPIOx->ODR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
-}
-
-/**
- * @brief Set several pins to high level on dedicated gpio port.
- * @rmtoll BSRR BSy LL_GPIO_SetOutputPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- WRITE_REG(GPIOx->BSRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
-}
-
-/**
- * @brief Set several pins to low level on dedicated gpio port.
- * @rmtoll BRR BRy LL_GPIO_ResetOutputPin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- WRITE_REG(GPIOx->BRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
-}
-
-/**
- * @brief Toggle data value for several pin of dedicated port.
- * @rmtoll ODR ODy LL_GPIO_TogglePin
- * @param GPIOx GPIO Port
- * @param PinMask This parameter can be a combination of the following values:
- * @arg @ref LL_GPIO_PIN_0
- * @arg @ref LL_GPIO_PIN_1
- * @arg @ref LL_GPIO_PIN_2
- * @arg @ref LL_GPIO_PIN_3
- * @arg @ref LL_GPIO_PIN_4
- * @arg @ref LL_GPIO_PIN_5
- * @arg @ref LL_GPIO_PIN_6
- * @arg @ref LL_GPIO_PIN_7
- * @arg @ref LL_GPIO_PIN_8
- * @arg @ref LL_GPIO_PIN_9
- * @arg @ref LL_GPIO_PIN_10
- * @arg @ref LL_GPIO_PIN_11
- * @arg @ref LL_GPIO_PIN_12
- * @arg @ref LL_GPIO_PIN_13
- * @arg @ref LL_GPIO_PIN_14
- * @arg @ref LL_GPIO_PIN_15
- * @arg @ref LL_GPIO_PIN_ALL
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
- WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping
- * @brief This section propose definition to remap the alternate function to some other port/pins.
- * @{
- */
-
-/**
- * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
- * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1
- * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
-}
-
-/**
- * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
- * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1
- * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
-}
-
-/**
- * @brief Check if SPI1 has been remaped or not
- * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP));
-}
-
-/**
- * @brief Enable the remapping of I2C1 alternate function SCL and SDA.
- * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1
- * @note ENABLE: Remap (SCL/PB8, SDA/PB9)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
-}
-
-/**
- * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
- * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1
- * @note DISABLE: No remap (SCL/PB6, SDA/PB7)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
-}
-
-/**
- * @brief Check if I2C1 has been remaped or not
- * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP));
-}
-
-/**
- * @brief Enable the remapping of USART1 alternate function TX and RX.
- * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1
- * @note ENABLE: Remap (TX/PB6, RX/PB7)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
-}
-
-/**
- * @brief Disable the remapping of USART1 alternate function TX and RX.
- * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1
- * @note DISABLE: No remap (TX/PA9, RX/PA10)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
-}
-
-/**
- * @brief Check if USART1 has been remaped or not
- * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP));
-}
-
-/**
- * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
- * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2
- * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
-}
-
-/**
- * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
- * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2
- * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
-}
-
-/**
- * @brief Check if USART2 has been remaped or not
- * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP));
-}
-
-#if defined (AFIO_MAPR_USART3_REMAP)
-/**
- * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
- * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3
- * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP);
-}
-
-/**
- * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
- * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3
- * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP);
-}
-
-/**
- * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
- * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3
- * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP);
-}
-#endif
-
-/**
- * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
- * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1
- * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP);
-}
-
-/**
- * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
- * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1
- * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
- * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1
- * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP);
-}
-
-/**
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2
- * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP);
-}
-
-/**
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2
- * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2);
-}
-
-/**
- * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2
- * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1);
-}
-
-/**
- * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
- * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2
- * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP);
-}
-
-/**
- * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
- * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3
- * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
- * @note TIM3_ETR on PE0 is not re-mapped.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP);
-}
-
-/**
- * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
- * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3
- * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
- * @note TIM3_ETR on PE0 is not re-mapped.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
- * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3
- * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
- * @note TIM3_ETR on PE0 is not re-mapped.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP);
-}
-
-#if defined(AFIO_MAPR_TIM4_REMAP)
-/**
- * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
- * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4
- * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15)
- * @note TIM4_ETR on PE0 is not re-mapped.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
-}
-/**
- * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
- * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4
- * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9)
- * @note TIM4_ETR on PE0 is not re-mapped.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
-}
-
-/**
- * @brief Check if TIM4 has been remaped or not
- * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR_CAN_REMAP_REMAP1)
-
-/**
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
- * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1
- * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1);
-}
-
-/**
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
- * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1
- * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2);
-}
-
-/**
- * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
- * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1
- * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3);
-}
-#endif
-
-/**
- * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
- * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
- * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
- * on 100-pin and 144-pin packages, no need for remapping).
- * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01
- * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
-}
-
-/**
- * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
- * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
- * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available
- * on 100-pin and 144-pin packages, no need for remapping).
- * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01
- * @note DISABLE: No remapping of PD0 and PD1
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
-}
-
-/**
- * @brief Check if PD01 has been remaped or not
- * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP));
-}
-
-#if defined(AFIO_MAPR_TIM5CH4_IREMAP)
-/**
- * @brief Enable the remapping of TIM5CH4.
- * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4
- * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose.
- * @note This function is available only in high density value line devices.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM5CH4.
- * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4
- * @note DISABLE: TIM5_CH4 is connected to PA3
- * @note This function is available only in high density value line devices.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
-}
-
-/**
- * @brief Check if TIM5CH4 has been remaped or not
- * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR_ETH_REMAP)
-/**
- * @brief Enable the remapping of Ethernet MAC connections with the PHY.
- * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH
- * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
-}
-
-/**
- * @brief Disable the remapping of Ethernet MAC connections with the PHY.
- * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH
- * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
-}
-
-/**
- * @brief Check if ETH has been remaped or not
- * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR_CAN2_REMAP)
-
-/**
- * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
- * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2
- * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
-}
-/**
- * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
- * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2
- * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
-}
-
-/**
- * @brief Check if CAN2 has been remaped or not
- * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR_MII_RMII_SEL)
-/**
- * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
- * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII
- * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
-}
-
-/**
- * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
- * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII
- * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
-}
-#endif
-
-#if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
-/**
- * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
- * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ
- * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
-}
-
-/**
- * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
- * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ
- * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
-}
-
-/**
- * @brief Check if ADC1_ETRGINJ has been remaped or not
- * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP)
-/**
- * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
- * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG
- * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
-}
-
-/**
- * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
- * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG
- * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
-}
-
-/**
- * @brief Check if ADC1_ETRGREG has been remaped or not
- * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP)
-
-/**
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
- * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ
- * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
-}
-
-/**
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
- * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ
- * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
-}
-
-/**
- * @brief Check if ADC2_ETRGINJ has been remaped or not
- * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP));
-}
-#endif
-
-#if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP)
-
-/**
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG
- * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
-}
-
-/**
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG
- * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
-}
-
-/**
- * @brief Check if ADC2_ETRGREG has been remaped or not
- * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP));
-}
-#endif
-
-/**
- * @brief Enable the Serial wire JTAG configuration
- * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ
- * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void)
-{
- CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET);
-}
-
-/**
- * @brief Enable the Serial wire JTAG configuration
- * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST
- * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void)
-{
- CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST);
-}
-
-/**
- * @brief Enable the Serial wire JTAG configuration
- * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG
- * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void)
-{
- CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE);
-}
-
-/**
- * @brief Disable the Serial wire JTAG configuration
- * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ
- * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void)
-{
- CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG);
- SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE);
-}
-
-#if defined(AFIO_MAPR_SPI3_REMAP)
-
-/**
- * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
- * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3
- * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12)
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
-}
-
-/**
- * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
- * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3
- * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5).
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
-}
-
-/**
- * @brief Check if SPI3 has been remaped or not
- * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void)
-{
- return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR_TIM2ITR1_IREMAP)
-
-/**
- * @brief Control of TIM2_ITR1 internal mapping.
- * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB
- * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
-}
-
-/**
- * @brief Control of TIM2_ITR1 internal mapping.
- * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH
- * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
-}
-#endif
-
-#if defined(AFIO_MAPR_PTP_PPS_REMAP)
-
-/**
- * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS
- * @note ENABLE: PTP_PPS is output on PB5 pin.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)
-{
- SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
-}
-
-/**
- * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
- * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS
- * @note DISABLE: PTP_PPS not output on PB5 pin.
- * @note This bit is available only in connectivity line devices and is reserved otherwise.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)
-{
- CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM9_REMAP)
-
-/**
- * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2.
- * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9
- * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2.
- * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9
- * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP);
-}
-
-/**
- * @brief Check if TIM9_CH1 and TIM9_CH2 have been remaped or not
- * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM10_REMAP)
-
-/**
- * @brief Enable the remapping of TIM10_CH1.
- * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10
- * @note ENABLE: Remap (TIM10_CH1 on PF6).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM10_CH1.
- * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10
- * @note DISABLE: No remap (TIM10_CH1 on PB8).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP);
-}
-
-/**
- * @brief Check if TIM10_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM11_REMAP)
-/**
- * @brief Enable the remapping of TIM11_CH1.
- * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11
- * @note ENABLE: Remap (TIM11_CH1 on PF7).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM11_CH1.
- * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11
- * @note DISABLE: No remap (TIM11_CH1 on PB9).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP);
-}
-
-/**
- * @brief Check if TIM11_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM13_REMAP)
-
-/**
- * @brief Enable the remapping of TIM13_CH1.
- * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13
- * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM13_CH1.
- * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13
- * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP);
-}
-
-/**
- * @brief Check if TIM13_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM14_REMAP)
-
-/**
- * @brief Enable the remapping of TIM14_CH1.
- * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14
- * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM14_CH1.
- * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14
- * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP);
-}
-
-/**
- * @brief Check if TIM14_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_FSMC_NADV_REMAP)
-
-/**
- * @brief Controls the use of the optional FSMC_NADV signal.
- * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV
- * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
-}
-
-/**
- * @brief Controls the use of the optional FSMC_NADV signal.
- * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV
- * @note CONNECTED: The NADV signal is connected to the output (default).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP);
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM15_REMAP)
-
-/**
- * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2.
- * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15
- * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
-}
-/**
- * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2.
- * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15
- * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP);
-}
-
-/**
- * @brief Check if TIM15_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM16_REMAP)
-
-/**
- * @brief Enable the remapping of TIM16_CH1.
- * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16
- * @note ENABLE: Remap (TIM16_CH1 on PA6).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM16_CH1.
- * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16
- * @note DISABLE: No remap (TIM16_CH1 on PB8).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP);
-}
-
-/**
- * @brief Check if TIM16_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM17_REMAP)
-
-/**
- * @brief Enable the remapping of TIM17_CH1.
- * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17
- * @note ENABLE: Remap (TIM17_CH1 on PA7).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM17_CH1.
- * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17
- * @note DISABLE: No remap (TIM17_CH1 on PB9).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP);
-}
-
-/**
- * @brief Check if TIM17_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_CEC_REMAP)
-
-/**
- * @brief Enable the remapping of CEC.
- * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC
- * @note ENABLE: Remap (CEC on PB10).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
-}
-
-/**
- * @brief Disable the remapping of CEC.
- * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC
- * @note DISABLE: No remap (CEC on PB8).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP);
-}
-
-/**
- * @brief Check if CEC has been remaped or not
- * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM1_DMA_REMAP)
-
-/**
- * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
- * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA
- * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
-}
-
-/**
- * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels.
- * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA
- * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3).
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP);
-}
-
-/**
- * @brief Check if TIM1DMA has been remaped or not
- * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP)
-
-/**
- * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
- * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA
- * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
-}
-
-/**
- * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels.
- * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA
- * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4)
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP);
-}
-
-/**
- * @brief Check if TIM67DACDMA has been remaped or not
- * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_TIM12_REMAP)
-
-/**
- * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2.
- * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12
- * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13).
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
-}
-
-/**
- * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2.
- * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12
- * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5).
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP);
-}
-
-/**
- * @brief Check if TIM12_CH1 has been remaped or not
- * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP));
-}
-#endif
-
-#if defined(AFIO_MAPR2_MISC_REMAP)
-
-/**
- * @brief Miscellaneous features remapping.
- * This bit is set and cleared by software. It controls miscellaneous features.
- * The DMA2 channel 5 interrupt position in the vector table.
- * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
- * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC
- * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is
- * selected as DAC Trigger 3, TIM15 triggers TIM1/3.
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void)
-{
- SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
-}
-
-/**
- * @brief Miscellaneous features remapping.
- * This bit is set and cleared by software. It controls miscellaneous features.
- * The DMA2 channel 5 interrupt position in the vector table.
- * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register).
- * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC
- * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO
- * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3.
- * @note This bit is available only in high density value line devices.
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void)
-{
- CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP);
-}
-
-/**
- * @brief Check if MISC has been remaped or not
- * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void)
-{
- return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP));
-}
-#endif
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration
- * @brief This section propose definition to Configure EVENTOUT Cortex feature .
- * @{
- */
-
-/**
- * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected.
- * @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n
- * EVCR PIN LL_GPIO_AF_ConfigEventout
- * @param LL_GPIO_PortSource This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A
- * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B
- * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C
- * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D
- * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E
- * @param LL_GPIO_PinSource This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14
- * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15
- * @retval None
-*/
-__STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource)
-{
- MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (LL_GPIO_PortSource) | (LL_GPIO_PinSource));
-}
-
-/**
- * @brief Enables the Event Output.
- * @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_EnableEventout(void)
-{
- SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
-}
-
-/**
- * @brief Disables the Event Output.
- * @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_DisableEventout(void)
-{
- CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE);
-}
-
-/**
- * @}
- */
-/** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt
- * @brief This section Configure source input for the EXTI external interrupt .
- * @{
- */
-
-/**
- * @brief Configure source input for the EXTI external interrupt.
- * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n
- * AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n
- * AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n
- * AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource
- * @param Port This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_EXTI_PORTA
- * @arg @ref LL_GPIO_AF_EXTI_PORTB
- * @arg @ref LL_GPIO_AF_EXTI_PORTC
- * @arg @ref LL_GPIO_AF_EXTI_PORTD
- * @arg @ref LL_GPIO_AF_EXTI_PORTE
- * @arg @ref LL_GPIO_AF_EXTI_PORTF
- * @arg @ref LL_GPIO_AF_EXTI_PORTG
- * @param Line This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_EXTI_LINE0
- * @arg @ref LL_GPIO_AF_EXTI_LINE1
- * @arg @ref LL_GPIO_AF_EXTI_LINE2
- * @arg @ref LL_GPIO_AF_EXTI_LINE3
- * @arg @ref LL_GPIO_AF_EXTI_LINE4
- * @arg @ref LL_GPIO_AF_EXTI_LINE5
- * @arg @ref LL_GPIO_AF_EXTI_LINE6
- * @arg @ref LL_GPIO_AF_EXTI_LINE7
- * @arg @ref LL_GPIO_AF_EXTI_LINE8
- * @arg @ref LL_GPIO_AF_EXTI_LINE9
- * @arg @ref LL_GPIO_AF_EXTI_LINE10
- * @arg @ref LL_GPIO_AF_EXTI_LINE11
- * @arg @ref LL_GPIO_AF_EXTI_LINE12
- * @arg @ref LL_GPIO_AF_EXTI_LINE13
- * @arg @ref LL_GPIO_AF_EXTI_LINE14
- * @arg @ref LL_GPIO_AF_EXTI_LINE15
- * @retval None
- */
-__STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line)
-{
- MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
-}
-
-/**
- * @brief Get the configured defined for specific EXTI Line
- * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n
- * AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n
- * AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n
- * AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource
- * @param Line This parameter can be one of the following values:
- * @arg @ref LL_GPIO_AF_EXTI_LINE0
- * @arg @ref LL_GPIO_AF_EXTI_LINE1
- * @arg @ref LL_GPIO_AF_EXTI_LINE2
- * @arg @ref LL_GPIO_AF_EXTI_LINE3
- * @arg @ref LL_GPIO_AF_EXTI_LINE4
- * @arg @ref LL_GPIO_AF_EXTI_LINE5
- * @arg @ref LL_GPIO_AF_EXTI_LINE6
- * @arg @ref LL_GPIO_AF_EXTI_LINE7
- * @arg @ref LL_GPIO_AF_EXTI_LINE8
- * @arg @ref LL_GPIO_AF_EXTI_LINE9
- * @arg @ref LL_GPIO_AF_EXTI_LINE10
- * @arg @ref LL_GPIO_AF_EXTI_LINE11
- * @arg @ref LL_GPIO_AF_EXTI_LINE12
- * @arg @ref LL_GPIO_AF_EXTI_LINE13
- * @arg @ref LL_GPIO_AF_EXTI_LINE14
- * @arg @ref LL_GPIO_AF_EXTI_LINE15
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_GPIO_AF_EXTI_PORTA
- * @arg @ref LL_GPIO_AF_EXTI_PORTB
- * @arg @ref LL_GPIO_AF_EXTI_PORTC
- * @arg @ref LL_GPIO_AF_EXTI_PORTD
- * @arg @ref LL_GPIO_AF_EXTI_PORTE
- * @arg @ref LL_GPIO_AF_EXTI_PORTF
- * @arg @ref LL_GPIO_AF_EXTI_PORTG
- */
-__STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line)
-{
- return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
-void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h
deleted file mode 100644
index aba9146116e97a3f67dd8d06ec3264487d2f635f..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_pwr.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_pwr.h
- * @author MCD Application Team
- * @brief Header file of PWR LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_PWR_H
-#define __STM32F1xx_LL_PWR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
- * @{
- */
-
-/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_PWR_WriteReg function
- * @{
- */
-#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
-#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_PWR_ReadReg function
- * @{
- */
-#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
-#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
-#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
-#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP /*!< Enable WKUP pin 1 */
-/**
- * @}
- */
-
-
-/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
- * @{
- */
-#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
-#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
-#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
- * @{
- */
-#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
-#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
- * @{
- */
-#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
-#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
-#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
-#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
-#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
-#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
-#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
-#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
-/**
- * @}
- */
-/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
- * @{
- */
-#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP) /*!< WKUP pin 1 : PA0 */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
- * @{
- */
-
-/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in PWR register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in PWR register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
- * @{
- */
-
-/** @defgroup PWR_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Enable access to the backup domain
- * @rmtoll CR DBP LL_PWR_EnableBkUpAccess
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
-{
- SET_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
- * @brief Disable access to the backup domain
- * @rmtoll CR DBP LL_PWR_DisableBkUpAccess
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
-{
- CLEAR_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
- * @brief Check if the backup domain is enabled
- * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
-{
- return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
-}
-
-/**
- * @brief Set voltage Regulator mode during deep sleep mode
- * @rmtoll CR LPDS LL_PWR_SetRegulModeDS
- * @param RegulMode This parameter can be one of the following values:
- * @arg @ref LL_PWR_REGU_DSMODE_MAIN
- * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
-{
- MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
-}
-
-/**
- * @brief Get voltage Regulator mode during deep sleep mode
- * @rmtoll CR LPDS LL_PWR_GetRegulModeDS
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_REGU_DSMODE_MAIN
- * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
- */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
-{
- return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
-}
-
-/**
- * @brief Set Power Down mode when CPU enters deepsleep
- * @rmtoll CR PDDS LL_PWR_SetPowerMode\n
- * @rmtoll CR LPDS LL_PWR_SetPowerMode
- * @param PDMode This parameter can be one of the following values:
- * @arg @ref LL_PWR_MODE_STOP_MAINREGU
- * @arg @ref LL_PWR_MODE_STOP_LPREGU
- * @arg @ref LL_PWR_MODE_STANDBY
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
-{
- MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
-}
-
-/**
- * @brief Get Power Down mode when CPU enters deepsleep
- * @rmtoll CR PDDS LL_PWR_GetPowerMode\n
- * @rmtoll CR LPDS LL_PWR_GetPowerMode
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_MODE_STOP_MAINREGU
- * @arg @ref LL_PWR_MODE_STOP_LPREGU
- * @arg @ref LL_PWR_MODE_STANDBY
- */
-__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
-{
- return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
-}
-
-/**
- * @brief Configure the voltage threshold detected by the Power Voltage Detector
- * @rmtoll CR PLS LL_PWR_SetPVDLevel
- * @param PVDLevel This parameter can be one of the following values:
- * @arg @ref LL_PWR_PVDLEVEL_0
- * @arg @ref LL_PWR_PVDLEVEL_1
- * @arg @ref LL_PWR_PVDLEVEL_2
- * @arg @ref LL_PWR_PVDLEVEL_3
- * @arg @ref LL_PWR_PVDLEVEL_4
- * @arg @ref LL_PWR_PVDLEVEL_5
- * @arg @ref LL_PWR_PVDLEVEL_6
- * @arg @ref LL_PWR_PVDLEVEL_7
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
-{
- MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
-}
-
-/**
- * @brief Get the voltage threshold detection
- * @rmtoll CR PLS LL_PWR_GetPVDLevel
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_PWR_PVDLEVEL_0
- * @arg @ref LL_PWR_PVDLEVEL_1
- * @arg @ref LL_PWR_PVDLEVEL_2
- * @arg @ref LL_PWR_PVDLEVEL_3
- * @arg @ref LL_PWR_PVDLEVEL_4
- * @arg @ref LL_PWR_PVDLEVEL_5
- * @arg @ref LL_PWR_PVDLEVEL_6
- * @arg @ref LL_PWR_PVDLEVEL_7
- */
-__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
-{
- return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
-}
-
-/**
- * @brief Enable Power Voltage Detector
- * @rmtoll CR PVDE LL_PWR_EnablePVD
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnablePVD(void)
-{
- SET_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
- * @brief Disable Power Voltage Detector
- * @rmtoll CR PVDE LL_PWR_DisablePVD
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisablePVD(void)
-{
- CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
- * @brief Check if Power Voltage Detector is enabled
- * @rmtoll CR PVDE LL_PWR_IsEnabledPVD
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
-{
- return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
-}
-
-/**
- * @brief Enable the WakeUp PINx functionality
- * @rmtoll CSR EWUP LL_PWR_EnableWakeUpPin
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
-{
- SET_BIT(PWR->CSR, WakeUpPin);
-}
-
-/**
- * @brief Disable the WakeUp PINx functionality
- * @rmtoll CSR EWUP LL_PWR_DisableWakeUpPin
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
-{
- CLEAR_BIT(PWR->CSR, WakeUpPin);
-}
-
-/**
- * @brief Check if the WakeUp PINx functionality is enabled
- * @rmtoll CSR EWUP LL_PWR_IsEnabledWakeUpPin
- * @param WakeUpPin This parameter can be one of the following values:
- * @arg @ref LL_PWR_WAKEUP_PIN1
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
-{
- return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
- * @{
- */
-
-/**
- * @brief Get Wake-up Flag
- * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
-}
-
-/**
- * @brief Get Standby Flag
- * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
-}
-
-/**
- * @brief Indicate whether VDD voltage is below the selected PVD threshold
- * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
-{
- return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
-}
-
-/**
- * @brief Clear Standby Flag
- * @rmtoll CR CSBF LL_PWR_ClearFlag_SB
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
-{
- SET_BIT(PWR->CR, PWR_CR_CSBF);
-}
-
-/**
- * @brief Clear Wake-up Flags
- * @rmtoll CR CWUF LL_PWR_ClearFlag_WU
- * @retval None
- */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
-{
- SET_BIT(PWR->CR, PWR_CR_CWUF);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup PWR_LL_EF_Init De-initialization function
- * @{
- */
-ErrorStatus LL_PWR_DeInit(void);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(PWR) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h
deleted file mode 100644
index 4a2b69078fc4e7da9070e03f5648fddfe337e41b..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_rcc.h
+++ /dev/null
@@ -1,2328 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_rcc.h
- * @author MCD Application Team
- * @brief Header file of RCC LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_RCC_H
-#define __STM32F1xx_LL_RCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Private_Macros RCC Private Macros
- * @{
- */
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Exported_Types RCC Exported Types
- * @{
- */
-
-/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
- * @{
- */
-
-/**
- * @brief RCC Clocks Frequency Structure
- */
-typedef struct
-{
- uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
- uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
- uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
- uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
-} LL_RCC_ClocksTypeDef;
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
- * @{
- */
-
-/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
- * @brief Defines used to adapt values of different oscillators
- * @note These values could be modified in the user environment according to
- * HW set-up.
- * @{
- */
-#if !defined (HSE_VALUE)
-#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
-#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */
-#endif /* HSI_VALUE */
-
-#if !defined (LSE_VALUE)
-#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined (LSI_VALUE)
-#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
-#endif /* LSI_VALUE */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
- * @brief Flags defines which can be used with LL_RCC_WriteReg function
- * @{
- */
-#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
-#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
-#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
-#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
-#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
-#define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /*!< PLL3(PLLI2S) Ready Interrupt Clear */
-#define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /*!< PLL2 Ready Interrupt Clear */
-#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_RCC_ReadReg function
- * @{
- */
-#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
-#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
-#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
-#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
-#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
-#define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /*!< PLL3(PLLI2S) Ready Interrupt flag */
-#define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */
-#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
-#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
-#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
-#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
-#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
-#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
-#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
- * @{
- */
-#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
-#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
-#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
-#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
-#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
-#define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /*!< PLL3(PLLI2S) Ready Interrupt Enable */
-#define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /*!< PLL2 Ready Interrupt Enable */
-/**
- * @}
- */
-
-#if defined(RCC_CFGR2_PREDIV2)
-/** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor
- * @{
- */
-#define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
-#define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
-#define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
-#define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
-#define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
-#define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
-#define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
-#define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
-#define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
-#define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
-#define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
-#define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
-#define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
-#define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
-#define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
-#define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
-/**
- * @}
- */
-
-#endif /* RCC_CFGR2_PREDIV2 */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
- * @{
- */
-#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
- * @{
- */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
- * @{
- */
-#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
-#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
-#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
-#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
-#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
-#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
-#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
- * @{
- */
-#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
-#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
-#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
-#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
-#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
- * @{
- */
-#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
-#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
-#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
-#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
-#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
- * @{
- */
-#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */
-#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */
-#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */
-#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */
-#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/
-#if defined(RCC_CFGR_MCOSEL_PLL2CLK)
-#define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCOSEL_PLL2 /*!< PLL2 clock selected as MCO source*/
-#endif /* RCC_CFGR_MCOSEL_PLL2CLK */
-#if defined(RCC_CFGR_MCOSEL_PLL3CLK_DIV2)
-#define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCOSEL_PLL3_DIV2 /*!< PLLI2S clock divided by 2 selected as MCO source*/
-#endif /* RCC_CFGR_MCOSEL_PLL3CLK_DIV2 */
-#if defined(RCC_CFGR_MCOSEL_EXT_HSE)
-#define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCOSEL_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
-#endif /* RCC_CFGR_MCOSEL_EXT_HSE */
-#if defined(RCC_CFGR_MCOSEL_PLL3CLK)
-#define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCOSEL_PLL3CLK /*!< PLLI2S clock selected as MCO source */
-#endif /* RCC_CFGR_MCOSEL_PLL3CLK */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
- * @{
- */
-#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
-#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-#if defined(RCC_CFGR2_I2S2SRC)
-/** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection
- * @{
- */
-#define LL_RCC_I2S2_CLKSOURCE_SYSCLK RCC_CFGR2_I2S2SRC /*!< System clock (SYSCLK) selected as I2S2 clock entry */
-#define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC | (RCC_CFGR2_I2S2SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S2 clock entry */
-#define LL_RCC_I2S3_CLKSOURCE_SYSCLK RCC_CFGR2_I2S3SRC /*!< System clock (SYSCLK) selected as I2S3 clock entry */
-#define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC | (RCC_CFGR2_I2S3SRC >> 16U)) /*!< PLLI2S VCO clock selected as I2S3 clock entry */
-/**
- * @}
- */
-#endif /* RCC_CFGR2_I2S2SRC */
-
-#if defined(USB_OTG_FS) || defined(USB)
-/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
- * @{
- */
-#if defined(RCC_CFGR_USBPRE)
-#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */
-#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.5 */
-#endif /*RCC_CFGR_USBPRE*/
-#if defined(RCC_CFGR_OTGFSPRE)
-#define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */
-#define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3 */
-#endif /*RCC_CFGR_OTGFSPRE*/
-/**
- * @}
- */
-#endif /* USB_OTG_FS || USB */
-
-/** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection
- * @{
- */
-#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*ADC prescaler PCLK2 divided by 2*/
-#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*ADC prescaler PCLK2 divided by 4*/
-#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*ADC prescaler PCLK2 divided by 6*/
-#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*ADC prescaler PCLK2 divided by 8*/
-/**
- * @}
- */
-
-#if defined(RCC_CFGR2_I2S2SRC)
-/** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source
- * @{
- */
-#define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /*!< I2S2 Clock source selection */
-#define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /*!< I2S3 Clock source selection */
-/**
- * @}
- */
-
-#endif /* RCC_CFGR2_I2S2SRC */
-
-#if defined(USB_OTG_FS) || defined(USB)
-/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
- * @{
- */
-#define LL_RCC_USB_CLKSOURCE 0x00400000U /*!< USB Clock source selection */
-/**
- * @}
- */
-
-#endif /* USB_OTG_FS || USB */
-
-/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
- * @{
- */
-#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
- * @{
- */
-#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
- * @{
- */
-#if defined(RCC_CFGR_PLLMULL2)
-#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /*!< PLL input clock*2 */
-#endif /*RCC_CFGR_PLLMULL2*/
-#if defined(RCC_CFGR_PLLMULL3)
-#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /*!< PLL input clock*3 */
-#endif /*RCC_CFGR_PLLMULL3*/
-#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /*!< PLL input clock*4 */
-#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /*!< PLL input clock*5 */
-#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /*!< PLL input clock*6 */
-#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /*!< PLL input clock*7 */
-#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /*!< PLL input clock*8 */
-#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /*!< PLL input clock*9 */
-#if defined(RCC_CFGR_PLLMULL6_5)
-#define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /*!< PLL input clock*6 */
-#else
-#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /*!< PLL input clock*10 */
-#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /*!< PLL input clock*11 */
-#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /*!< PLL input clock*12 */
-#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /*!< PLL input clock*13 */
-#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /*!< PLL input clock*14 */
-#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /*!< PLL input clock*15 */
-#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /*!< PLL input clock*16 */
-#endif /*RCC_CFGR_PLLMULL6_5*/
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
- * @{
- */
-#define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE/PREDIV1 clock selected as PLL entry clock source */
-#if defined(RCC_CFGR2_PREDIV1SRC)
-#define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/PREDIV1 clock selected as PLL entry clock source */
-#endif /*RCC_CFGR2_PREDIV1SRC*/
-
-#if defined(RCC_CFGR2_PREDIV1)
-#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1) /*!< HSE/1 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */
-#if defined(RCC_CFGR2_PREDIV1SRC)
-#define LL_RCC_PLLSOURCE_PLL2_DIV_1 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV1 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/1 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV2 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/2 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV3 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/3 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV4 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/4 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV5 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/5 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV6 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/6 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV7 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/7 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV8 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/8 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV9 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/9 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV10 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/10 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV11 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/11 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV12 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/12 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV13 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/13 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV14 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/14 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV15 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/15 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC | RCC_CFGR2_PREDIV1_DIV16 | RCC_CFGR2_PREDIV1SRC << 4U) /*!< PLL2/16 clock selected as PLL entry clock source */
-#endif /*RCC_CFGR2_PREDIV1SRC*/
-#else
-#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC | 0x00000000U) /*!< HSE/1 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE) /*!< HSE/2 clock selected as PLL entry clock source */
-#endif /*RCC_CFGR2_PREDIV1*/
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
- * @{
- */
-#if defined(RCC_CFGR2_PREDIV1)
-#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /*!< PREDIV1 input clock not divided */
-#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /*!< PREDIV1 input clock divided by 2 */
-#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /*!< PREDIV1 input clock divided by 3 */
-#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /*!< PREDIV1 input clock divided by 4 */
-#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /*!< PREDIV1 input clock divided by 5 */
-#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /*!< PREDIV1 input clock divided by 6 */
-#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /*!< PREDIV1 input clock divided by 7 */
-#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /*!< PREDIV1 input clock divided by 8 */
-#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /*!< PREDIV1 input clock divided by 9 */
-#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /*!< PREDIV1 input clock divided by 10 */
-#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /*!< PREDIV1 input clock divided by 11 */
-#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /*!< PREDIV1 input clock divided by 12 */
-#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /*!< PREDIV1 input clock divided by 13 */
-#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /*!< PREDIV1 input clock divided by 14 */
-#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /*!< PREDIV1 input clock divided by 15 */
-#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /*!< PREDIV1 input clock divided by 16 */
-#else
-#define LL_RCC_PREDIV_DIV_1 0x00000000U /*!< HSE divider clock clock not divided */
-#define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /*!< HSE divider clock divided by 2 for PLL entry */
-#endif /*RCC_CFGR2_PREDIV1*/
-/**
- * @}
- */
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL
- * @{
- */
-#define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
-#define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
-#define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
-#define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
-#define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
-#define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
-#define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
-#define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
-#define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
-/**
- * @}
- */
-
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL
- * @{
- */
-#define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
-#define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
-#define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
-#define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
-#define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
-#define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
-#define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
-#define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
-#define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
-/**
- * @}
- */
-
-#endif /* RCC_PLL2_SUPPORT */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
- * @{
- */
-
-/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in RCC register
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in RCC register
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
- * @{
- */
-
-#if defined(RCC_CFGR_PLLMULL6_5)
-/**
- * @brief Helper macro to calculate the PLLCLK frequency
- * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
- * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1)
- * @param __PLLMUL__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLL_MUL_4
- * @arg @ref LL_RCC_PLL_MUL_5
- * @arg @ref LL_RCC_PLL_MUL_6
- * @arg @ref LL_RCC_PLL_MUL_7
- * @arg @ref LL_RCC_PLL_MUL_8
- * @arg @ref LL_RCC_PLL_MUL_9
- * @arg @ref LL_RCC_PLL_MUL_6_5
- * @retval PLL clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
- (((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \
- ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)) :\
- (((__INPUTFREQ__) * 13U) / 2U))
-
-#else
-/**
- * @brief Helper macro to calculate the PLLCLK frequency
- * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ());
- * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2)
- * @param __PLLMUL__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLL_MUL_2
- * @arg @ref LL_RCC_PLL_MUL_3
- * @arg @ref LL_RCC_PLL_MUL_4
- * @arg @ref LL_RCC_PLL_MUL_5
- * @arg @ref LL_RCC_PLL_MUL_6
- * @arg @ref LL_RCC_PLL_MUL_7
- * @arg @ref LL_RCC_PLL_MUL_8
- * @arg @ref LL_RCC_PLL_MUL_9
- * @arg @ref LL_RCC_PLL_MUL_10
- * @arg @ref LL_RCC_PLL_MUL_11
- * @arg @ref LL_RCC_PLL_MUL_12
- * @arg @ref LL_RCC_PLL_MUL_13
- * @arg @ref LL_RCC_PLL_MUL_14
- * @arg @ref LL_RCC_PLL_MUL_15
- * @arg @ref LL_RCC_PLL_MUL_16
- * @retval PLL clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U))
-#endif /* RCC_CFGR_PLLMULL6_5 */
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
- * @brief Helper macro to calculate the PLLI2S frequency
- * @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
- * @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value)
- * @param __PLLI2SMUL__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLI2S_MUL_8
- * @arg @ref LL_RCC_PLLI2S_MUL_9
- * @arg @ref LL_RCC_PLLI2S_MUL_10
- * @arg @ref LL_RCC_PLLI2S_MUL_11
- * @arg @ref LL_RCC_PLLI2S_MUL_12
- * @arg @ref LL_RCC_PLLI2S_MUL_13
- * @arg @ref LL_RCC_PLLI2S_MUL_14
- * @arg @ref LL_RCC_PLLI2S_MUL_16
- * @arg @ref LL_RCC_PLLI2S_MUL_20
- * @param __PLLI2SDIV__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
- * @retval PLLI2S clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> RCC_CFGR2_PLL3MUL_Pos) + 2U)) / (((__PLLI2SDIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/**
- * @brief Helper macro to calculate the PLL2 frequency
- * @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
- * @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value)
- * @param __PLL2MUL__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLL2_MUL_8
- * @arg @ref LL_RCC_PLL2_MUL_9
- * @arg @ref LL_RCC_PLL2_MUL_10
- * @arg @ref LL_RCC_PLL2_MUL_11
- * @arg @ref LL_RCC_PLL2_MUL_12
- * @arg @ref LL_RCC_PLL2_MUL_13
- * @arg @ref LL_RCC_PLL2_MUL_14
- * @arg @ref LL_RCC_PLL2_MUL_16
- * @arg @ref LL_RCC_PLL2_MUL_20
- * @param __PLL2DIV__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
- * @retval PLL2 clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> RCC_CFGR2_PLL2MUL_Pos) + 2U)) / (((__PLL2DIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
-#endif /* RCC_PLL2_SUPPORT */
-
-/**
- * @brief Helper macro to calculate the HCLK frequency
- * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
- * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
- * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
- * @param __AHBPRESCALER__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- * @retval HCLK clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
-
-/**
- * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
- * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
- * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
- * @param __HCLKFREQ__ HCLK frequency
- * @param __APB1PRESCALER__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- * @retval PCLK1 clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
-
-/**
- * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
- * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
- * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
- * @param __HCLKFREQ__ HCLK frequency
- * @param __APB2PRESCALER__: This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- * @retval PCLK2 clock frequency (in Hz)
- */
-#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
- * @{
- */
-
-/** @defgroup RCC_LL_EF_HSE HSE
- * @{
- */
-
-/**
- * @brief Enable the Clock Security System.
- * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
-{
- SET_BIT(RCC->CR, RCC_CR_CSSON);
-}
-
-/**
- * @brief Enable HSE external oscillator (HSE Bypass)
- * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
-{
- SET_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
- * @brief Disable HSE external oscillator (HSE Bypass)
- * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
- * @brief Enable HSE crystal oscillator (HSE ON)
- * @rmtoll CR HSEON LL_RCC_HSE_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
- * @brief Disable HSE crystal oscillator (HSE ON)
- * @rmtoll CR HSEON LL_RCC_HSE_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSE_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
- * @brief Check if HSE oscillator Ready
- * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
-}
-
-#if defined(RCC_CFGR2_PREDIV2)
-/**
- * @brief Get PREDIV2 division factor
- * @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
- */
-__STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2));
-}
-#endif /* RCC_CFGR2_PREDIV2 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_HSI HSI
- * @{
- */
-
-/**
- * @brief Enable HSI oscillator
- * @rmtoll CR HSION LL_RCC_HSI_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
- * @brief Disable HSI oscillator
- * @rmtoll CR HSION LL_RCC_HSI_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
- * @brief Check if HSI clock is ready
- * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
-}
-
-/**
- * @brief Get HSI Calibration value
- * @note When HSITRIM is written, HSICAL is updated with the sum of
- * HSITRIM and the factory trim value
- * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
- * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
-{
- return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
-}
-
-/**
- * @brief Set HSI Calibration trimming
- * @note user-programmable trimming value that is added to the HSICAL
- * @note Default value is 16, which, when added to the HSICAL value,
- * should trim the HSI to 16 MHz +/- 1 %
- * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
- * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
-{
- MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
-}
-
-/**
- * @brief Get HSI Calibration trimming
- * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
- * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
- */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
-{
- return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_LSE LSE
- * @{
- */
-
-/**
- * @brief Enable Low Speed External (LSE) crystal.
- * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_Enable(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
- * @brief Disable Low Speed External (LSE) crystal.
- * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_Disable(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
- * @brief Enable external clock source (LSE bypass).
- * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
- * @brief Disable external clock source (LSE bypass).
- * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
- * @brief Check if LSE oscillator Ready
- * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
-{
- return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_LSI LSI
- * @{
- */
-
-/**
- * @brief Enable LSI Oscillator
- * @rmtoll CSR LSION LL_RCC_LSI_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSI_Enable(void)
-{
- SET_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
- * @brief Disable LSI Oscillator
- * @rmtoll CSR LSION LL_RCC_LSI_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_LSI_Disable(void)
-{
- CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
- * @brief Check if LSI is Ready
- * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_System System
- * @{
- */
-
-/**
- * @brief Configure the system clock source
- * @rmtoll CFGR SW LL_RCC_SetSysClkSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
- * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
- * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
-}
-
-/**
- * @brief Get the system clock source
- * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
- * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
- */
-__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
-}
-
-/**
- * @brief Set AHB prescaler
- * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
-}
-
-/**
- * @brief Set APB1 prescaler
- * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
-}
-
-/**
- * @brief Set APB2 prescaler
- * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
- * @param Prescaler This parameter can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
-}
-
-/**
- * @brief Get AHB prescaler
- * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_SYSCLK_DIV_1
- * @arg @ref LL_RCC_SYSCLK_DIV_2
- * @arg @ref LL_RCC_SYSCLK_DIV_4
- * @arg @ref LL_RCC_SYSCLK_DIV_8
- * @arg @ref LL_RCC_SYSCLK_DIV_16
- * @arg @ref LL_RCC_SYSCLK_DIV_64
- * @arg @ref LL_RCC_SYSCLK_DIV_128
- * @arg @ref LL_RCC_SYSCLK_DIV_256
- * @arg @ref LL_RCC_SYSCLK_DIV_512
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
-}
-
-/**
- * @brief Get APB1 prescaler
- * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_APB1_DIV_1
- * @arg @ref LL_RCC_APB1_DIV_2
- * @arg @ref LL_RCC_APB1_DIV_4
- * @arg @ref LL_RCC_APB1_DIV_8
- * @arg @ref LL_RCC_APB1_DIV_16
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
-}
-
-/**
- * @brief Get APB2 prescaler
- * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_APB2_DIV_1
- * @arg @ref LL_RCC_APB2_DIV_2
- * @arg @ref LL_RCC_APB2_DIV_4
- * @arg @ref LL_RCC_APB2_DIV_8
- * @arg @ref LL_RCC_APB2_DIV_16
- */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_MCO MCO
- * @{
- */
-
-/**
- * @brief Configure MCOx
- * @rmtoll CFGR MCO LL_RCC_ConfigMCO
- * @param MCOxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
- * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
- * @arg @ref LL_RCC_MCO1SOURCE_HSI
- * @arg @ref LL_RCC_MCO1SOURCE_HSE
- * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
- * @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*)
- * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*)
- * @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*)
- * @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*)
- *
- * (*) value not defined in all devices
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
- * @{
- */
-
-#if defined(RCC_CFGR2_I2S2SRC)
-/**
- * @brief Configure I2Sx clock source
- * @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n
- * CFGR2 I2S3SRC LL_RCC_SetI2SClockSource
- * @param I2SxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
- * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
-{
- MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U));
-}
-#endif /* RCC_CFGR2_I2S2SRC */
-
-#if defined(USB_OTG_FS) || defined(USB)
-/**
- * @brief Configure USB clock source
- * @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n
- * CFGR USBPRE LL_RCC_SetUSBClockSource
- * @param USBxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
- *
- * (*) value not defined in all devices
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
-{
-#if defined(RCC_CFGR_USBPRE)
- MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
-#else /*RCC_CFGR_OTGFSPRE*/
- MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource);
-#endif /*RCC_CFGR_USBPRE*/
-}
-#endif /* USB_OTG_FS || USB */
-
-/**
- * @brief Configure ADC clock source
- * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
- * @param ADCxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
-}
-
-#if defined(RCC_CFGR2_I2S2SRC)
-/**
- * @brief Get I2Sx clock source
- * @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n
- * CFGR2 I2S3SRC LL_RCC_GetI2SClockSource
- * @param I2Sx This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S2_CLKSOURCE
- * @arg @ref LL_RCC_I2S3_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
- * @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
- * @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
- */
-__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U | I2Sx);
-}
-#endif /* RCC_CFGR2_I2S2SRC */
-
-#if defined(USB_OTG_FS) || defined(USB)
-/**
- * @brief Get USBx clock source
- * @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n
- * CFGR USBPRE LL_RCC_GetUSBClockSource
- * @param USBx This parameter can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
- * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
- *
- * (*) value not defined in all devices
- */
-__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
-}
-#endif /* USB_OTG_FS || USB */
-
-/**
- * @brief Get ADCx clock source
- * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
- * @param ADCx This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC_CLKSOURCE
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
- * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
- */
-__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_RTC RTC
- * @{
- */
-
-/**
- * @brief Set RTC Clock Source
- * @note Once the RTC clock source has been selected, it cannot be changed any more unless
- * the Backup domain is reset. The BDRST bit can be used to reset them.
- * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
- * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
-{
- MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
-}
-
-/**
- * @brief Get RTC Clock Source
- * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
- * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
- * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
- */
-__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
-{
- return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
-}
-
-/**
- * @brief Enable RTC
- * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableRTC(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
- * @brief Disable RTC
- * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableRTC(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
- * @brief Check if RTC has been enabled or not
- * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
-{
- return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
-}
-
-/**
- * @brief Force the Backup domain reset
- * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
-{
- SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
- * @brief Release the Backup domain reset
- * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
-{
- CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_PLL PLL
- * @{
- */
-
-/**
- * @brief Enable PLL
- * @rmtoll CR PLLON LL_RCC_PLL_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
- * @brief Disable PLL
- * @note Cannot be disabled if the PLL clock is used as the system clock
- * @rmtoll CR PLLON LL_RCC_PLL_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
- * @brief Check if PLL Ready
- * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
-}
-
-/**
- * @brief Configure PLL used for SYSCLK Domain
- * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
- * CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n
- * CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n
- * CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n
- * CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS
- * @param Source This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*)
- * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_1 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*)
- * @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*)
- *
- * (*) value not defined in all devices
- * @param PLLMul This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLL_MUL_2 (*)
- * @arg @ref LL_RCC_PLL_MUL_3 (*)
- * @arg @ref LL_RCC_PLL_MUL_4
- * @arg @ref LL_RCC_PLL_MUL_5
- * @arg @ref LL_RCC_PLL_MUL_6
- * @arg @ref LL_RCC_PLL_MUL_7
- * @arg @ref LL_RCC_PLL_MUL_8
- * @arg @ref LL_RCC_PLL_MUL_9
- * @arg @ref LL_RCC_PLL_MUL_6_5 (*)
- * @arg @ref LL_RCC_PLL_MUL_10 (*)
- * @arg @ref LL_RCC_PLL_MUL_11 (*)
- * @arg @ref LL_RCC_PLL_MUL_12 (*)
- * @arg @ref LL_RCC_PLL_MUL_13 (*)
- * @arg @ref LL_RCC_PLL_MUL_14 (*)
- * @arg @ref LL_RCC_PLL_MUL_15 (*)
- * @arg @ref LL_RCC_PLL_MUL_16 (*)
- *
- * (*) value not defined in all devices
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
-{
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL,
- (Source & (RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE)) | PLLMul);
-#if defined(RCC_CFGR2_PREDIV1)
-#if defined(RCC_CFGR2_PREDIV1SRC)
- MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC),
- (Source & RCC_CFGR2_PREDIV1) | ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U));
-#else
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1));
-#endif /*RCC_CFGR2_PREDIV1SRC*/
-#endif /*RCC_CFGR2_PREDIV1*/
-}
-
-/**
- * @brief Configure PLL clock source
- * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource\n
- * CFGR2 PREDIV1SRC LL_RCC_PLL_SetMainSource
- * @param PLLSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*)
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
-{
-#if defined(RCC_CFGR2_PREDIV1SRC)
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC, ((PLLSource & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U));
-#endif /* RCC_CFGR2_PREDIV1SRC */
- MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
-}
-
-/**
- * @brief Get the oscillator used as PLL clock source.
- * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource\n
- * CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- * @arg @ref LL_RCC_PLLSOURCE_PLL2 (*)
- *
- * (*) value not defined in all devices
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
-{
-#if defined(RCC_CFGR2_PREDIV1SRC)
- register uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC);
- register uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U);
- return (uint32_t)(pllsrc | predivsrc);
-#else
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
-#endif /*RCC_CFGR2_PREDIV1SRC*/
-}
-
-/**
- * @brief Get PLL multiplication Factor
- * @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLL_MUL_2 (*)
- * @arg @ref LL_RCC_PLL_MUL_3 (*)
- * @arg @ref LL_RCC_PLL_MUL_4
- * @arg @ref LL_RCC_PLL_MUL_5
- * @arg @ref LL_RCC_PLL_MUL_6
- * @arg @ref LL_RCC_PLL_MUL_7
- * @arg @ref LL_RCC_PLL_MUL_8
- * @arg @ref LL_RCC_PLL_MUL_9
- * @arg @ref LL_RCC_PLL_MUL_6_5 (*)
- * @arg @ref LL_RCC_PLL_MUL_10 (*)
- * @arg @ref LL_RCC_PLL_MUL_11 (*)
- * @arg @ref LL_RCC_PLL_MUL_12 (*)
- * @arg @ref LL_RCC_PLL_MUL_13 (*)
- * @arg @ref LL_RCC_PLL_MUL_14 (*)
- * @arg @ref LL_RCC_PLL_MUL_15 (*)
- * @arg @ref LL_RCC_PLL_MUL_16 (*)
- *
- * (*) value not defined in all devices
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL));
-}
-
-/**
- * @brief Get PREDIV1 division factor for the main PLL
- * @note They can be written only when the PLL is disabled
- * @rmtoll CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv\n
- * CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PREDIV_DIV_1
- * @arg @ref LL_RCC_PREDIV_DIV_2
- * @arg @ref LL_RCC_PREDIV_DIV_3 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_4 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_5 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_6 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_7 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_8 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_9 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_10 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_11 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_12 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_13 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_14 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_15 (*)
- * @arg @ref LL_RCC_PREDIV_DIV_16 (*)
- *
- * (*) value not defined in all devices
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
-{
-#if defined(RCC_CFGR2_PREDIV1)
- return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1));
-#else
- return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos);
-#endif /*RCC_CFGR2_PREDIV1*/
-}
-
-/**
- * @}
- */
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
- * @{
- */
-
-/**
- * @brief Enable PLLI2S
- * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_PLL3ON);
-}
-
-/**
- * @brief Disable PLLI2S
- * @rmtoll CR PLL3ON LL_RCC_PLLI2S_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
-}
-
-/**
- * @brief Check if PLLI2S Ready
- * @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY));
-}
-
-/**
- * @brief Configure PLLI2S used for I2S Domain
- * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLLI2S\n
- * CFGR2 PLL3MUL LL_RCC_PLL_ConfigDomain_PLLI2S
- * @param Divider This parameter can be one of the following values:
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
- * @param Multiplicator This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLLI2S_MUL_8
- * @arg @ref LL_RCC_PLLI2S_MUL_9
- * @arg @ref LL_RCC_PLLI2S_MUL_10
- * @arg @ref LL_RCC_PLLI2S_MUL_11
- * @arg @ref LL_RCC_PLLI2S_MUL_12
- * @arg @ref LL_RCC_PLLI2S_MUL_13
- * @arg @ref LL_RCC_PLLI2S_MUL_14
- * @arg @ref LL_RCC_PLLI2S_MUL_16
- * @arg @ref LL_RCC_PLLI2S_MUL_20
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator)
-{
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL3MUL, Divider | Multiplicator);
-}
-
-/**
- * @brief Get PLLI2S Multiplication Factor
- * @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLI2S_MUL_8
- * @arg @ref LL_RCC_PLLI2S_MUL_9
- * @arg @ref LL_RCC_PLLI2S_MUL_10
- * @arg @ref LL_RCC_PLLI2S_MUL_11
- * @arg @ref LL_RCC_PLLI2S_MUL_12
- * @arg @ref LL_RCC_PLLI2S_MUL_13
- * @arg @ref LL_RCC_PLLI2S_MUL_14
- * @arg @ref LL_RCC_PLLI2S_MUL_16
- * @arg @ref LL_RCC_PLLI2S_MUL_20
- */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL));
-}
-
-/**
- * @}
- */
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/** @defgroup RCC_LL_EF_PLL2 PLL2
- * @{
- */
-
-/**
- * @brief Enable PLL2
- * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL2_Enable(void)
-{
- SET_BIT(RCC->CR, RCC_CR_PLL2ON);
-}
-
-/**
- * @brief Disable PLL2
- * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL2_Disable(void)
-{
- CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
-}
-
-/**
- * @brief Check if PLL2 Ready
- * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
-{
- return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY));
-}
-
-/**
- * @brief Configure PLL2 used for PLL2 Domain
- * @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n
- * CFGR2 PLL2MUL LL_RCC_PLL_ConfigDomain_PLL2
- * @param Divider This parameter can be one of the following values:
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
- * @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
- * @param Multiplicator This parameter can be one of the following values:
- * @arg @ref LL_RCC_PLL2_MUL_8
- * @arg @ref LL_RCC_PLL2_MUL_9
- * @arg @ref LL_RCC_PLL2_MUL_10
- * @arg @ref LL_RCC_PLL2_MUL_11
- * @arg @ref LL_RCC_PLL2_MUL_12
- * @arg @ref LL_RCC_PLL2_MUL_13
- * @arg @ref LL_RCC_PLL2_MUL_14
- * @arg @ref LL_RCC_PLL2_MUL_16
- * @arg @ref LL_RCC_PLL2_MUL_20
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator)
-{
- MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL, Divider | Multiplicator);
-}
-
-/**
- * @brief Get PLL2 Multiplication Factor
- * @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLL2_MUL_8
- * @arg @ref LL_RCC_PLL2_MUL_9
- * @arg @ref LL_RCC_PLL2_MUL_10
- * @arg @ref LL_RCC_PLL2_MUL_11
- * @arg @ref LL_RCC_PLL2_MUL_12
- * @arg @ref LL_RCC_PLL2_MUL_13
- * @arg @ref LL_RCC_PLL2_MUL_14
- * @arg @ref LL_RCC_PLL2_MUL_16
- * @arg @ref LL_RCC_PLL2_MUL_20
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void)
-{
- return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL));
-}
-
-/**
- * @}
- */
-#endif /* RCC_PLL2_SUPPORT */
-
-/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
- * @{
- */
-
-/**
- * @brief Clear LSI ready interrupt flag
- * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
-}
-
-/**
- * @brief Clear LSE ready interrupt flag
- * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
-}
-
-/**
- * @brief Clear HSI ready interrupt flag
- * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
-}
-
-/**
- * @brief Clear HSE ready interrupt flag
- * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
-}
-
-/**
- * @brief Clear PLL ready interrupt flag
- * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
- * @brief Clear PLLI2S ready interrupt flag
- * @rmtoll CIR PLL3RDYC LL_RCC_ClearFlag_PLLI2SRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC);
-}
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/**
- * @brief Clear PLL2 ready interrupt flag
- * @rmtoll CIR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC);
-}
-#endif /* RCC_PLL2_SUPPORT */
-
-/**
- * @brief Clear Clock security system interrupt flag
- * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_CSSC);
-}
-
-/**
- * @brief Check if LSI ready interrupt occurred or not
- * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
-}
-
-/**
- * @brief Check if LSE ready interrupt occurred or not
- * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
-}
-
-/**
- * @brief Check if HSI ready interrupt occurred or not
- * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
-}
-
-/**
- * @brief Check if HSE ready interrupt occurred or not
- * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
-}
-
-/**
- * @brief Check if PLL ready interrupt occurred or not
- * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
- * @brief Check if PLLI2S ready interrupt occurred or not
- * @rmtoll CIR PLL3RDYF LL_RCC_IsActiveFlag_PLLI2SRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF));
-}
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/**
- * @brief Check if PLL2 ready interrupt occurred or not
- * @rmtoll CIR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF));
-}
-#endif /* RCC_PLL2_SUPPORT */
-
-/**
- * @brief Check if Clock security system interrupt occurred or not
- * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
-}
-
-/**
- * @brief Check if RCC flag Independent Watchdog reset is set or not.
- * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
-}
-
-/**
- * @brief Check if RCC flag Low Power reset is set or not.
- * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
-}
-
-/**
- * @brief Check if RCC flag Pin reset is set or not.
- * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
-}
-
-/**
- * @brief Check if RCC flag POR/PDR reset is set or not.
- * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
-}
-
-/**
- * @brief Check if RCC flag Software reset is set or not.
- * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
-}
-
-/**
- * @brief Check if RCC flag Window Watchdog reset is set or not.
- * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
-{
- return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
-}
-
-/**
- * @brief Set RMVF bit to clear the reset flags.
- * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
-{
- SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_IT_Management IT Management
- * @{
- */
-
-/**
- * @brief Enable LSI ready interrupt
- * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
-}
-
-/**
- * @brief Enable LSE ready interrupt
- * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
-}
-
-/**
- * @brief Enable HSI ready interrupt
- * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
-}
-
-/**
- * @brief Enable HSE ready interrupt
- * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
-}
-
-/**
- * @brief Enable PLL ready interrupt
- * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
- * @brief Enable PLLI2S ready interrupt
- * @rmtoll CIR PLL3RDYIE LL_RCC_EnableIT_PLLI2SRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
-}
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/**
- * @brief Enable PLL2 ready interrupt
- * @rmtoll CIR PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
-{
- SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
-}
-#endif /* RCC_PLL2_SUPPORT */
-
-/**
- * @brief Disable LSI ready interrupt
- * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
-}
-
-/**
- * @brief Disable LSE ready interrupt
- * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
-}
-
-/**
- * @brief Disable HSI ready interrupt
- * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
-}
-
-/**
- * @brief Disable HSE ready interrupt
- * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
-}
-
-/**
- * @brief Disable PLL ready interrupt
- * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
- * @brief Disable PLLI2S ready interrupt
- * @rmtoll CIR PLL3RDYIE LL_RCC_DisableIT_PLLI2SRDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
-}
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/**
- * @brief Disable PLL2 ready interrupt
- * @rmtoll CIR PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
- * @retval None
- */
-__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
-{
- CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
-}
-#endif /* RCC_PLL2_SUPPORT */
-
-/**
- * @brief Checks if LSI ready interrupt source is enabled or disabled.
- * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
-}
-
-/**
- * @brief Checks if LSE ready interrupt source is enabled or disabled.
- * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
-}
-
-/**
- * @brief Checks if HSI ready interrupt source is enabled or disabled.
- * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
-}
-
-/**
- * @brief Checks if HSE ready interrupt source is enabled or disabled.
- * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
-}
-
-/**
- * @brief Checks if PLL ready interrupt source is enabled or disabled.
- * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
- * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
- * @rmtoll CIR PLL3RDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE));
-}
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLL2_SUPPORT)
-/**
- * @brief Checks if PLL2 ready interrupt source is enabled or disabled.
- * @rmtoll CIR PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
-{
- return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE));
-}
-#endif /* RCC_PLL2_SUPPORT */
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EF_Init De-initialization function
- * @{
- */
-ErrorStatus LL_RCC_DeInit(void);
-/**
- * @}
- */
-
-/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
- * @{
- */
-void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
-#if defined(RCC_CFGR2_I2S2SRC)
-uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
-#endif /* RCC_CFGR2_I2S2SRC */
-#if defined(USB_OTG_FS) || defined(USB)
-uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
-#endif /* USB_OTG_FS || USB */
-uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* RCC */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h
deleted file mode 100644
index d274f04f94de30e40cbceb738a7c6933c82cb8f3..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_spi.h
+++ /dev/null
@@ -1,1920 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_spi.h
- * @author MCD Application Team
- * @brief Header file of SPI LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_SPI_H
-#define __STM32F1xx_LL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (SPI1) || defined (SPI2) || defined (SPI3)
-
-/** @defgroup SPI_LL SPI
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
- * @{
- */
-
-/**
- * @brief SPI Init structures definition
- */
-typedef struct
-{
- uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
- This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
-
- uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
- This parameter can be a value of @ref SPI_LL_EC_MODE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
-
- uint32_t DataWidth; /*!< Specifies the SPI data width.
- This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
-
- uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_LL_EC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
-
- uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_LL_EC_PHASE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
-
- uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
-
- uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
- @note The communication clock is derived from the master clock. The slave clock does not need to be set.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
-
- uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
-
- uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
- This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
-
- This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
-
- uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
- This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
-
- This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
-
-} LL_SPI_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
- * @{
- */
-
-/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_SPI_ReadReg function
- * @{
- */
-#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
-#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
-#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
-#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
-#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
-#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
-#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
- * @{
- */
-#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
-#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
-#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_MODE Operation Mode
- * @{
- */
-#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
-#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
-/**
- * @}
- */
-
-
-/** @defgroup SPI_LL_EC_PHASE Clock Phase
- * @{
- */
-#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
-#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
- * @{
- */
-#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
-#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
- * @{
- */
-#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
-#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
- * @{
- */
-#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
-#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
- * @{
- */
-#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
-#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
-#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
-#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
- * @{
- */
-#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
-#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
-#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
- * @{
- */
-#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */
-#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
- * @{
- */
-#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
-#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
- * @{
- */
-
-/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in SPI register
- * @param __INSTANCE__ SPI Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in SPI register
- * @param __INSTANCE__ SPI Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
- * @{
- */
-
-/** @defgroup SPI_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Enable SPI peripheral
- * @rmtoll CR1 SPE LL_SPI_Enable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
- * @brief Disable SPI peripheral
- * @note When disabling the SPI, follow the procedure described in the Reference Manual.
- * @rmtoll CR1 SPE LL_SPI_Disable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
-}
-
-/**
- * @brief Check if SPI peripheral is enabled
- * @rmtoll CR1 SPE LL_SPI_IsEnabled
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
-}
-
-/**
- * @brief Set SPI operation mode to Master or Slave
- * @note This bit should not be changed when communication is ongoing.
- * @rmtoll CR1 MSTR LL_SPI_SetMode\n
- * CR1 SSI LL_SPI_SetMode
- * @param SPIx SPI Instance
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_SPI_MODE_MASTER
- * @arg @ref LL_SPI_MODE_SLAVE
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
-}
-
-/**
- * @brief Get SPI operation mode (Master or Slave)
- * @rmtoll CR1 MSTR LL_SPI_GetMode\n
- * CR1 SSI LL_SPI_GetMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_MODE_MASTER
- * @arg @ref LL_SPI_MODE_SLAVE
- */
-__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
-}
-
-
-/**
- * @brief Set clock phase
- * @note This bit should not be changed when communication is ongoing.
- * This bit is not used in SPI TI mode.
- * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
- * @param SPIx SPI Instance
- * @param ClockPhase This parameter can be one of the following values:
- * @arg @ref LL_SPI_PHASE_1EDGE
- * @arg @ref LL_SPI_PHASE_2EDGE
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
-}
-
-/**
- * @brief Get clock phase
- * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_PHASE_1EDGE
- * @arg @ref LL_SPI_PHASE_2EDGE
- */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
-}
-
-/**
- * @brief Set clock polarity
- * @note This bit should not be changed when communication is ongoing.
- * This bit is not used in SPI TI mode.
- * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
- * @param SPIx SPI Instance
- * @param ClockPolarity This parameter can be one of the following values:
- * @arg @ref LL_SPI_POLARITY_LOW
- * @arg @ref LL_SPI_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
-}
-
-/**
- * @brief Get clock polarity
- * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_POLARITY_LOW
- * @arg @ref LL_SPI_POLARITY_HIGH
- */
-__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
-}
-
-/**
- * @brief Set baud rate prescaler
- * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
- * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
- * @param SPIx SPI Instance
- * @param BaudRate This parameter can be one of the following values:
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
-}
-
-/**
- * @brief Get baud rate prescaler
- * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
- * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
- */
-__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
-}
-
-/**
- * @brief Set transfer bit order
- * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
- * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
- * @param SPIx SPI Instance
- * @param BitOrder This parameter can be one of the following values:
- * @arg @ref LL_SPI_LSB_FIRST
- * @arg @ref LL_SPI_MSB_FIRST
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
-}
-
-/**
- * @brief Get transfer bit order
- * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_LSB_FIRST
- * @arg @ref LL_SPI_MSB_FIRST
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
-}
-
-/**
- * @brief Set transfer direction mode
- * @note For Half-Duplex mode, Rx Direction is set by default.
- * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
- * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
- * CR1 BIDIMODE LL_SPI_SetTransferDirection\n
- * CR1 BIDIOE LL_SPI_SetTransferDirection
- * @param SPIx SPI Instance
- * @param TransferDirection This parameter can be one of the following values:
- * @arg @ref LL_SPI_FULL_DUPLEX
- * @arg @ref LL_SPI_SIMPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_TX
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
-}
-
-/**
- * @brief Get transfer direction mode
- * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
- * CR1 BIDIMODE LL_SPI_GetTransferDirection\n
- * CR1 BIDIOE LL_SPI_GetTransferDirection
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_FULL_DUPLEX
- * @arg @ref LL_SPI_SIMPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_RX
- * @arg @ref LL_SPI_HALF_DUPLEX_TX
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
-}
-
-/**
- * @brief Set frame data width
- * @rmtoll CR1 DFF LL_SPI_SetDataWidth
- * @param SPIx SPI Instance
- * @param DataWidth This parameter can be one of the following values:
- * @arg @ref LL_SPI_DATAWIDTH_8BIT
- * @arg @ref LL_SPI_DATAWIDTH_16BIT
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
-}
-
-/**
- * @brief Get frame data width
- * @rmtoll CR1 DFF LL_SPI_GetDataWidth
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_DATAWIDTH_8BIT
- * @arg @ref LL_SPI_DATAWIDTH_16BIT
- */
-__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_CRC_Management CRC Management
- * @{
- */
-
-/**
- * @brief Enable CRC
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
- * @brief Disable CRC
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
-}
-
-/**
- * @brief Check if CRC is enabled
- * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
- * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
-}
-
-/**
- * @brief Set CRCNext to transfer CRC on the line
- * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
- * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
-}
-
-/**
- * @brief Set polynomial for CRC calculation
- * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
- * @param SPIx SPI Instance
- * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
-{
- WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
-}
-
-/**
- * @brief Get polynomial for CRC calculation
- * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_REG(SPIx->CRCPR));
-}
-
-/**
- * @brief Get Rx CRC
- * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_REG(SPIx->RXCRCR));
-}
-
-/**
- * @brief Get Tx CRC
- * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
- * @param SPIx SPI Instance
- * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
- */
-__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_REG(SPIx->TXCRCR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
- * @{
- */
-
-/**
- * @brief Set NSS mode
- * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
- * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
- * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
- * @param SPIx SPI Instance
- * @param NSS This parameter can be one of the following values:
- * @arg @ref LL_SPI_NSS_SOFT
- * @arg @ref LL_SPI_NSS_HARD_INPUT
- * @arg @ref LL_SPI_NSS_HARD_OUTPUT
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
-{
- MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
- MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
-}
-
-/**
- * @brief Get NSS mode
- * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
- * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_SPI_NSS_SOFT
- * @arg @ref LL_SPI_NSS_HARD_INPUT
- * @arg @ref LL_SPI_NSS_HARD_OUTPUT
- */
-__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
-{
- register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
- register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
- return (Ssm | Ssoe);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
- * @{
- */
-
-/**
- * @brief Check if Rx buffer is not empty
- * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
-}
-
-/**
- * @brief Check if Tx buffer is empty
- * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
-}
-
-/**
- * @brief Get CRC error flag
- * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
-}
-
-/**
- * @brief Get mode fault error flag
- * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
-}
-
-/**
- * @brief Get overrun error flag
- * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
-}
-
-/**
- * @brief Get busy flag
- * @note The BSY flag is cleared under any one of the following conditions:
- * -When the SPI is correctly disabled
- * -When a fault is detected in Master mode (MODF bit set to 1)
- * -In Master mode, when it finishes a data transmission and no new data is ready to be
- * sent
- * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
- * each data transfer.
- * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
-}
-
-
-/**
- * @brief Clear CRC error flag
- * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
-}
-
-/**
- * @brief Clear mode fault error flag
- * @note Clearing this flag is done by a read access to the SPIx_SR
- * register followed by a write access to the SPIx_CR1 register
- * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
-{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->SR;
- (void) tmpreg;
- tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
- (void) tmpreg;
-}
-
-/**
- * @brief Clear overrun error flag
- * @note Clearing this flag is done by a read access to the SPIx_DR
- * register followed by a read access to the SPIx_SR register
- * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
-{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->DR;
- (void) tmpreg;
- tmpreg = SPIx->SR;
- (void) tmpreg;
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
- * @{
- */
-
-/**
- * @brief Enable error interrupt
- * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
- * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
- * @brief Enable Rx buffer not empty interrupt
- * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
- * @brief Enable Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
- * @brief Disable error interrupt
- * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
- * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
-}
-
-/**
- * @brief Disable Rx buffer not empty interrupt
- * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
-}
-
-/**
- * @brief Disable Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
-}
-
-/**
- * @brief Check if error interrupt is enabled
- * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
-}
-
-/**
- * @brief Check if Rx buffer not empty interrupt is enabled
- * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
-}
-
-/**
- * @brief Check if Tx buffer empty interrupt
- * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_DMA_Management DMA Management
- * @{
- */
-
-/**
- * @brief Enable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
- * @brief Disable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
-}
-
-/**
- * @brief Check if DMA Rx is enabled
- * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
-}
-
-/**
- * @brief Enable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
- * @brief Disable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
-}
-
-/**
- * @brief Check if DMA Tx is enabled
- * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
-}
-
-/**
- * @brief Get the data register address used for DMA transfer
- * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
- * @param SPIx SPI Instance
- * @retval Address of data register
- */
-__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
-{
- return (uint32_t) & (SPIx->DR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EF_DATA_Management DATA Management
- * @{
- */
-
-/**
- * @brief Read 8-Bits in the data register
- * @rmtoll DR DR LL_SPI_ReceiveData8
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
- */
-__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
-{
- return (uint8_t)(READ_REG(SPIx->DR));
-}
-
-/**
- * @brief Read 16-Bits in the data register
- * @rmtoll DR DR LL_SPI_ReceiveData16
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
-{
- return (uint16_t)(READ_REG(SPIx->DR));
-}
-
-/**
- * @brief Write 8-Bits in the data register
- * @rmtoll DR DR LL_SPI_TransmitData8
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
-{
- SPIx->DR = TxData;
-}
-
-/**
- * @brief Write 16-Bits in the data register
- * @rmtoll DR DR LL_SPI_TransmitData16
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
-{
- SPIx->DR = TxData;
-}
-
-/**
- * @}
- */
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
-void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#if defined(SPI_I2S_SUPPORT)
-/** @defgroup I2S_LL I2S
- * @{
- */
-
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
- * @{
- */
-
-/**
- * @brief I2S Init structure definition
- */
-
-typedef struct
-{
- uint32_t Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref I2S_LL_EC_MODE
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
-
- uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref I2S_LL_EC_STANDARD
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
-
-
- uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
-
-
- uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
-
- This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
-
-
- uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
-
- Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
- and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
-
-
- uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref I2S_LL_EC_POLARITY
-
- This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
-
-} LL_I2S_InitTypeDef;
-
-/**
- * @}
- */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
- * @{
- */
-
-/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_I2S_ReadReg function
- * @{
- */
-#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
-#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
-#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
-#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
-#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
-#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
-/**
- * @}
- */
-
-/** @defgroup SPI_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
- * @{
- */
-#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
-#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
-#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
- * @{
- */
-#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */
-#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */
-#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */
-#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
- * @{
- */
-#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
-#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_STANDARD I2s Standard
- * @{
- */
-#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
-#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
-#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
-#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
-#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_MODE Operation Mode
- * @{
- */
-#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
-#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
-#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
-#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
- * @{
- */
-#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
-#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
- * @{
- */
-#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
-#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
- * @{
- */
-
-#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
-#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
-#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
-#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
-#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
-#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
-#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
-#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
-#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
-#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
- * @{
- */
-
-/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-
-/**
- * @brief Write a value in I2S register
- * @param __INSTANCE__ I2S Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in I2S register
- * @param __INSTANCE__ I2S Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
- * @{
- */
-
-/** @defgroup I2S_LL_EF_Configuration Configuration
- * @{
- */
-
-/**
- * @brief Select I2S mode and Enable I2S peripheral
- * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
- * I2SCFGR I2SE LL_I2S_Enable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
- * @brief Disable I2S peripheral
- * @rmtoll I2SCFGR I2SE LL_I2S_Disable
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
-}
-
-/**
- * @brief Check if I2S peripheral is enabled
- * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
-}
-
-/**
- * @brief Set I2S data frame length
- * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
- * I2SCFGR CHLEN LL_I2S_SetDataFormat
- * @param SPIx SPI Instance
- * @param DataFormat This parameter can be one of the following values:
- * @arg @ref LL_I2S_DATAFORMAT_16B
- * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
- * @arg @ref LL_I2S_DATAFORMAT_24B
- * @arg @ref LL_I2S_DATAFORMAT_32B
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
-{
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
-}
-
-/**
- * @brief Get I2S data frame length
- * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
- * I2SCFGR CHLEN LL_I2S_GetDataFormat
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_DATAFORMAT_16B
- * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
- * @arg @ref LL_I2S_DATAFORMAT_24B
- * @arg @ref LL_I2S_DATAFORMAT_32B
- */
-__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
-}
-
-/**
- * @brief Set I2S clock polarity
- * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
- * @param SPIx SPI Instance
- * @param ClockPolarity This parameter can be one of the following values:
- * @arg @ref LL_I2S_POLARITY_LOW
- * @arg @ref LL_I2S_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
-{
- SET_BIT(SPIx->I2SCFGR, ClockPolarity);
-}
-
-/**
- * @brief Get I2S clock polarity
- * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_POLARITY_LOW
- * @arg @ref LL_I2S_POLARITY_HIGH
- */
-__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
-}
-
-/**
- * @brief Set I2S standard protocol
- * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
- * I2SCFGR PCMSYNC LL_I2S_SetStandard
- * @param SPIx SPI Instance
- * @param Standard This parameter can be one of the following values:
- * @arg @ref LL_I2S_STANDARD_PHILIPS
- * @arg @ref LL_I2S_STANDARD_MSB
- * @arg @ref LL_I2S_STANDARD_LSB
- * @arg @ref LL_I2S_STANDARD_PCM_SHORT
- * @arg @ref LL_I2S_STANDARD_PCM_LONG
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
-{
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
-}
-
-/**
- * @brief Get I2S standard protocol
- * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
- * I2SCFGR PCMSYNC LL_I2S_GetStandard
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_STANDARD_PHILIPS
- * @arg @ref LL_I2S_STANDARD_MSB
- * @arg @ref LL_I2S_STANDARD_LSB
- * @arg @ref LL_I2S_STANDARD_PCM_SHORT
- * @arg @ref LL_I2S_STANDARD_PCM_LONG
- */
-__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
-}
-
-/**
- * @brief Set I2S transfer mode
- * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
- * @param SPIx SPI Instance
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_I2S_MODE_SLAVE_TX
- * @arg @ref LL_I2S_MODE_SLAVE_RX
- * @arg @ref LL_I2S_MODE_MASTER_TX
- * @arg @ref LL_I2S_MODE_MASTER_RX
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
-{
- MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
-}
-
-/**
- * @brief Get I2S transfer mode
- * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_MODE_SLAVE_TX
- * @arg @ref LL_I2S_MODE_SLAVE_RX
- * @arg @ref LL_I2S_MODE_MASTER_TX
- * @arg @ref LL_I2S_MODE_MASTER_RX
- */
-__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
-}
-
-/**
- * @brief Set I2S linear prescaler
- * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
- * @param SPIx SPI Instance
- * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
-{
- MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
-}
-
-/**
- * @brief Get I2S linear prescaler
- * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
- * @param SPIx SPI Instance
- * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
- */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
-}
-
-/**
- * @brief Set I2S parity prescaler
- * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
- * @param SPIx SPI Instance
- * @param PrescalerParity This parameter can be one of the following values:
- * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
- * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
-{
- MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
-}
-
-/**
- * @brief Get I2S parity prescaler
- * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
- * @param SPIx SPI Instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
- * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
- */
-__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
-{
- return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
-}
-
-/**
- * @brief Enable the master clock ouput (Pin MCK)
- * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
-{
- SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
- * @brief Disable the master clock ouput (Pin MCK)
- * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
-{
- CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
-}
-
-/**
- * @brief Check if the master clock ouput (Pin MCK) is enabled
- * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_FLAG FLAG Management
- * @{
- */
-
-/**
- * @brief Check if Rx buffer is not empty
- * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_RXNE(SPIx);
-}
-
-/**
- * @brief Check if Tx buffer is empty
- * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_TXE(SPIx);
-}
-
-/**
- * @brief Get busy flag
- * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_BSY(SPIx);
-}
-
-/**
- * @brief Get overrun error flag
- * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsActiveFlag_OVR(SPIx);
-}
-
-/**
- * @brief Get underrun error flag
- * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
-}
-
-/**
- * @brief Get channel side flag.
- * @note 0: Channel Left has to be transmitted or has been received\n
- * 1: Channel Right has to be transmitted or has been received\n
- * It has no significance in PCM mode.
- * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
-{
- return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
-}
-
-/**
- * @brief Clear overrun error flag
- * @rmtoll SR OVR LL_I2S_ClearFlag_OVR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
-{
- LL_SPI_ClearFlag_OVR(SPIx);
-}
-
-/**
- * @brief Clear underrun error flag
- * @rmtoll SR UDR LL_I2S_ClearFlag_UDR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
-{
- __IO uint32_t tmpreg;
- tmpreg = SPIx->SR;
- (void)tmpreg;
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_IT Interrupt Management
- * @{
- */
-
-/**
- * @brief Enable error IT
- * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
- * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableIT_ERR(SPIx);
-}
-
-/**
- * @brief Enable Rx buffer not empty IT
- * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableIT_RXNE(SPIx);
-}
-
-/**
- * @brief Enable Tx buffer empty IT
- * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableIT_TXE(SPIx);
-}
-
-/**
- * @brief Disable error IT
- * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
- * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableIT_ERR(SPIx);
-}
-
-/**
- * @brief Disable Rx buffer not empty IT
- * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableIT_RXNE(SPIx);
-}
-
-/**
- * @brief Disable Tx buffer empty IT
- * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableIT_TXE(SPIx);
-}
-
-/**
- * @brief Check if ERR IT is enabled
- * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledIT_ERR(SPIx);
-}
-
-/**
- * @brief Check if RXNE IT is enabled
- * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledIT_RXNE(SPIx);
-}
-
-/**
- * @brief Check if TXE IT is enabled
- * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledIT_TXE(SPIx);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_DMA DMA Management
- * @{
- */
-
-/**
- * @brief Enable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Disable DMA Rx
- * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Check if DMA Rx is enabled
- * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledDMAReq_RX(SPIx);
-}
-
-/**
- * @brief Enable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- LL_SPI_EnableDMAReq_TX(SPIx);
-}
-
-/**
- * @brief Disable DMA Tx
- * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
- * @param SPIx SPI Instance
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
-{
- LL_SPI_DisableDMAReq_TX(SPIx);
-}
-
-/**
- * @brief Check if DMA Tx is enabled
- * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
- * @param SPIx SPI Instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
-{
- return LL_SPI_IsEnabledDMAReq_TX(SPIx);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2S_LL_EF_DATA DATA Management
- * @{
- */
-
-/**
- * @brief Read 16-Bits in data register
- * @rmtoll DR DR LL_I2S_ReceiveData16
- * @param SPIx SPI Instance
- * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
-{
- return LL_SPI_ReceiveData16(SPIx);
-}
-
-/**
- * @brief Write 16-Bits in data register
- * @rmtoll DR DR LL_I2S_TransmitData16
- * @param SPIx SPI Instance
- * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
- * @retval None
- */
-__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
-{
- LL_SPI_TransmitData16(SPIx, TxData);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
- * @{
- */
-
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
-void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
-void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h
deleted file mode 100644
index f3592bc2b315e9e6bbb1e562d6b6601c79942ac7..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_system.h
+++ /dev/null
@@ -1,590 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_system.h
- * @author MCD Application Team
- * @brief Header file of SYSTEM LL module.
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LL SYSTEM driver contains a set of generic APIs that can be
- used by user:
- (+) Some of the FLASH features need to be handled in the SYSTEM file.
- (+) Access to DBGCMU registers
- (+) Access to SYSCFG registers
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_SYSTEM_H
-#define __STM32F1xx_LL_SYSTEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (FLASH) || defined (DBGMCU)
-
-/** @defgroup SYSTEM_LL SYSTEM
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
- * @{
- */
-
-
-
-/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
- * @{
- */
-#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
-#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
- * @{
- */
-#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
-#if defined(DBGMCU_CR_DBG_TIM5_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM5_STOP */
-#if defined(DBGMCU_CR_DBG_TIM6_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM6_STOP */
-#if defined(DBGMCU_CR_DBG_TIM7_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM7_STOP */
-#if defined(DBGMCU_CR_DBG_TIM12_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM12_STOP */
-#if defined(DBGMCU_CR_DBG_TIM13_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM13_STOP */
-#if defined(DBGMCU_CR_DBG_TIM14_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM14_STOP */
-#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
-#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */
-#if defined(DBGMCU_CR_DBG_CAN1_STOP)
-#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
-#endif /* DBGMCU_CR_DBG_CAN1_STOP */
-#if defined(DBGMCU_CR_DBG_CAN2_STOP)
-#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
-#endif /* DBGMCU_CR_DBG_CAN2_STOP */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
- * @{
- */
-#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
-#if defined(DBGMCU_CR_DBG_TIM8_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_CAN1_STOP */
-#if defined(DBGMCU_CR_DBG_TIM9_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM9_STOP */
-#if defined(DBGMCU_CR_DBG_TIM10_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM10_STOP */
-#if defined(DBGMCU_CR_DBG_TIM11_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM11_STOP */
-#if defined(DBGMCU_CR_DBG_TIM15_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM15_STOP */
-#if defined(DBGMCU_CR_DBG_TIM16_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM16_STOP */
-#if defined(DBGMCU_CR_DBG_TIM17_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
-#endif /* DBGMCU_CR_DBG_TIM17_STOP */
-/**
- * @}
- */
-
-/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
- * @{
- */
-#if defined(FLASH_ACR_LATENCY)
-#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
-#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
-#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
-#else
-#endif /* FLASH_ACR_LATENCY */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
- * @{
- */
-
-
-
-/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
- * @{
- */
-
-/**
- * @brief Return the device identifier
- * @note For Low Density devices, the device ID is 0x412
- * @note For Medium Density devices, the device ID is 0x410
- * @note For High Density devices, the device ID is 0x414
- * @note For XL Density devices, the device ID is 0x430
- * @note For Connectivity Line devices, the device ID is 0x418
- * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
- * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
-{
- return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
-}
-
-/**
- * @brief Return the device revision identifier
- * @note This field indicates the revision of the device.
- For example, it is read as revA -> 0x1000,for Low Density devices
- For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
- For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
- For example, it is read as revA or 1 -> 0x1003,for XL Density devices
- For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
- * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
- * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
-{
- return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
-}
-
-/**
- * @brief Enable the Debug Module during SLEEP mode
- * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Disable the Debug Module during SLEEP mode
- * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Enable the Debug Module during STOP mode
- * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Disable the Debug Module during STOP mode
- * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
- * @brief Enable the Debug Module during STANDBY mode
- * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Disable the Debug Module during STANDBY mode
- * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
- * @brief Set Trace pin assignment control
- * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
- * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
- * @param PinAssignment This parameter can be one of the following values:
- * @arg @ref LL_DBGMCU_TRACE_NONE
- * @arg @ref LL_DBGMCU_TRACE_ASYNCH
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
-{
- MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
-}
-
-/**
- * @brief Get Trace pin assignment control
- * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
- * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_DBGMCU_TRACE_NONE
- * @arg @ref LL_DBGMCU_TRACE_ASYNCH
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
- * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
- */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
-{
- return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
-}
-
-/**
- * @brief Freeze APB1 peripherals (group1 peripherals)
- * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
-{
- SET_BIT(DBGMCU->CR, Periphs);
-}
-
-/**
- * @brief Unfreeze APB1 peripherals (group1 peripherals)
- * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
- * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
- * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
- * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
- CLEAR_BIT(DBGMCU->CR, Periphs);
-}
-
-/**
- * @brief Freeze APB2 peripherals
- * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
-{
- SET_BIT(DBGMCU->CR, Periphs);
-}
-
-/**
- * @brief Unfreeze APB2 peripherals
- * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
- * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
- * @param Periphs This parameter can be a combination of the following values:
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
- * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
- *
- * (*) value not defined in all devices.
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
- CLEAR_BIT(DBGMCU->CR, Periphs);
-}
-/**
- * @}
- */
-
-#if defined(FLASH_ACR_LATENCY)
-/** @defgroup SYSTEM_LL_EF_FLASH FLASH
- * @{
- */
-
-/**
- * @brief Set FLASH Latency
- * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
- * @param Latency This parameter can be one of the following values:
- * @arg @ref LL_FLASH_LATENCY_0
- * @arg @ref LL_FLASH_LATENCY_1
- * @arg @ref LL_FLASH_LATENCY_2
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
-{
- MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
-}
-
-/**
- * @brief Get FLASH Latency
- * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_FLASH_LATENCY_0
- * @arg @ref LL_FLASH_LATENCY_1
- * @arg @ref LL_FLASH_LATENCY_2
- */
-__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
-{
- return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
-}
-
-/**
- * @brief Enable Prefetch
- * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
-{
- SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
-}
-
-/**
- * @brief Disable Prefetch
- * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
-{
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
-}
-
-/**
- * @brief Check if Prefetch buffer is enabled
- * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
-{
- return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
-}
-
-#endif /* FLASH_ACR_LATENCY */
-/**
- * @brief Enable Flash Half Cycle Access
- * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
-{
- SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
-}
-
-/**
- * @brief Disable Flash Half Cycle Access
- * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
- * @retval None
- */
-__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
-{
- CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
-}
-
-/**
- * @brief Check if Flash Half Cycle Access is enabled or not
- * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
-{
- return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (FLASH) || defined (DBGMCU) */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_SYSTEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h
deleted file mode 100644
index 8c84a250eb742bbe3fc332530c0922ced8930dd4..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_tim.h
+++ /dev/null
@@ -1,3838 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_tim.h
- * @author MCD Application Team
- * @brief Header file of TIM LL module.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_TIM_H
-#define __STM32F1xx_LL_TIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
-
-/** @defgroup TIM_LL TIM
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Variables TIM Private Variables
- * @{
- */
-static const uint8_t OFFSET_TAB_CCMRx[] =
-{
- 0x00U, /* 0: TIMx_CH1 */
- 0x00U, /* 1: TIMx_CH1N */
- 0x00U, /* 2: TIMx_CH2 */
- 0x00U, /* 3: TIMx_CH2N */
- 0x04U, /* 4: TIMx_CH3 */
- 0x04U, /* 5: TIMx_CH3N */
- 0x04U /* 6: TIMx_CH4 */
-};
-
-static const uint8_t SHIFT_TAB_OCxx[] =
-{
- 0U, /* 0: OC1M, OC1FE, OC1PE */
- 0U, /* 1: - NA */
- 8U, /* 2: OC2M, OC2FE, OC2PE */
- 0U, /* 3: - NA */
- 0U, /* 4: OC3M, OC3FE, OC3PE */
- 0U, /* 5: - NA */
- 8U /* 6: OC4M, OC4FE, OC4PE */
-};
-
-static const uint8_t SHIFT_TAB_ICxx[] =
-{
- 0U, /* 0: CC1S, IC1PSC, IC1F */
- 0U, /* 1: - NA */
- 8U, /* 2: CC2S, IC2PSC, IC2F */
- 0U, /* 3: - NA */
- 0U, /* 4: CC3S, IC3PSC, IC3F */
- 0U, /* 5: - NA */
- 8U /* 6: CC4S, IC4PSC, IC4F */
-};
-
-static const uint8_t SHIFT_TAB_CCxP[] =
-{
- 0U, /* 0: CC1P */
- 2U, /* 1: CC1NP */
- 4U, /* 2: CC2P */
- 6U, /* 3: CC2NP */
- 8U, /* 4: CC3P */
- 10U, /* 5: CC3NP */
- 12U /* 6: CC4P */
-};
-
-static const uint8_t SHIFT_TAB_OISx[] =
-{
- 0U, /* 0: OIS1 */
- 1U, /* 1: OIS1N */
- 2U, /* 2: OIS2 */
- 3U, /* 3: OIS2N */
- 4U, /* 4: OIS3 */
- 5U, /* 5: OIS3N */
- 6U /* 6: OIS4 */
-};
-/**
- * @}
- */
-
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Constants TIM Private Constants
- * @{
- */
-
-
-
-/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
-#define DT_DELAY_1 ((uint8_t)0x7F)
-#define DT_DELAY_2 ((uint8_t)0x3F)
-#define DT_DELAY_3 ((uint8_t)0x1F)
-#define DT_DELAY_4 ((uint8_t)0x1F)
-
-/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
-#define DT_RANGE_1 ((uint8_t)0x00)
-#define DT_RANGE_2 ((uint8_t)0x80)
-#define DT_RANGE_3 ((uint8_t)0xC0)
-#define DT_RANGE_4 ((uint8_t)0xE0)
-
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Private_Macros TIM Private Macros
- * @{
- */
-/** @brief Convert channel id into channel index.
- * @param __CHANNEL__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval none
- */
-#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
-(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
-((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
-
-/** @brief Calculate the deadtime sampling period(in ps).
- * @param __TIMCLK__ timer input clock frequency (in Hz).
- * @param __CKD__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- * @retval none
- */
-#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
- (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
- ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
- ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
-/**
- * @}
- */
-
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
- * @{
- */
-
-/**
- * @brief TIM Time Base configuration structure definition.
- */
-typedef struct
-{
- uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
-
- uint32_t CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
-
- uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
- Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
-
- uint32_t ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
-
- uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- This parameter must be a number between 0x00 and 0xFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
-} LL_TIM_InitTypeDef;
-
-/**
- * @brief TIM Output Compare configuration structure definition.
- */
-typedef struct
-{
- uint32_t OCMode; /*!< Specifies the output mode.
- This parameter can be a value of @ref TIM_LL_EC_OCMODE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
-
- uint32_t OCState; /*!< Specifies the TIM Output Compare state.
- This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
- This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
- uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
- This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
-
- This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
-
- uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
- This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
-
- This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
-
- uint32_t OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
-
- uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
-
-
- uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
-
- uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
-} LL_TIM_OC_InitTypeDef;
-
-/**
- * @brief TIM Input Capture configuration structure definition.
- */
-
-typedef struct
-{
-
- uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t ICActiveInput; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
-} LL_TIM_IC_InitTypeDef;
-
-
-/**
- * @brief TIM Encoder interface configuration structure definition.
- */
-typedef struct
-{
- uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
- This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
- This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
-
- uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
- This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
-
- uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
-
-} LL_TIM_ENCODER_InitTypeDef;
-
-/**
- * @brief TIM Hall sensor interface configuration structure definition.
- */
-typedef struct
-{
-
- uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
- This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
-
- uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
- Prescaler must be set to get a maximum counter period longer than the
- time interval between 2 consecutive changes on the Hall inputs.
- This parameter can be a value of @ref TIM_LL_EC_ICPSC.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
-
- uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
- This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
-
- uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
- A positive pulse (TRGO event) is generated with a programmable delay every time
- a change occurs on the Hall inputs.
- This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
-} LL_TIM_HALLSENSOR_InitTypeDef;
-
-/**
- * @brief BDTR (Break and Dead Time) structure definition
- */
-typedef struct
-{
- uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
- This parameter can be a value of @ref TIM_LL_EC_OSSR
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
-
- @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
-
- uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
- This parameter can be a value of @ref TIM_LL_EC_OSSI
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
-
- @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
-
- uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
- This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
-
- @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
- has been written, their content is frozen until the next reset.*/
-
- uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
- switching-on of the outputs.
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
-
- @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
-
- uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
- This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
-
- This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
-
- uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
- This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
-
- This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
-
- uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
- This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
-
- This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
-
- @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
-} LL_TIM_BDTR_InitTypeDef;
-
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
- * @{
- */
-
-/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
- * @brief Flags defines which can be used with LL_TIM_ReadReg function.
- * @{
- */
-#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
-#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
-#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
-#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
-#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
-#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
-#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
-#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
-#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
-#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
-#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
-#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
- * @{
- */
-#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
-#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
- * @{
- */
-#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
-#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_IT IT Defines
- * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
- * @{
- */
-#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
-#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
-#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
-#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
-#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
-#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
-#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
-#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
- * @{
- */
-#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
-#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
- * @{
- */
-#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
- * @{
- */
-#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
-#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
-#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
-#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
- * @{
- */
-#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
- * @{
- */
-#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
-#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
- * @{
- */
-#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
-#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
- * @{
- */
-#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
-#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
- * @{
- */
-#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
-#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
-#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
-#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CHANNEL Channel
- * @{
- */
-#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
-#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
-#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
-#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
-#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
-#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
-#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
- * @{
- */
-#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
-#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
- * @{
- */
-#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
-#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
-#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
-#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
-#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
-#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
-#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
-#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
- * @{
- */
-#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
-#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
- * @{
- */
-#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
-#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
-/**
- * @}
- */
-
-
-/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
- * @{
- */
-#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
-#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
-#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
- * @{
- */
-#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
-#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
-#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
-#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
- * @{
- */
-#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
- * @{
- */
-#define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
-#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
- * @{
- */
-#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
-#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
-#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
- * @{
- */
-#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
-#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
-#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TRGO Trigger Output
- * @{
- */
-#define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
-#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
-#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
-#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
-#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
-#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
-/**
- * @}
- */
-
-
-/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
- * @{
- */
-#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
-#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
-#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
-#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_TS Trigger Selection
- * @{
- */
-#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
-#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
-#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
-#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
-#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
-#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
- * @{
- */
-#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
-#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
- * @{
- */
-#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
-#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
-#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
-#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
- * @{
- */
-#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
-/**
- * @}
- */
-
-
-/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
- * @{
- */
-#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
-#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
-/**
- * @}
- */
-
-
-
-
-/** @defgroup TIM_LL_EC_OSSI OSSI
- * @{
- */
-#define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
-#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_OSSR OSSR
- * @{
- */
-#define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
-#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
-/**
- * @}
- */
-
-
-/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
- * @{
- */
-#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
-#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
- * @{
- */
-#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
-#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
-/**
- * @}
- */
-
-
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
- * @{
- */
-
-/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
- * @{
- */
-/**
- * @brief Write a value in TIM register.
- * @param __INSTANCE__ TIM Instance
- * @param __REG__ Register to be written
- * @param __VALUE__ Value to be written in the register
- * @retval None
- */
-#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
- * @brief Read a value in TIM register.
- * @param __INSTANCE__ TIM Instance
- * @param __REG__ Register to be read
- * @retval Register value
- */
-#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
- * @{
- */
-
-/**
- * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
- * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __CKD__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- * @param __DT__ deadtime duration (in ns)
- * @retval DTG[0:7]
- */
-#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
- ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
- (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
- (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
- (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
- 0U)
-
-/**
- * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
- * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __CNTCLK__ counter clock frequency (in Hz)
- * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
- ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
-
-/**
- * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
- * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __FREQ__ output signal frequency (in Hz)
- * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
- (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
-
-/**
- * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
- * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __DELAY__ timer output compare active/inactive delay (in us)
- * @retval Compare value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
-((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
- / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
-
-/**
- * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
- * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
- * @param __TIMCLK__ timer input clock frequency (in Hz)
- * @param __PSC__ prescaler
- * @param __DELAY__ timer output compare active/inactive delay (in us)
- * @param __PULSE__ pulse duration (in us)
- * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
- */
-#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
- ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
- + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
-
-/**
- * @brief HELPER macro retrieving the ratio of the input capture prescaler
- * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
- * @param __ICPSC__ This parameter can be one of the following values:
- * @arg @ref LL_TIM_ICPSC_DIV1
- * @arg @ref LL_TIM_ICPSC_DIV2
- * @arg @ref LL_TIM_ICPSC_DIV4
- * @arg @ref LL_TIM_ICPSC_DIV8
- * @retval Input capture prescaler ratio (1, 2, 4 or 8)
- */
-#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
- ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
-
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
- * @{
- */
-
-/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
- * @{
- */
-/**
- * @brief Enable timer counter.
- * @rmtoll CR1 CEN LL_TIM_EnableCounter
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
- * @brief Disable timer counter.
- * @rmtoll CR1 CEN LL_TIM_DisableCounter
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
-}
-
-/**
- * @brief Indicates whether the timer counter is enabled.
- * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
-}
-
-/**
- * @brief Enable update event generation.
- * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
- * @brief Disable update event generation.
- * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
-}
-
-/**
- * @brief Indicates whether update event generation is enabled.
- * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
-}
-
-/**
- * @brief Set update event source
- * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
- * generate an update interrupt or DMA request if enabled:
- * - Counter overflow/underflow
- * - Setting the UG bit
- * - Update generation through the slave mode controller
- * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
- * overflow/underflow generates an update interrupt or DMA request if enabled.
- * @rmtoll CR1 URS LL_TIM_SetUpdateSource
- * @param TIMx Timer instance
- * @param UpdateSource This parameter can be one of the following values:
- * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
- * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
-{
- MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
-}
-
-/**
- * @brief Get actual event update source
- * @rmtoll CR1 URS LL_TIM_GetUpdateSource
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
- * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
- */
-__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
-}
-
-/**
- * @brief Set one pulse mode (one shot v.s. repetitive).
- * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
- * @param TIMx Timer instance
- * @param OnePulseMode This parameter can be one of the following values:
- * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
- * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
-{
- MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
-}
-
-/**
- * @brief Get actual one pulse mode.
- * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
- * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
- */
-__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
-}
-
-/**
- * @brief Set the timer counter counting mode.
- * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
- * check whether or not the counter mode selection feature is supported
- * by a timer instance.
- * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
- * requires a timer reset to avoid unexpected direction
- * due to DIR bit readonly in center aligned mode.
- * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
- * CR1 CMS LL_TIM_SetCounterMode
- * @param TIMx Timer instance
- * @param CounterMode This parameter can be one of the following values:
- * @arg @ref LL_TIM_COUNTERMODE_UP
- * @arg @ref LL_TIM_COUNTERMODE_DOWN
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
-{
- MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
-}
-
-/**
- * @brief Get actual counter mode.
- * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
- * check whether or not the counter mode selection feature is supported
- * by a timer instance.
- * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
- * CR1 CMS LL_TIM_GetCounterMode
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_COUNTERMODE_UP
- * @arg @ref LL_TIM_COUNTERMODE_DOWN
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
- * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
- */
-__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
-}
-
-/**
- * @brief Enable auto-reload (ARR) preload.
- * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
- * @brief Disable auto-reload (ARR) preload.
- * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
-}
-
-/**
- * @brief Indicates whether auto-reload (ARR) preload is enabled.
- * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
-}
-
-/**
- * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
- * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
- * whether or not the clock division feature is supported by the timer
- * instance.
- * @rmtoll CR1 CKD LL_TIM_SetClockDivision
- * @param TIMx Timer instance
- * @param ClockDivision This parameter can be one of the following values:
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
-{
- MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
-}
-
-/**
- * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
- * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
- * whether or not the clock division feature is supported by the timer
- * instance.
- * @rmtoll CR1 CKD LL_TIM_GetClockDivision
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
- * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
- */
-__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
-}
-
-/**
- * @brief Set the counter value.
- * @rmtoll CNT CNT LL_TIM_SetCounter
- * @param TIMx Timer instance
- * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF)
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
-{
- WRITE_REG(TIMx->CNT, Counter);
-}
-
-/**
- * @brief Get the counter value.
- * @rmtoll CNT CNT LL_TIM_GetCounter
- * @param TIMx Timer instance
- * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF)
- */
-__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CNT));
-}
-
-/**
- * @brief Get the current direction of the counter
- * @rmtoll CR1 DIR LL_TIM_GetDirection
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_COUNTERDIRECTION_UP
- * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
- */
-__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
-}
-
-/**
- * @brief Set the prescaler value.
- * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
- * @note The prescaler can be changed on the fly as this control register is buffered. The new
- * prescaler ratio is taken into account at the next update event.
- * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
- * @rmtoll PSC PSC LL_TIM_SetPrescaler
- * @param TIMx Timer instance
- * @param Prescaler between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
-{
- WRITE_REG(TIMx->PSC, Prescaler);
-}
-
-/**
- * @brief Get the prescaler value.
- * @rmtoll PSC PSC LL_TIM_GetPrescaler
- * @param TIMx Timer instance
- * @retval Prescaler value between Min_Data=0 and Max_Data=65535
- */
-__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->PSC));
-}
-
-/**
- * @brief Set the auto-reload value.
- * @note The counter is blocked while the auto-reload value is null.
- * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
- * @rmtoll ARR ARR LL_TIM_SetAutoReload
- * @param TIMx Timer instance
- * @param AutoReload between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
-{
- WRITE_REG(TIMx->ARR, AutoReload);
-}
-
-/**
- * @brief Get the auto-reload value.
- * @rmtoll ARR ARR LL_TIM_GetAutoReload
- * @param TIMx Timer instance
- * @retval Auto-reload value
- */
-__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->ARR));
-}
-
-/**
- * @brief Set the repetition counter value.
- * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a repetition counter.
- * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
- * @param TIMx Timer instance
- * @param RepetitionCounter between Min_Data=0 and Max_Data=255
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
-{
- WRITE_REG(TIMx->RCR, RepetitionCounter);
-}
-
-/**
- * @brief Get the repetition counter value.
- * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports a repetition counter.
- * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
- * @param TIMx Timer instance
- * @retval Repetition counter value
- */
-__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->RCR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
- * @{
- */
-/**
- * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
- * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
- * they are updated only when a commutation event (COM) occurs.
- * @note Only on channels that have a complementary output.
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance is able to generate a commutation event.
- * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
-}
-
-/**
- * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance is able to generate a commutation event.
- * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
-}
-
-/**
- * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
- * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance is able to generate a commutation event.
- * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
- * @param TIMx Timer instance
- * @param CCUpdateSource This parameter can be one of the following values:
- * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
- * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
-{
- MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
-}
-
-/**
- * @brief Set the trigger of the capture/compare DMA request.
- * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
- * @param TIMx Timer instance
- * @param DMAReqTrigger This parameter can be one of the following values:
- * @arg @ref LL_TIM_CCDMAREQUEST_CC
- * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
-{
- MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
-}
-
-/**
- * @brief Get actual trigger of the capture/compare DMA request.
- * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
- * @param TIMx Timer instance
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_CCDMAREQUEST_CC
- * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
- */
-__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
-}
-
-/**
- * @brief Set the lock level to freeze the
- * configuration of several capture/compare parameters.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * the lock mechanism is supported by a timer instance.
- * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
- * @param TIMx Timer instance
- * @param LockLevel This parameter can be one of the following values:
- * @arg @ref LL_TIM_LOCKLEVEL_OFF
- * @arg @ref LL_TIM_LOCKLEVEL_1
- * @arg @ref LL_TIM_LOCKLEVEL_2
- * @arg @ref LL_TIM_LOCKLEVEL_3
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
-{
- MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
-}
-
-/**
- * @brief Enable capture/compare channels.
- * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
- * CCER CC1NE LL_TIM_CC_EnableChannel\n
- * CCER CC2E LL_TIM_CC_EnableChannel\n
- * CCER CC2NE LL_TIM_CC_EnableChannel\n
- * CCER CC3E LL_TIM_CC_EnableChannel\n
- * CCER CC3NE LL_TIM_CC_EnableChannel\n
- * CCER CC4E LL_TIM_CC_EnableChannel
- * @param TIMx Timer instance
- * @param Channels This parameter can be a combination of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
- SET_BIT(TIMx->CCER, Channels);
-}
-
-/**
- * @brief Disable capture/compare channels.
- * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
- * CCER CC1NE LL_TIM_CC_DisableChannel\n
- * CCER CC2E LL_TIM_CC_DisableChannel\n
- * CCER CC2NE LL_TIM_CC_DisableChannel\n
- * CCER CC3E LL_TIM_CC_DisableChannel\n
- * CCER CC3NE LL_TIM_CC_DisableChannel\n
- * CCER CC4E LL_TIM_CC_DisableChannel
- * @param TIMx Timer instance
- * @param Channels This parameter can be a combination of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
- CLEAR_BIT(TIMx->CCER, Channels);
-}
-
-/**
- * @brief Indicate whether channel(s) is(are) enabled.
- * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
- * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
- * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
- * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
- * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
- * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
- * CCER CC4E LL_TIM_CC_IsEnabledChannel
- * @param TIMx Timer instance
- * @param Channels This parameter can be a combination of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
-{
- return (READ_BIT(TIMx->CCER, Channels) == (Channels));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
- * @{
- */
-/**
- * @brief Configure an output channel.
- * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
- * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
- * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
- * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
- * CCER CC1P LL_TIM_OC_ConfigOutput\n
- * CCER CC2P LL_TIM_OC_ConfigOutput\n
- * CCER CC3P LL_TIM_OC_ConfigOutput\n
- * CCER CC4P LL_TIM_OC_ConfigOutput\n
- * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
- * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
- * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
- * CR2 OIS4 LL_TIM_OC_ConfigOutput
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param Configuration This parameter must be a combination of all the following values:
- * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
- * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
- MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
- (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
- MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
- (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
- * @brief Define the behavior of the output reference signal OCxREF from which
- * OCx and OCxN (when relevant) are derived.
- * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
- * CCMR1 OC2M LL_TIM_OC_SetMode\n
- * CCMR2 OC3M LL_TIM_OC_SetMode\n
- * CCMR2 OC4M LL_TIM_OC_SetMode
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param Mode This parameter can be one of the following values:
- * @arg @ref LL_TIM_OCMODE_FROZEN
- * @arg @ref LL_TIM_OCMODE_ACTIVE
- * @arg @ref LL_TIM_OCMODE_INACTIVE
- * @arg @ref LL_TIM_OCMODE_TOGGLE
- * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
- * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
- * @arg @ref LL_TIM_OCMODE_PWM1
- * @arg @ref LL_TIM_OCMODE_PWM2
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
- * @brief Get the output compare mode of an output channel.
- * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
- * CCMR1 OC2M LL_TIM_OC_GetMode\n
- * CCMR2 OC3M LL_TIM_OC_GetMode\n
- * CCMR2 OC4M LL_TIM_OC_GetMode
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_OCMODE_FROZEN
- * @arg @ref LL_TIM_OCMODE_ACTIVE
- * @arg @ref LL_TIM_OCMODE_INACTIVE
- * @arg @ref LL_TIM_OCMODE_TOGGLE
- * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
- * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
- * @arg @ref LL_TIM_OCMODE_PWM1
- * @arg @ref LL_TIM_OCMODE_PWM2
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
-}
-
-/**
- * @brief Set the polarity of an output channel.
- * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
- * CCER CC1NP LL_TIM_OC_SetPolarity\n
- * CCER CC2P LL_TIM_OC_SetPolarity\n
- * CCER CC2NP LL_TIM_OC_SetPolarity\n
- * CCER CC3P LL_TIM_OC_SetPolarity\n
- * CCER CC3NP LL_TIM_OC_SetPolarity\n
- * CCER CC4P LL_TIM_OC_SetPolarity
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param Polarity This parameter can be one of the following values:
- * @arg @ref LL_TIM_OCPOLARITY_HIGH
- * @arg @ref LL_TIM_OCPOLARITY_LOW
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Get the polarity of an output channel.
- * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
- * CCER CC1NP LL_TIM_OC_GetPolarity\n
- * CCER CC2P LL_TIM_OC_GetPolarity\n
- * CCER CC2NP LL_TIM_OC_GetPolarity\n
- * CCER CC3P LL_TIM_OC_GetPolarity\n
- * CCER CC3NP LL_TIM_OC_GetPolarity\n
- * CCER CC4P LL_TIM_OC_GetPolarity
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_OCPOLARITY_HIGH
- * @arg @ref LL_TIM_OCPOLARITY_LOW
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Set the IDLE state of an output channel
- * @note This function is significant only for the timer instances
- * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
- * can be used to check whether or not a timer instance provides
- * a break input.
- * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
- * CR2 OIS1N LL_TIM_OC_SetIdleState\n
- * CR2 OIS2 LL_TIM_OC_SetIdleState\n
- * CR2 OIS2N LL_TIM_OC_SetIdleState\n
- * CR2 OIS3 LL_TIM_OC_SetIdleState\n
- * CR2 OIS3N LL_TIM_OC_SetIdleState\n
- * CR2 OIS4 LL_TIM_OC_SetIdleState
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param IdleState This parameter can be one of the following values:
- * @arg @ref LL_TIM_OCIDLESTATE_LOW
- * @arg @ref LL_TIM_OCIDLESTATE_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
- * @brief Get the IDLE state of an output channel
- * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
- * CR2 OIS1N LL_TIM_OC_GetIdleState\n
- * CR2 OIS2 LL_TIM_OC_GetIdleState\n
- * CR2 OIS2N LL_TIM_OC_GetIdleState\n
- * CR2 OIS3 LL_TIM_OC_GetIdleState\n
- * CR2 OIS3N LL_TIM_OC_GetIdleState\n
- * CR2 OIS4 LL_TIM_OC_GetIdleState
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH1N
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH2N
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH3N
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_OCIDLESTATE_LOW
- * @arg @ref LL_TIM_OCIDLESTATE_HIGH
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
-}
-
-/**
- * @brief Enable fast mode for the output channel.
- * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
- * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
- * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
- * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
- * CCMR2 OC4FE LL_TIM_OC_EnableFast
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-
-}
-
-/**
- * @brief Disable fast mode for the output channel.
- * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
- * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
- * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
- * CCMR2 OC4FE LL_TIM_OC_DisableFast
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
-
-}
-
-/**
- * @brief Indicates whether fast mode is enabled for the output channel.
- * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
- * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
- * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
- * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
-}
-
-/**
- * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
- * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
- * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
- * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
- * CCMR2 OC4PE LL_TIM_OC_EnablePreload
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
- * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
- * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
- * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
- * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
- * CCMR2 OC4PE LL_TIM_OC_DisablePreload
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
- * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
- * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
- * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
- * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
- * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
-}
-
-/**
- * @brief Enable clearing the output channel on an external event.
- * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance can clear the OCxREF signal on an external event.
- * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
- * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
- * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
- * CCMR2 OC4CE LL_TIM_OC_EnableClear
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
- * @brief Disable clearing the output channel on an external event.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance can clear the OCxREF signal on an external event.
- * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
- * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
- * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
- * CCMR2 OC4CE LL_TIM_OC_DisableClear
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
-}
-
-/**
- * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
- * @note This function enables clearing the output channel on an external event.
- * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
- * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
- * or not a timer instance can clear the OCxREF signal on an external event.
- * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
- * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
- * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
- * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
- return (READ_BIT(*pReg, bitfield) == bitfield);
-}
-
-/**
- * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * dead-time insertion feature is supported by a timer instance.
- * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
- * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
- * @param TIMx Timer instance
- * @param DeadTime between Min_Data=0 and Max_Data=255
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
-{
- MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
-}
-
-/**
- * @brief Set compare value for output channel 1 (TIMx_CCR1).
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
- * output channel 1 is supported by a timer instance.
- * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
- * @param TIMx Timer instance
- * @param CompareValue between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
- WRITE_REG(TIMx->CCR1, CompareValue);
-}
-
-/**
- * @brief Set compare value for output channel 2 (TIMx_CCR2).
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
- * output channel 2 is supported by a timer instance.
- * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
- * @param TIMx Timer instance
- * @param CompareValue between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
- WRITE_REG(TIMx->CCR2, CompareValue);
-}
-
-/**
- * @brief Set compare value for output channel 3 (TIMx_CCR3).
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
- * output channel is supported by a timer instance.
- * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
- * @param TIMx Timer instance
- * @param CompareValue between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
- WRITE_REG(TIMx->CCR3, CompareValue);
-}
-
-/**
- * @brief Set compare value for output channel 4 (TIMx_CCR4).
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
- * output channel 4 is supported by a timer instance.
- * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
- * @param TIMx Timer instance
- * @param CompareValue between Min_Data=0 and Max_Data=65535
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
-{
- WRITE_REG(TIMx->CCR4, CompareValue);
-}
-
-/**
- * @brief Get compare value (TIMx_CCR1) set for output channel 1.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
- * output channel 1 is supported by a timer instance.
- * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
- * @param TIMx Timer instance
- * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
- * @brief Get compare value (TIMx_CCR2) set for output channel 2.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
- * output channel 2 is supported by a timer instance.
- * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
- * @param TIMx Timer instance
- * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
- * @brief Get compare value (TIMx_CCR3) set for output channel 3.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
- * output channel 3 is supported by a timer instance.
- * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
- * @param TIMx Timer instance
- * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
- * @brief Get compare value (TIMx_CCR4) set for output channel 4.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
- * output channel 4 is supported by a timer instance.
- * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
- * @param TIMx Timer instance
- * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
- * @{
- */
-/**
- * @brief Configure input channel.
- * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
- * CCMR1 IC1PSC LL_TIM_IC_Config\n
- * CCMR1 IC1F LL_TIM_IC_Config\n
- * CCMR1 CC2S LL_TIM_IC_Config\n
- * CCMR1 IC2PSC LL_TIM_IC_Config\n
- * CCMR1 IC2F LL_TIM_IC_Config\n
- * CCMR2 CC3S LL_TIM_IC_Config\n
- * CCMR2 IC3PSC LL_TIM_IC_Config\n
- * CCMR2 IC3F LL_TIM_IC_Config\n
- * CCMR2 CC4S LL_TIM_IC_Config\n
- * CCMR2 IC4PSC LL_TIM_IC_Config\n
- * CCMR2 IC4F LL_TIM_IC_Config\n
- * CCER CC1P LL_TIM_IC_Config\n
- * CCER CC1NP LL_TIM_IC_Config\n
- * CCER CC2P LL_TIM_IC_Config\n
- * CCER CC2NP LL_TIM_IC_Config\n
- * CCER CC3P LL_TIM_IC_Config\n
- * CCER CC3NP LL_TIM_IC_Config\n
- * CCER CC4P LL_TIM_IC_Config\n
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param Configuration This parameter must be a combination of all the following values:
- * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
- * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
- * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
- * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
- ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
- MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
- (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Set the active input.
- * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
- * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
- * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
- * CCMR2 CC4S LL_TIM_IC_SetActiveInput
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param ICActiveInput This parameter can be one of the following values:
- * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
- * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
- * @arg @ref LL_TIM_ACTIVEINPUT_TRC
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
- * @brief Get the current active input.
- * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
- * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
- * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
- * CCMR2 CC4S LL_TIM_IC_GetActiveInput
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
- * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
- * @arg @ref LL_TIM_ACTIVEINPUT_TRC
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
- * @brief Set the prescaler of input channel.
- * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
- * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
- * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
- * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param ICPrescaler This parameter can be one of the following values:
- * @arg @ref LL_TIM_ICPSC_DIV1
- * @arg @ref LL_TIM_ICPSC_DIV2
- * @arg @ref LL_TIM_ICPSC_DIV4
- * @arg @ref LL_TIM_ICPSC_DIV8
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
- * @brief Get the current prescaler value acting on an input channel.
- * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
- * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
- * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
- * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_ICPSC_DIV1
- * @arg @ref LL_TIM_ICPSC_DIV2
- * @arg @ref LL_TIM_ICPSC_DIV4
- * @arg @ref LL_TIM_ICPSC_DIV8
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
- * @brief Set the input filter duration.
- * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
- * CCMR1 IC2F LL_TIM_IC_SetFilter\n
- * CCMR2 IC3F LL_TIM_IC_SetFilter\n
- * CCMR2 IC4F LL_TIM_IC_SetFilter
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param ICFilter This parameter can be one of the following values:
- * @arg @ref LL_TIM_IC_FILTER_FDIV1
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
-}
-
-/**
- * @brief Get the input filter duration.
- * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
- * CCMR1 IC2F LL_TIM_IC_GetFilter\n
- * CCMR2 IC3F LL_TIM_IC_GetFilter\n
- * CCMR2 IC4F LL_TIM_IC_GetFilter
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_IC_FILTER_FDIV1
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
- * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
- * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
-}
-
-/**
- * @brief Set the input channel polarity.
- * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
- * CCER CC1NP LL_TIM_IC_SetPolarity\n
- * CCER CC2P LL_TIM_IC_SetPolarity\n
- * CCER CC2NP LL_TIM_IC_SetPolarity\n
- * CCER CC3P LL_TIM_IC_SetPolarity\n
- * CCER CC3NP LL_TIM_IC_SetPolarity\n
- * CCER CC4P LL_TIM_IC_SetPolarity\n
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param ICPolarity This parameter can be one of the following values:
- * @arg @ref LL_TIM_IC_POLARITY_RISING
- * @arg @ref LL_TIM_IC_POLARITY_FALLING
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
- ICPolarity << SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Get the current input channel polarity.
- * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
- * CCER CC1NP LL_TIM_IC_GetPolarity\n
- * CCER CC2P LL_TIM_IC_GetPolarity\n
- * CCER CC2NP LL_TIM_IC_GetPolarity\n
- * CCER CC3P LL_TIM_IC_GetPolarity\n
- * CCER CC3NP LL_TIM_IC_GetPolarity\n
- * CCER CC4P LL_TIM_IC_GetPolarity\n
- * @param TIMx Timer instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_TIM_IC_POLARITY_RISING
- * @arg @ref LL_TIM_IC_POLARITY_FALLING
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
-{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
- SHIFT_TAB_CCxP[iChannel]);
-}
-
-/**
- * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an XOR input.
- * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
- * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an XOR input.
- * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
-}
-
-/**
- * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
- * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an XOR input.
- * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
-}
-
-/**
- * @brief Get captured value for input channel 1.
- * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
- * input channel 1 is supported by a timer instance.
- * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
- * @param TIMx Timer instance
- * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR1));
-}
-
-/**
- * @brief Get captured value for input channel 2.
- * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
- * input channel 2 is supported by a timer instance.
- * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
- * @param TIMx Timer instance
- * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR2));
-}
-
-/**
- * @brief Get captured value for input channel 3.
- * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
- * input channel 3 is supported by a timer instance.
- * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
- * @param TIMx Timer instance
- * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR3));
-}
-
-/**
- * @brief Get captured value for input channel 4.
- * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
- * input channel 4 is supported by a timer instance.
- * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
- * @param TIMx Timer instance
- * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
- */
-__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
-{
- return (uint32_t)(READ_REG(TIMx->CCR4));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
- * @{
- */
-/**
- * @brief Enable external clock mode 2.
- * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode2.
- * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
- * @brief Disable external clock mode 2.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode2.
- * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
-}
-
-/**
- * @brief Indicate whether external clock mode 2 is enabled.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode2.
- * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
-}
-
-/**
- * @brief Set the clock source of the counter clock.
- * @note when selected clock source is external clock mode 1, the timer input
- * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
- * function. This timer input must be configured by calling
- * the @ref LL_TIM_IC_Config() function.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode1.
- * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports external clock mode2.
- * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
- * SMCR ECE LL_TIM_SetClockSource
- * @param TIMx Timer instance
- * @param ClockSource This parameter can be one of the following values:
- * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
- * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
- * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
-{
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
-}
-
-/**
- * @brief Set the encoder interface mode.
- * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance supports the encoder mode.
- * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
- * @param TIMx Timer instance
- * @param EncoderMode This parameter can be one of the following values:
- * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
- * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
- * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
-{
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
- * @{
- */
-/**
- * @brief Set the trigger output (TRGO) used for timer synchronization .
- * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
- * whether or not a timer instance can operate as a master timer.
- * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
- * @param TIMx Timer instance
- * @param TimerSynchronization This parameter can be one of the following values:
- * @arg @ref LL_TIM_TRGO_RESET
- * @arg @ref LL_TIM_TRGO_ENABLE
- * @arg @ref LL_TIM_TRGO_UPDATE
- * @arg @ref LL_TIM_TRGO_CC1IF
- * @arg @ref LL_TIM_TRGO_OC1REF
- * @arg @ref LL_TIM_TRGO_OC2REF
- * @arg @ref LL_TIM_TRGO_OC3REF
- * @arg @ref LL_TIM_TRGO_OC4REF
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
-{
- MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
-}
-
-/**
- * @brief Set the synchronization mode of a slave timer.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
- * @param TIMx Timer instance
- * @param SlaveMode This parameter can be one of the following values:
- * @arg @ref LL_TIM_SLAVEMODE_DISABLED
- * @arg @ref LL_TIM_SLAVEMODE_RESET
- * @arg @ref LL_TIM_SLAVEMODE_GATED
- * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
-{
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
-}
-
-/**
- * @brief Set the selects the trigger input to be used to synchronize the counter.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR TS LL_TIM_SetTriggerInput
- * @param TIMx Timer instance
- * @param TriggerInput This parameter can be one of the following values:
- * @arg @ref LL_TIM_TS_ITR0
- * @arg @ref LL_TIM_TS_ITR1
- * @arg @ref LL_TIM_TS_ITR2
- * @arg @ref LL_TIM_TS_ITR3
- * @arg @ref LL_TIM_TS_TI1F_ED
- * @arg @ref LL_TIM_TS_TI1FP1
- * @arg @ref LL_TIM_TS_TI2FP2
- * @arg @ref LL_TIM_TS_ETRF
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
-{
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
-}
-
-/**
- * @brief Enable the Master/Slave mode.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
- * @brief Disable the Master/Slave mode.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
-}
-
-/**
- * @brief Indicates whether the Master/Slave mode is enabled.
- * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance can operate as a slave timer.
- * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
-}
-
-/**
- * @brief Configure the external trigger (ETR) input.
- * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides an external trigger input.
- * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
- * SMCR ETPS LL_TIM_ConfigETR\n
- * SMCR ETF LL_TIM_ConfigETR
- * @param TIMx Timer instance
- * @param ETRPolarity This parameter can be one of the following values:
- * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
- * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
- * @param ETRPrescaler This parameter can be one of the following values:
- * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
- * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
- * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
- * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
- * @param ETRFilter This parameter can be one of the following values:
- * @arg @ref LL_TIM_ETR_FILTER_FDIV1
- * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
- * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
- * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
- * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
- * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
- * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
- * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
- uint32_t ETRFilter)
-{
- MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_Break_Function Break function configuration
- * @{
- */
-/**
- * @brief Enable the break function.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR BKE LL_TIM_EnableBRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
-}
-
-/**
- * @brief Disable the break function.
- * @rmtoll BDTR BKE LL_TIM_DisableBRK
- * @param TIMx Timer instance
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
-}
-
-/**
- * @brief Configure the break input.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR BKP LL_TIM_ConfigBRK
- * @param TIMx Timer instance
- * @param BreakPolarity This parameter can be one of the following values:
- * @arg @ref LL_TIM_BREAK_POLARITY_LOW
- * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
-{
- MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
-}
-
-/**
- * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
- * BDTR OSSR LL_TIM_SetOffStates
- * @param TIMx Timer instance
- * @param OffStateIdle This parameter can be one of the following values:
- * @arg @ref LL_TIM_OSSI_DISABLE
- * @arg @ref LL_TIM_OSSI_ENABLE
- * @param OffStateRun This parameter can be one of the following values:
- * @arg @ref LL_TIM_OSSR_DISABLE
- * @arg @ref LL_TIM_OSSR_ENABLE
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
-{
- MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
-}
-
-/**
- * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
-}
-
-/**
- * @brief Disable automatic output (MOE can be set only by software).
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
-}
-
-/**
- * @brief Indicate whether automatic output is enabled.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
-}
-
-/**
- * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
- * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
- * software and is reset in case of break or break2 event
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
-}
-
-/**
- * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
- * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
- * software and is reset in case of break or break2 event.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
-}
-
-/**
- * @brief Indicates whether outputs are enabled.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
- * @{
- */
-/**
- * @brief Configures the timer DMA burst feature.
- * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
- * not a timer instance supports the DMA burst mode.
- * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
- * DCR DBA LL_TIM_ConfigDMABurst
- * @param TIMx Timer instance
- * @param DMABurstBaseAddress This parameter can be one of the following values:
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
- * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
- * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
- * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
- * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
- * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
- * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
- * @param DMABurstLength This parameter can be one of the following values:
- * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
- * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
- * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
-{
- MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
-}
-
-/**
- * @}
- */
-
-
-/**
- * @}
- */
-
-
-/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
- * @{
- */
-/**
- * @brief Clear the update interrupt flag (UIF).
- * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
-}
-
-/**
- * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
- * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
-}
-
-/**
- * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
- * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
- * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
-}
-
-/**
- * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
- * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
- * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
-}
-
-/**
- * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
- * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
- * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
-}
-
-/**
- * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
- * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
- * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
-}
-
-/**
- * @brief Clear the commutation interrupt flag (COMIF).
- * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
-}
-
-/**
- * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
- * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
-}
-
-/**
- * @brief Clear the trigger interrupt flag (TIF).
- * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
-}
-
-/**
- * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
- * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
-}
-
-/**
- * @brief Clear the break interrupt flag (BIF).
- * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
-}
-
-/**
- * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
- * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
-}
-
-/**
- * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
- * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
- * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
-}
-
-/**
- * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
- * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
- * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
-}
-
-/**
- * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
- * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
- * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
-}
-
-/**
- * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
- * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
-{
- WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
-}
-
-/**
- * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
- * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_IT_Management IT-Management
- * @{
- */
-/**
- * @brief Enable update interrupt (UIE).
- * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
- * @brief Disable update interrupt (UIE).
- * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
-}
-
-/**
- * @brief Indicates whether the update interrupt (UIE) is enabled.
- * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
-}
-
-/**
- * @brief Enable capture/compare 1 interrupt (CC1IE).
- * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
- * @brief Disable capture/compare 1 interrupt (CC1IE).
- * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
- * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
-}
-
-/**
- * @brief Enable capture/compare 2 interrupt (CC2IE).
- * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
- * @brief Disable capture/compare 2 interrupt (CC2IE).
- * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
- * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
-}
-
-/**
- * @brief Enable capture/compare 3 interrupt (CC3IE).
- * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
- * @brief Disable capture/compare 3 interrupt (CC3IE).
- * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
- * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
-}
-
-/**
- * @brief Enable capture/compare 4 interrupt (CC4IE).
- * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
- * @brief Disable capture/compare 4 interrupt (CC4IE).
- * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
- * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
-}
-
-/**
- * @brief Enable commutation interrupt (COMIE).
- * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
-}
-
-/**
- * @brief Disable commutation interrupt (COMIE).
- * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
-}
-
-/**
- * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
- * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
-}
-
-/**
- * @brief Enable trigger interrupt (TIE).
- * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
- * @brief Disable trigger interrupt (TIE).
- * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
-}
-
-/**
- * @brief Indicates whether the trigger interrupt (TIE) is enabled.
- * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
-}
-
-/**
- * @brief Enable break interrupt (BIE).
- * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_BIE);
-}
-
-/**
- * @brief Disable break interrupt (BIE).
- * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
-}
-
-/**
- * @brief Indicates whether the break interrupt (BIE) is enabled.
- * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
- * @{
- */
-/**
- * @brief Enable update DMA request (UDE).
- * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
- * @brief Disable update DMA request (UDE).
- * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
-}
-
-/**
- * @brief Indicates whether the update DMA request (UDE) is enabled.
- * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
-}
-
-/**
- * @brief Enable capture/compare 1 DMA request (CC1DE).
- * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
- * @brief Disable capture/compare 1 DMA request (CC1DE).
- * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
- * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
-}
-
-/**
- * @brief Enable capture/compare 2 DMA request (CC2DE).
- * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
- * @brief Disable capture/compare 2 DMA request (CC2DE).
- * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
- * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
-}
-
-/**
- * @brief Enable capture/compare 3 DMA request (CC3DE).
- * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
- * @brief Disable capture/compare 3 DMA request (CC3DE).
- * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
- * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
-}
-
-/**
- * @brief Enable capture/compare 4 DMA request (CC4DE).
- * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
- * @brief Disable capture/compare 4 DMA request (CC4DE).
- * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
-}
-
-/**
- * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
- * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
-}
-
-/**
- * @brief Enable commutation DMA request (COMDE).
- * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
-}
-
-/**
- * @brief Disable commutation DMA request (COMDE).
- * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
-}
-
-/**
- * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
- * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
-}
-
-/**
- * @brief Enable trigger interrupt (TDE).
- * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
- * @brief Disable trigger interrupt (TDE).
- * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
- CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
-}
-
-/**
- * @brief Indicates whether the trigger interrupt (TDE) is enabled.
- * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
- * @param TIMx Timer instance
- * @retval State of bit (1 or 0).
- */
-__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
-{
- return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
- * @{
- */
-/**
- * @brief Generate an update event.
- * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_UG);
-}
-
-/**
- * @brief Generate Capture/Compare 1 event.
- * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
-}
-
-/**
- * @brief Generate Capture/Compare 2 event.
- * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
-}
-
-/**
- * @brief Generate Capture/Compare 3 event.
- * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
-}
-
-/**
- * @brief Generate Capture/Compare 4 event.
- * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
-}
-
-/**
- * @brief Generate commutation event.
- * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_COMG);
-}
-
-/**
- * @brief Generate trigger event.
- * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_TG);
-}
-
-/**
- * @brief Generate break event.
- * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
- * @param TIMx Timer instance
- * @retval None
- */
-__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
-{
- SET_BIT(TIMx->EGR, TIM_EGR_BG);
-}
-
-/**
- * @}
- */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
- * @{
- */
-
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
-void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
-void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
-ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
-void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
-/**
- * @}
- */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_TIM_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h b/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h
deleted file mode 100644
index e224e691707d57c71d0162c2db5993a800628d71..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_utils.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_utils.h
- * @author MCD Application Team
- * @brief Header file of UTILS LL module.
- @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- The LL UTILS driver contains a set of generic APIs that can be
- used by user:
- (+) Device electronic signature
- (+) Timing functions
- (+) PLL configuration functions
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_LL_UTILS_H
-#define __STM32F1xx_LL_UTILS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-/** @defgroup UTILS_LL UTILS
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
- * @{
- */
-
-/* Max delay can be used in LL_mDelay */
-#define LL_MAX_DELAY 0xFFFFFFFFU
-
-/**
- * @brief Unique device ID register base address
- */
-#define UID_BASE_ADDRESS UID_BASE
-
-/**
- * @brief Flash size data register base address
- */
-#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
-
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
- * @{
- */
-/**
- * @}
- */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
- * @{
- */
-/**
- * @brief UTILS PLL structure definition
- */
-typedef struct
-{
- uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
- This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-
- uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
- This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-} LL_UTILS_PLLInitTypeDef;
-
-/**
- * @brief UTILS System, AHB and APB buses clock configuration structure definition
- */
-typedef struct
-{
- uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
- This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_SetAHBPrescaler(). */
-
- uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_SetAPB1Prescaler(). */
-
- uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
- This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
-
- This feature can be modified afterwards using unitary function
- @ref LL_RCC_SetAPB2Prescaler(). */
-
-} LL_UTILS_ClkInitTypeDef;
-
-/**
- * @}
- */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
- * @{
- */
-
-/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
- * @{
- */
-#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
-#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
- * @{
- */
-
-/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
- * @{
- */
-
-/**
- * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
- * @retval UID[31:0]
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
-{
- return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
-}
-
-/**
- * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
- * @retval UID[63:32]
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
-{
- return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
-}
-
-/**
- * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
- * @retval UID[95:64]
- */
-__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
-{
- return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
-}
-
-/**
- * @brief Get Flash memory size
- * @note This bitfield indicates the size of the device Flash memory expressed in
- * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
- * @retval FLASH_SIZE[15:0]: Flash memory size
- */
-__STATIC_INLINE uint32_t LL_GetFlashSize(void)
-{
- return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
-}
-
-
-/**
- * @}
- */
-
-/** @defgroup UTILS_LL_EF_DELAY DELAY
- * @{
- */
-
-/**
- * @brief This function configures the Cortex-M SysTick source of the time base.
- * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
- * @note When a RTOS is used, it is recommended to avoid changing the SysTick
- * configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param Ticks Number of ticks
- * @retval None
- */
-__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
-{
- /* Configure the SysTick to have interrupt in 1ms time base */
- SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
-}
-
-void LL_Init1msTick(uint32_t HCLKFrequency);
-void LL_mDelay(uint32_t Delay);
-
-/**
- * @}
- */
-
-/** @defgroup UTILS_EF_SYSTEM SYSTEM
- * @{
- */
-
-void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
- LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
- LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_LL_UTILS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c
deleted file mode 100644
index cb73461f552d1e604a8c3bad0c5f11a0304da637..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_dma.c
- * @author MCD Application Team
- * @brief DMA LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_dma.h"
-#include "stm32f1xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (DMA1) || defined (DMA2)
-
-/** @defgroup DMA_LL DMA
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup DMA_LL_Private_Macros
- * @{
- */
-#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
- ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
- ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
-
-#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
- ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
-
-#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
- ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
-
-#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
- ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
-
-#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
- ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
- ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
-
-#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
- ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
- ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
-
-#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
-
-#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
- ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
- ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
- ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
-
-#if defined (DMA2)
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1) || \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5) || \
- ((CHANNEL) == LL_DMA_CHANNEL_6) || \
- ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
- (((INSTANCE) == DMA2) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1) || \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5))))
-#else
-#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
- (((CHANNEL) == LL_DMA_CHANNEL_1) || \
- ((CHANNEL) == LL_DMA_CHANNEL_2) || \
- ((CHANNEL) == LL_DMA_CHANNEL_3) || \
- ((CHANNEL) == LL_DMA_CHANNEL_4) || \
- ((CHANNEL) == LL_DMA_CHANNEL_5) || \
- ((CHANNEL) == LL_DMA_CHANNEL_6) || \
- ((CHANNEL) == LL_DMA_CHANNEL_7))))
-#endif
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup DMA_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the DMA registers to their default reset values.
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: DMA registers are de-initialized
- * - ERROR: DMA registers are not de-initialized
- */
-uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
-{
- DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
- ErrorStatus status = SUCCESS;
-
- /* Check the DMA Instance DMAx and Channel parameters*/
- assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
-
- tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
-
- /* Disable the selected DMAx_Channely */
- CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
-
- /* Reset DMAx_Channely control register */
- LL_DMA_WriteReg(tmp, CCR, 0U);
-
- /* Reset DMAx_Channely remaining bytes register */
- LL_DMA_WriteReg(tmp, CNDTR, 0U);
-
- /* Reset DMAx_Channely peripheral address register */
- LL_DMA_WriteReg(tmp, CPAR, 0U);
-
- /* Reset DMAx_Channely memory address register */
- LL_DMA_WriteReg(tmp, CMAR, 0U);
-
- if (Channel == LL_DMA_CHANNEL_1)
- {
- /* Reset interrupt pending bits for DMAx Channel1 */
- LL_DMA_ClearFlag_GI1(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_2)
- {
- /* Reset interrupt pending bits for DMAx Channel2 */
- LL_DMA_ClearFlag_GI2(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_3)
- {
- /* Reset interrupt pending bits for DMAx Channel3 */
- LL_DMA_ClearFlag_GI3(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_4)
- {
- /* Reset interrupt pending bits for DMAx Channel4 */
- LL_DMA_ClearFlag_GI4(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_5)
- {
- /* Reset interrupt pending bits for DMAx Channel5 */
- LL_DMA_ClearFlag_GI5(DMAx);
- }
-
- else if (Channel == LL_DMA_CHANNEL_6)
- {
- /* Reset interrupt pending bits for DMAx Channel6 */
- LL_DMA_ClearFlag_GI6(DMAx);
- }
- else if (Channel == LL_DMA_CHANNEL_7)
- {
- /* Reset interrupt pending bits for DMAx Channel7 */
- LL_DMA_ClearFlag_GI7(DMAx);
- }
- else
- {
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
- * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
- * @arg @ref __LL_DMA_GET_INSTANCE
- * @arg @ref __LL_DMA_GET_CHANNEL
- * @param DMAx DMAx Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_DMA_CHANNEL_1
- * @arg @ref LL_DMA_CHANNEL_2
- * @arg @ref LL_DMA_CHANNEL_3
- * @arg @ref LL_DMA_CHANNEL_4
- * @arg @ref LL_DMA_CHANNEL_5
- * @arg @ref LL_DMA_CHANNEL_6
- * @arg @ref LL_DMA_CHANNEL_7
- * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: DMA registers are initialized
- * - ERROR: Not applicable
- */
-uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
-{
- /* Check the DMA Instance DMAx and Channel parameters*/
- assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
-
- /* Check the DMA parameters from DMA_InitStruct */
- assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
- assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
- assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
- assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
- assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
- assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
- assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
- assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
-
- /*---------------------------- DMAx CCR Configuration ------------------------
- * Configure DMAx_Channely: data transfer direction, data transfer mode,
- * peripheral and memory increment mode,
- * data size alignment and priority level with parameters :
- * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
- * - Mode: DMA_CCR_CIRC bit
- * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
- * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
- * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
- * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
- * - Priority: DMA_CCR_PL[1:0] bits
- */
- LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
- DMA_InitStruct->Mode | \
- DMA_InitStruct->PeriphOrM2MSrcIncMode | \
- DMA_InitStruct->MemoryOrM2MDstIncMode | \
- DMA_InitStruct->PeriphOrM2MSrcDataSize | \
- DMA_InitStruct->MemoryOrM2MDstDataSize | \
- DMA_InitStruct->Priority);
-
- /*-------------------------- DMAx CMAR Configuration -------------------------
- * Configure the memory or destination base address with parameter :
- * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
- */
- LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
-
- /*-------------------------- DMAx CPAR Configuration -------------------------
- * Configure the peripheral or source base address with parameter :
- * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
- */
- LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
-
- /*--------------------------- DMAx CNDTR Configuration -----------------------
- * Configure the peripheral base address with parameter :
- * - NbData: DMA_CNDTR_NDT[15:0] bits
- */
- LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
- * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
- * @retval None
- */
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
-{
- /* Set DMA_InitStruct fields to default values */
- DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
- DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
- DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
- DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
- DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
- DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
- DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
- DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
- DMA_InitStruct->NbData = 0x00000000U;
- DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* DMA1 || DMA2 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c
deleted file mode 100644
index 5485adf95f8a0a44f1e14911072882b9574a409a..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_exti.c
- * @author MCD Application Team
- * @brief EXTI LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_exti.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup EXTI_LL_Private_Macros
- * @{
- */
-
-#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
-
-#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
- || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
- || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
-
-
-#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup EXTI_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup EXTI_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the EXTI registers to their default reset values.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: EXTI registers are de-initialized
- * - ERROR: not applicable
- */
-uint32_t LL_EXTI_DeInit(void)
-{
- /* Interrupt mask register set to default reset values */
- LL_EXTI_WriteReg(IMR, 0x00000000U);
- /* Event mask register set to default reset values */
- LL_EXTI_WriteReg(EMR, 0x00000000U);
- /* Rising Trigger selection register set to default reset values */
- LL_EXTI_WriteReg(RTSR, 0x00000000U);
- /* Falling Trigger selection register set to default reset values */
- LL_EXTI_WriteReg(FTSR, 0x00000000U);
- /* Software interrupt event register set to default reset values */
- LL_EXTI_WriteReg(SWIER, 0x00000000U);
- /* Pending register clear */
- LL_EXTI_WriteReg(PR, 0x000FFFFFU);
-
- return SUCCESS;
-}
-
-/**
- * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
- * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: EXTI registers are initialized
- * - ERROR: not applicable
- */
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
-{
- ErrorStatus status = SUCCESS;
- /* Check the parameters */
- assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
- assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
- assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
-
- /* ENABLE LineCommand */
- if (EXTI_InitStruct->LineCommand != DISABLE)
- {
- assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
-
- /* Configure EXTI Lines in range from 0 to 31 */
- if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
- {
- switch (EXTI_InitStruct->Mode)
- {
- case LL_EXTI_MODE_IT:
- /* First Disable Event on provided Lines */
- LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable IT on provided Lines */
- LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_MODE_EVENT:
- /* First Disable IT on provided Lines */
- LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable Event on provided Lines */
- LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_MODE_IT_EVENT:
- /* Directly Enable IT & Event on provided Lines */
- LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
- LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
- break;
- default:
- status = ERROR;
- break;
- }
- if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
- {
- switch (EXTI_InitStruct->Trigger)
- {
- case LL_EXTI_TRIGGER_RISING:
- /* First Disable Falling Trigger on provided Lines */
- LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable Rising Trigger on provided Lines */
- LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_TRIGGER_FALLING:
- /* First Disable Rising Trigger on provided Lines */
- LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
- /* Then Enable Falling Trigger on provided Lines */
- LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
- break;
- case LL_EXTI_TRIGGER_RISING_FALLING:
- LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
- LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
- break;
- default:
- status = ERROR;
- break;
- }
- }
- }
- }
- /* DISABLE LineCommand */
- else
- {
- /* De-configure EXTI Lines in range from 0 to 31 */
- LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
- LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
- * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
- * @retval None
- */
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
-{
- EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
- EXTI_InitStruct->LineCommand = DISABLE;
- EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
- EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (EXTI) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c
deleted file mode 100644
index 18fc3bd1517c19cf8f40d2931de19d15632a4dfa..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_gpio.c
- * @author MCD Application Team
- * @brief GPIO LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_gpio.h"
-#include "stm32f1xx_ll_bus.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
-
-/** @addtogroup GPIO_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup GPIO_LL_Private_Macros
- * @{
- */
-
-#define IS_LL_GPIO_PIN(__VALUE__) ((((__VALUE__) & LL_GPIO_PIN_ALL)!= 0U) &&\
- (((__VALUE__) & (~LL_GPIO_PIN_ALL))== 0U))
-
-#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_ANALOG) ||\
- ((__VALUE__) == LL_GPIO_MODE_FLOATING) ||\
- ((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
- ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
- ((__VALUE__) == LL_GPIO_MODE_ALTERNATE))
-
-#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
- ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
- ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH))
-
-#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
- ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
-
-#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_DOWN) ||\
- ((__VALUE__) == LL_GPIO_PULL_UP))
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup GPIO_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize GPIO registers (Registers restored to their default values).
- * @param GPIOx GPIO Port
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: GPIO registers are de-initialized
- * - ERROR: Wrong GPIO Port
- */
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-
- /* Force and Release reset on clock of GPIOx Port */
- if (GPIOx == GPIOA)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOA);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOA);
- }
- else if (GPIOx == GPIOB)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOB);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOB);
- }
- else if (GPIOx == GPIOC)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOC);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOC);
- }
- else if (GPIOx == GPIOD)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOD);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOD);
- }
-#if defined(GPIOE)
- else if (GPIOx == GPIOE)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOE);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOE);
- }
-#endif
-#if defined(GPIOF)
- else if (GPIOx == GPIOF)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOF);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOF);
- }
-#endif
-#if defined(GPIOG)
- else if (GPIOx == GPIOG)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_GPIOG);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_GPIOG);
- }
-#endif
- else
- {
- status = ERROR;
- }
-
- return (status);
-}
-
-/**
- * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
- * @param GPIOx GPIO Port
- * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
- * that contains the configuration information for the specified GPIO peripheral.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
- * - ERROR: Not applicable
- */
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
-{
- uint32_t pinmask;
- uint32_t pinpos;
- uint32_t currentpin;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
- assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
-
- /* ------------------------- Configure the port pins ---------------- */
- /* Initialize pinpos on first pin set */
-
- pinmask = ((GPIO_InitStruct->Pin) << GPIO_PIN_MASK_POS) >> GPIO_PIN_NB;
- pinpos = POSITION_VAL(pinmask);
-
- /* Configure the port pins */
- while ((pinmask >> pinpos) != 0U)
- {
- /* skip if bit is not set */
- if ((pinmask & (1U << pinpos)) != 0U)
- {
- /* Get current io position */
- if (pinpos < GPIO_PIN_MASK_POS)
- {
- currentpin = (0x00000101U << pinpos);
- }
- else
- {
- currentpin = ((0x00010001U << (pinpos - GPIO_PIN_MASK_POS)) | 0x04000000U);
- }
-
- /* Check Pin Mode and Pin Pull parameters */
- assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
- assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
-
- /* Pin Mode configuration */
- LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
-
- /* Pull-up Pull-down resistor configuration*/
- LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
-
- if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
- {
- /* Check speed and Output mode parameters */
- assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
- assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
-
- /* Speed mode configuration */
- LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
-
- /* Output mode configuration*/
- LL_GPIO_SetPinOutputType(GPIOx, currentpin, GPIO_InitStruct->OutputType);
- }
- }
- pinpos++;
- }
- return (SUCCESS);
-}
-
-/**
- * @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
- * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-
-void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
- GPIO_InitStruct->Mode = LL_GPIO_MODE_FLOATING;
- GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
- GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
- GPIO_InitStruct->Pull = LL_GPIO_PULL_DOWN;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c
deleted file mode 100644
index 5304bd5957662bdeeb60e346b1ff02b8dba69325..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_pwr.c
- * @author MCD Application Team
- * @brief PWR LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_pwr.h"
-#include "stm32f1xx_ll_bus.h"
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWR_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup PWR_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the PWR registers to their default reset values.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: PWR registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_PWR_DeInit(void)
-{
- /* Force reset of PWR clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
-
- /* Release reset of PWR clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
-
- return SUCCESS;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* defined(PWR) */
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c
deleted file mode 100644
index 615adecb9be5f33d188efb7c341575e513e9e5f8..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c
+++ /dev/null
@@ -1,489 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_rcc.c
- * @author MCD Application Team
- * @brief RCC LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_rcc.h"
-#ifdef USE_FULL_ASSERT
- #include "stm32_assert.h"
-#else
- #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCC_LL_Private_Macros
- * @{
- */
-#if defined(RCC_PLLI2S_SUPPORT)
-#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S2_CLKSOURCE) \
- || ((__VALUE__) == LL_RCC_I2S3_CLKSOURCE))
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(USB) || defined(USB_OTG_FS)
-#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
-#endif /* USB */
-
-#define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_ADC_CLKSOURCE))
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup RCC_LL_Private_Functions RCC Private functions
- * @{
- */
-uint32_t RCC_GetSystemClockFreq(void);
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
-uint32_t RCC_PLL_GetFreqDomain_SYS(void);
-#if defined(RCC_PLLI2S_SUPPORT)
-uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
-#endif /* RCC_PLLI2S_SUPPORT */
-#if defined(RCC_PLL2_SUPPORT)
-uint32_t RCC_PLL2_GetFreqClockFreq(void);
-#endif /* RCC_PLL2_SUPPORT */
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup RCC_LL_EF_Init
- * @{
- */
-
-/**
- * @brief Reset the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE PLL, PLL2 & PLL3 are OFF
- * - AHB, APB1 and APB2 prescaler set to 1.
- * - CSS, MCO OFF
- * - All interrupts disabled
- * @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RCC registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_RCC_DeInit(void)
-{
- /* Set HSION bit */
- LL_RCC_HSI_Enable();
-
- /* Wait for HSI READY bit */
- while(LL_RCC_HSI_IsReady() != 1U)
- {}
-
- /* Configure HSI as system clock source */
- LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
-
- /* Wait till clock switch is ready */
- while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI)
- {}
-
- /* Reset PLLON bit */
- CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
-
- /* Wait for PLL READY bit to be reset */
- while(LL_RCC_PLL_IsReady() != 0U)
- {}
-
- /* Reset CFGR register */
- LL_RCC_WriteReg(CFGR, 0x00000000U);
-
- /* Reset HSEON, HSEBYP & CSSON bits */
- CLEAR_BIT(RCC->CR, (RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSEBYP));
-
-#if defined(RCC_CR_PLL2ON)
- /* Reset PLL2ON bit */
- CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
-#endif /* RCC_CR_PLL2ON */
-
-#if defined(RCC_CR_PLL3ON)
- /* Reset PLL3ON bit */
- CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
-#endif /* RCC_CR_PLL3ON */
-
- /* Set HSITRIM bits to the reset value */
- LL_RCC_HSI_SetCalibTrimming(0x10U);
-
-#if defined(RCC_CFGR2_PREDIV1)
- /* Reset CFGR2 register */
- LL_RCC_WriteReg(CFGR2, 0x00000000U);
-#endif /* RCC_CFGR2_PREDIV1 */
-
- /* Disable all interrupts */
- LL_RCC_WriteReg(CIR, 0x00000000U);
-
- /* Clear reset flags */
- LL_RCC_ClearResetFlags();
-
- return SUCCESS;
-}
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_LL_EF_Get_Freq
- * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
- * and different peripheral clocks available on the device.
- * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
- * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
- * @note If SYSCLK source is PLL, function returns values based on
- * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
- * @note (**) HSI_VALUE is a defined constant but the real value may vary
- * depending on the variations in voltage and temperature.
- * @note (***) HSE_VALUE is a defined constant, user has to ensure that
- * HSE_VALUE is same as the real frequency of the crystal used.
- * Otherwise, this function may have wrong result.
- * @note The result of this function could be incorrect when using fractional
- * value for HSE crystal.
- * @note This function can be used by the user application to compute the
- * baud-rate for the communication peripherals or configure other parameters.
- * @{
- */
-
-/**
- * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
- * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
- * must be called to update structure fields. Otherwise, any
- * configuration based on this function will be incorrect.
- * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
- * @retval None
- */
-void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
-{
- /* Get SYSCLK frequency */
- RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
-
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
-
- /* PCLK1 clock frequency */
- RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
-
- /* PCLK2 clock frequency */
- RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
-}
-
-#if defined(RCC_CFGR2_I2S2SRC)
-/**
- * @brief Return I2Sx clock frequency
- * @param I2SxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_I2S2_CLKSOURCE
- * @arg @ref LL_RCC_I2S3_CLKSOURCE
- * @retval I2S clock frequency (in Hz)
- */
-uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
-{
- uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
-
- /* I2S1CLK clock frequency */
- switch (LL_RCC_GetI2SClockSource(I2SxSource))
- {
- case LL_RCC_I2S2_CLKSOURCE_SYSCLK: /*!< System clock selected as I2S clock source */
- case LL_RCC_I2S3_CLKSOURCE_SYSCLK:
- i2s_frequency = RCC_GetSystemClockFreq();
- break;
-
- case LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO: /*!< PLLI2S oscillator clock selected as I2S clock source */
- case LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO:
- default:
- i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S() * 2U;
- break;
- }
-
- return i2s_frequency;
-}
-#endif /* RCC_CFGR2_I2S2SRC */
-
-#if defined(USB) || defined(USB_OTG_FS)
-/**
- * @brief Return USBx clock frequency
- * @param USBxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_USB_CLKSOURCE
- * @retval USB clock frequency (in Hz)
- * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI), HSE or PLL is not ready
- */
-uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
-{
- uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
-
- /* USBCLK clock frequency */
- switch (LL_RCC_GetUSBClockSource(USBxSource))
- {
-#if defined(RCC_CFGR_USBPRE)
- case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
- if (LL_RCC_PLL_IsReady())
- {
- usb_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
- break;
-
- case LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5: /* PLL clock divided by 1.5 used as USB clock source */
- default:
- if (LL_RCC_PLL_IsReady())
- {
- usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 3U) / 2U;
- }
- break;
-#endif /* RCC_CFGR_USBPRE */
-#if defined(RCC_CFGR_OTGFSPRE)
- /* USBCLK = PLLVCO/2
- = (2 x PLLCLK) / 2
- = PLLCLK */
- case LL_RCC_USB_CLKSOURCE_PLL_DIV_2: /* PLL clock used as USB clock source */
- if (LL_RCC_PLL_IsReady())
- {
- usb_frequency = RCC_PLL_GetFreqDomain_SYS();
- }
- break;
-
- /* USBCLK = PLLVCO/3
- = (2 x PLLCLK) / 3 */
- case LL_RCC_USB_CLKSOURCE_PLL_DIV_3: /* PLL clock divided by 3 used as USB clock source */
- default:
- if (LL_RCC_PLL_IsReady())
- {
- usb_frequency = (RCC_PLL_GetFreqDomain_SYS() * 2U) / 3U;
- }
- break;
-#endif /* RCC_CFGR_OTGFSPRE */
- }
-
- return usb_frequency;
-}
-#endif /* USB */
-
-/**
- * @brief Return ADCx clock frequency
- * @param ADCxSource This parameter can be one of the following values:
- * @arg @ref LL_RCC_ADC_CLKSOURCE
- * @retval ADC clock frequency (in Hz)
- */
-uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
-{
- uint32_t adc_prescaler = 0U;
- uint32_t adc_frequency = 0U;
-
- /* Check parameter */
- assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
-
- /* Get ADC prescaler */
- adc_prescaler = LL_RCC_GetADCClockSource(ADCxSource);
-
- /* ADC frequency = PCLK2 frequency / ADC prescaler (2, 4, 6 or 8) */
- adc_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()))
- / (((adc_prescaler >> POSITION_VAL(ADCxSource)) + 1U) * 2U);
-
- return adc_frequency;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup RCC_LL_Private_Functions
- * @{
- */
-
-/**
- * @brief Return SYSTEM clock frequency
- * @retval SYSTEM clock frequency (in Hz)
- */
-uint32_t RCC_GetSystemClockFreq(void)
-{
- uint32_t frequency = 0U;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- switch (LL_RCC_GetSysClkSource())
- {
- case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
- frequency = HSI_VALUE;
- break;
-
- case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
- frequency = HSE_VALUE;
- break;
-
- case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
- frequency = RCC_PLL_GetFreqDomain_SYS();
- break;
-
- default:
- frequency = HSI_VALUE;
- break;
- }
-
- return frequency;
-}
-
-/**
- * @brief Return HCLK clock frequency
- * @param SYSCLK_Frequency SYSCLK clock frequency
- * @retval HCLK clock frequency (in Hz)
- */
-uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
-{
- /* HCLK clock frequency */
- return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
-}
-
-/**
- * @brief Return PCLK1 clock frequency
- * @param HCLK_Frequency HCLK clock frequency
- * @retval PCLK1 clock frequency (in Hz)
- */
-uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
-{
- /* PCLK1 clock frequency */
- return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
-}
-
-/**
- * @brief Return PCLK2 clock frequency
- * @param HCLK_Frequency HCLK clock frequency
- * @retval PCLK2 clock frequency (in Hz)
- */
-uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
-{
- /* PCLK2 clock frequency */
- return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
-}
-
-/**
- * @brief Return PLL clock frequency used for system domain
- * @retval PLL clock frequency (in Hz)
- */
-uint32_t RCC_PLL_GetFreqDomain_SYS(void)
-{
- uint32_t pllinputfreq = 0U, pllsource = 0U;
-
- /* PLL_VCO = (HSE_VALUE, HSI_VALUE or PLL2 / PLL Predivider) * PLL Multiplicator */
-
- /* Get PLL source */
- pllsource = LL_RCC_PLL_GetMainSource();
-
- switch (pllsource)
- {
- case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
- pllinputfreq = HSI_VALUE / 2U;
- break;
-
- case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
- pllinputfreq = HSE_VALUE / (LL_RCC_PLL_GetPrediv() + 1U);
- break;
-
-#if defined(RCC_PLL2_SUPPORT)
- case LL_RCC_PLLSOURCE_PLL2: /* PLL2 used as PLL clock source */
- pllinputfreq = RCC_PLL2_GetFreqClockFreq() / (LL_RCC_PLL_GetPrediv() + 1U);
- break;
-#endif /* RCC_PLL2_SUPPORT */
-
- default:
- pllinputfreq = HSI_VALUE / 2U;
- break;
- }
- return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator());
-}
-
-#if defined(RCC_PLL2_SUPPORT)
-/**
- * @brief Return PLL clock frequency used for system domain
- * @retval PLL clock frequency (in Hz)
- */
-uint32_t RCC_PLL2_GetFreqClockFreq(void)
-{
- return __LL_RCC_CALC_PLL2CLK_FREQ(HSE_VALUE, LL_RCC_PLL2_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
-}
-#endif /* RCC_PLL2_SUPPORT */
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
- * @brief Return PLL clock frequency used for system domain
- * @retval PLL clock frequency (in Hz)
- */
-uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
-{
- return __LL_RCC_CALC_PLLI2SCLK_FREQ(HSE_VALUE, LL_RCC_PLLI2S_GetMultiplicator(), LL_RCC_HSE_GetPrediv2());
-}
-#endif /* RCC_PLLI2S_SUPPORT */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* defined(RCC) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c
deleted file mode 100644
index 151f6dd43451814c2ec624fded4d5a758fea6da4..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c
+++ /dev/null
@@ -1,560 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_spi.c
- * @author MCD Application Team
- * @brief SPI LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_spi.h"
-#include "stm32f1xx_ll_bus.h"
-#include "stm32f1xx_ll_rcc.h"
-
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (SPI1) || defined (SPI2) || defined (SPI3)
-
-/** @addtogroup SPI_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SPI_LL_Private_Constants SPI Private Constants
- * @{
- */
-/* SPI registers Masks */
-#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
- SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
- SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
- SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
- SPI_CR1_BIDIMODE)
-/**
- * @}
- */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_LL_Private_Macros SPI Private Macros
- * @{
- */
-#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
- || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
- || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
- || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
-
-#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
- || ((__VALUE__) == LL_SPI_MODE_SLAVE))
-
-#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
- || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
-
-#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
- || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
-
-#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
- || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
-
-#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
- || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
- || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
-
-#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
- || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
-
-#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
- || ((__VALUE__) == LL_SPI_MSB_FIRST))
-
-#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
- || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
-
-#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
-
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup SPI_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the SPI registers to their default reset values.
- * @param SPIx SPI Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: SPI registers are de-initialized
- * - ERROR: SPI registers are not de-initialized
- */
-ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_INSTANCE(SPIx));
-
-#if defined(SPI1)
- if (SPIx == SPI1)
- {
- /* Force reset of SPI clock */
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
-
- /* Release reset of SPI clock */
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
-
- status = SUCCESS;
- }
-#endif /* SPI1 */
-#if defined(SPI2)
- if (SPIx == SPI2)
- {
- /* Force reset of SPI clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
-
- /* Release reset of SPI clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
-
- status = SUCCESS;
- }
-#endif /* SPI2 */
-#if defined(SPI3)
- if (SPIx == SPI3)
- {
- /* Force reset of SPI clock */
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
-
- /* Release reset of SPI clock */
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
-
- status = SUCCESS;
- }
-#endif /* SPI3 */
-
- return status;
-}
-
-/**
- * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
- * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @param SPIx SPI Instance
- * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
- * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
- */
-ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
-{
- ErrorStatus status = ERROR;
-
- /* Check the SPI Instance SPIx*/
- assert_param(IS_SPI_ALL_INSTANCE(SPIx));
-
- /* Check the SPI parameters from SPI_InitStruct*/
- assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
- assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
- assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
- assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
- assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
- assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
- assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
- assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
- assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
-
- if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
- {
- /*---------------------------- SPIx CR1 Configuration ------------------------
- * Configure SPIx CR1 with parameters:
- * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
- * - Master/Slave Mode: SPI_CR1_MSTR bit
- * - DataWidth: SPI_CR1_DFF bit
- * - ClockPolarity: SPI_CR1_CPOL bit
- * - ClockPhase: SPI_CR1_CPHA bit
- * - NSS management: SPI_CR1_SSM bit
- * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
- * - BitOrder: SPI_CR1_LSBFIRST bit
- * - CRCCalculation: SPI_CR1_CRCEN bit
- */
- MODIFY_REG(SPIx->CR1,
- SPI_CR1_CLEAR_MASK,
- SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
- SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
- SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
- SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
-
- /*---------------------------- SPIx CR2 Configuration ------------------------
- * Configure SPIx CR2 with parameters:
- * - NSS management: SSOE bit
- */
- MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
-
- /*---------------------------- SPIx CRCPR Configuration ----------------------
- * Configure SPIx CRCPR with parameters:
- * - CRCPoly: CRCPOLY[15:0] bits
- */
- if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
- {
- assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
- LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
- }
- status = SUCCESS;
- }
-
-#if defined (SPI_I2S_SUPPORT)
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
- CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif /* SPI_I2S_SUPPORT */
- return status;
-}
-
-/**
- * @brief Set each @ref LL_SPI_InitTypeDef field to default value.
- * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
-{
- /* Set SPI_InitStruct fields to default values */
- SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
- SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
- SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
- SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
- SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
- SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
- SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
- SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
- SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
- SPI_InitStruct->CRCPoly = 7U;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#if defined(SPI_I2S_SUPPORT)
-/** @addtogroup I2S_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2S_LL_Private_Constants I2S Private Constants
- * @{
- */
-/* I2S registers Masks */
-#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
- SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
- SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
-
-#define I2S_I2SPR_CLEAR_MASK 0x0002U
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_LL_Private_Macros I2S Private Macros
- * @{
- */
-
-#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
- || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
-
-#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
- || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
-
-#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
- || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
- || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
- || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
- || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
-
-#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
- || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
- || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
-
-#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
- || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
-
-#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
- && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
- || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
-
-#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
-
-#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
- || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
-/**
- * @}
- */
-
-/* Private function prototypes -----------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup I2S_LL_EF_Init
- * @{
- */
-
-/**
- * @brief De-initialize the SPI/I2S registers to their default reset values.
- * @param SPIx SPI Instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: SPI registers are de-initialized
- * - ERROR: SPI registers are not de-initialized
- */
-ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
-{
- return LL_SPI_DeInit(SPIx);
-}
-
-/**
- * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
- * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
- * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
- * @param SPIx SPI Instance
- * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: SPI registers are Initialized
- * - ERROR: SPI registers are not Initialized
- */
-ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
-{
- uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
- uint32_t tmp = 0U;
- uint32_t sourceclock = 0U;
-#if defined(I2S2_I2S3_CLOCK_FEATURE)
-#else
- LL_RCC_ClocksTypeDef rcc_clocks;
-#endif /* I2S2_I2S3_CLOCK_FEATURE */
- ErrorStatus status = ERROR;
-
- /* Check the I2S parameters */
- assert_param(IS_I2S_ALL_INSTANCE(SPIx));
- assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
- assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
- assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
- assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
- assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
- assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
-
- if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
- {
- /*---------------------------- SPIx I2SCFGR Configuration --------------------
- * Configure SPIx I2SCFGR with parameters:
- * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
- * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
- * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
- * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
- */
-
- /* Write to SPIx I2SCFGR */
- MODIFY_REG(SPIx->I2SCFGR,
- I2S_I2SCFGR_CLEAR_MASK,
- I2S_InitStruct->Mode | I2S_InitStruct->Standard |
- I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
- SPI_I2SCFGR_I2SMOD);
-
- /*---------------------------- SPIx I2SPR Configuration ----------------------
- * Configure SPIx I2SPR with parameters:
- * - MCLKOutput: SPI_I2SPR_MCKOE bit
- * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
- */
-
- /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
- * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
- */
- if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
- {
- /* Check the frame length (For the Prescaler computing)
- * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
- */
- if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
- {
- /* Packet length is 32 bits */
- packetlength = 2U;
- }
-#if defined(I2S2_I2S3_CLOCK_FEATURE)
- /* If an external I2S clock has to be used, the specific define should be set
- in the project configuration or in the stm32f1xx_ll_rcc.h file */
- if(SPIx == SPI2)
- {
- /* Get the I2S source clock value */
- sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
- }
- else /* SPI3 */
- {
- /* Get the I2S source clock value */
- sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S3_CLKSOURCE);
- }
-#else
- /* I2S Clock source is System clock: Get System Clock frequency */
- LL_RCC_GetSystemClocksFreq(&rcc_clocks);
-
- /* Get the source clock value: based on System Clock value */
- sourceclock = rcc_clocks.SYSCLK_Frequency;
-#endif /* I2S2_I2S3_CLOCK_FEATURE */
- /* Compute the Real divider depending on the MCLK output state with a floating point */
- if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
- {
- /* MCLK output is enabled */
- tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
- }
-
- /* Remove the floating point */
- tmp = tmp / 10U;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t)(i2sodd << 8U);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
- {
- /* Set the default values */
- i2sdiv = 2U;
- i2sodd = 0U;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
-
- status = SUCCESS;
- }
- return status;
-}
-
-/**
- * @brief Set each @ref LL_I2S_InitTypeDef field to default value.
- * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
- * whose fields will be set to default values.
- * @retval None
- */
-void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
-{
- /*--------------- Reset I2S init structure parameters values -----------------*/
- I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
- I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
- I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
- I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
- I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
- I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
-}
-
-/**
- * @brief Set linear and parity prescaler.
- * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
- * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
- * @param SPIx SPI Instance
- * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
- * @param PrescalerParity This parameter can be one of the following values:
- * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
- * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
- * @retval None
- */
-void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
-{
- /* Check the I2S parameters */
- assert_param(IS_I2S_ALL_INSTANCE(SPIx));
- assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
- assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
-
- /* Write to SPIx I2SPR */
- MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-#endif /* SPI_I2S_SUPPORT */
-
-#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c
deleted file mode 100644
index 942ce13466aa1e2a957abe4b83ae686bcdf91ba6..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c
+++ /dev/null
@@ -1,1214 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_tim.c
- * @author MCD Application Team
- * @brief TIM LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-#if defined(USE_FULL_LL_DRIVER)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_tim.h"
-#include "stm32f1xx_ll_bus.h"
-
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
-
-/** @addtogroup TIM_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup TIM_LL_Private_Macros
- * @{
- */
-#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
- || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
-
-#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
- || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
- || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
-
-#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
- || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
- || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
-
-#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
- || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
-
-#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
- || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
-
-#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
- || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
-
-#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
- || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
- || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
-
-#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
- || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
-
-#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
- || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
-
-#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
-
-#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
- || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
- || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
-
-#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
- || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
-
-#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
- || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
-
-#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
- || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
-
-#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
- || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
-
-#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
- || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
-
-#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
- || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
-
-#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
- || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
-/**
- * @}
- */
-
-
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup TIM_LL_Private_Functions TIM Private Functions
- * @{
- */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup TIM_LL_EF_Init
- * @{
- */
-
-/**
- * @brief Set TIMx registers to their reset values.
- * @param TIMx Timer instance
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: invalid TIMx instance
- */
-ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
-{
- ErrorStatus result = SUCCESS;
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(TIMx));
-
- if (TIMx == TIM2)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
- }
-#if defined(TIM1)
- else if (TIMx == TIM1)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
- }
-#endif
-#if defined(TIM3)
- else if (TIMx == TIM3)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
- }
-#endif
-#if defined(TIM4)
- else if (TIMx == TIM4)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
- }
-#endif
-#if defined(TIM5)
- else if (TIMx == TIM5)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
- }
-#endif
-#if defined(TIM6)
- else if (TIMx == TIM6)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
- }
-#endif
-#if defined (TIM7)
- else if (TIMx == TIM7)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
- }
-#endif
-#if defined(TIM8)
- else if (TIMx == TIM8)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
- }
-#endif
-#if defined(TIM9)
- else if (TIMx == TIM9)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
- }
-#endif
-#if defined(TIM10)
- else if (TIMx == TIM10)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
- }
-#endif
-#if defined(TIM11)
- else if (TIMx == TIM11)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
- }
-#endif
-#if defined(TIM12)
- else if (TIMx == TIM12)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
- }
-#endif
-#if defined(TIM13)
- else if (TIMx == TIM13)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
- }
-#endif
-#if defined(TIM14)
- else if (TIMx == TIM14)
- {
- LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
- LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
- }
-#endif
-#if defined(TIM15)
- else if (TIMx == TIM15)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
- }
-#endif
-#if defined(TIM16)
- else if (TIMx == TIM16)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
- }
-#endif
-#if defined(TIM17)
- else if (TIMx == TIM17)
- {
- LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
- LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
- }
-#endif
- else
- {
- result = ERROR;
- }
-
- return result;
-}
-
-/**
- * @brief Set the fields of the time base unit configuration data structure
- * to their default values.
- * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
- * @retval None
- */
-void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
-{
- /* Set the default configuration */
- TIM_InitStruct->Prescaler = (uint16_t)0x0000;
- TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
- TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
- TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
-}
-
-/**
- * @brief Configure the TIMx time base unit.
- * @param TIMx Timer Instance
- * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
-{
- uint32_t tmpcr1 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
- assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
-
- tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
-
- if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- {
- /* Select the Counter Mode */
- MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
- }
-
- if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- {
- /* Set the clock division */
- MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
- }
-
- /* Write to TIMx CR1 */
- LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
-
- /* Set the Autoreload value */
- LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
-
- /* Set the Prescaler value */
- LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
-
- if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- {
- /* Set the Repetition Counter value */
- LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
- }
-
- /* Generate an update event to reload the Prescaler
- and the repetition counter value (if applicable) immediately */
- LL_TIM_GenerateEvent_UPDATE(TIMx);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set the fields of the TIMx output channel configuration data
- * structure to their default values.
- * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
- * @retval None
- */
-void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
-{
- /* Set the default configuration */
- TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
- TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
- TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
- TIM_OC_InitStruct->CompareValue = 0x00000000U;
- TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
- TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
- TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
- TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
-}
-
-/**
- * @brief Configure the TIMx output channel.
- * @param TIMx Timer Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx output channel is initialized
- * - ERROR: TIMx output channel is not initialized
- */
-ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
-{
- ErrorStatus result = ERROR;
-
- switch (Channel)
- {
- case LL_TIM_CHANNEL_CH1:
- result = OC1Config(TIMx, TIM_OC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH2:
- result = OC2Config(TIMx, TIM_OC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH3:
- result = OC3Config(TIMx, TIM_OC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH4:
- result = OC4Config(TIMx, TIM_OC_InitStruct);
- break;
- default:
- break;
- }
-
- return result;
-}
-
-/**
- * @brief Set the fields of the TIMx input channel configuration data
- * structure to their default values.
- * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
- * @retval None
- */
-void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
- TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
- TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
- TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
-}
-
-/**
- * @brief Configure the TIMx input channel.
- * @param TIMx Timer Instance
- * @param Channel This parameter can be one of the following values:
- * @arg @ref LL_TIM_CHANNEL_CH1
- * @arg @ref LL_TIM_CHANNEL_CH2
- * @arg @ref LL_TIM_CHANNEL_CH3
- * @arg @ref LL_TIM_CHANNEL_CH4
- * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx output channel is initialized
- * - ERROR: TIMx output channel is not initialized
- */
-ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
-{
- ErrorStatus result = ERROR;
-
- switch (Channel)
- {
- case LL_TIM_CHANNEL_CH1:
- result = IC1Config(TIMx, TIM_IC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH2:
- result = IC2Config(TIMx, TIM_IC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH3:
- result = IC3Config(TIMx, TIM_IC_InitStruct);
- break;
- case LL_TIM_CHANNEL_CH4:
- result = IC4Config(TIMx, TIM_IC_InitStruct);
- break;
- default:
- break;
- }
-
- return result;
-}
-
-/**
- * @brief Fills each TIM_EncoderInitStruct field with its default value
- * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
- * @retval None
- */
-void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
-{
- /* Set the default configuration */
- TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
- TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
- TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
- TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
- TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
- TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
- TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
- TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
- TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
-}
-
-/**
- * @brief Configure the encoder interface of the timer instance.
- * @param TIMx Timer Instance
- * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
- assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
- assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
-
- /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
- TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Configure TI1 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
-
- /* Configure TI2 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
- tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
-
- /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
- tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
- tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
- tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Set encoder mode */
- LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set the fields of the TIMx Hall sensor interface configuration data
- * structure to their default values.
- * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
- * @retval None
- */
-void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
-{
- /* Set the default configuration */
- TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
- TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
- TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
- TIM_HallSensorInitStruct->CommutationDelay = 0U;
-}
-
-/**
- * @brief Configure the Hall sensor interface of the timer instance.
- * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
- * to the TI1 input channel
- * @note TIMx slave mode controller is configured in reset mode.
- Selected internal trigger is TI1F_ED.
- * @note Channel 1 is configured as input, IC1 is mapped on TRC.
- * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
- * between 2 changes on the inputs. It gives information about motor speed.
- * @note Channel 2 is configured in output PWM 2 mode.
- * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
- * @note OC2REF is selected as trigger output on TRGO.
- * @param TIMx Timer Instance
- * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
-{
- uint32_t tmpcr2 = 0U;
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpsmcr = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
- assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
-
- /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
- TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
-
- /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
- tmpcr2 |= TIM_CR2_TI1S;
-
- /* OC2REF signal is used as trigger output (TRGO) */
- tmpcr2 |= LL_TIM_TRGO_OC2REF;
-
- /* Configure the slave mode controller */
- tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
- tmpsmcr |= LL_TIM_TS_TI1F_ED;
- tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
-
- /* Configure input channel 1 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
- tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
- tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
-
- /* Configure input channel 2 */
- tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
- tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
-
- /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
- tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
- tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
- tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx SMCR */
- LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- /* Write to TIMx CCR2 */
- LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
-
- return SUCCESS;
-}
-
-/**
- * @brief Set the fields of the Break and Dead Time configuration data structure
- * to their default values.
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
- * @retval None
- */
-void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
-{
- /* Set the default configuration */
- TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
- TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
- TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
- TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
- TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
- TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
- TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
-}
-
-/**
- * @brief Configure the Break and Dead Time feature of the timer instance.
- * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
- * depending on the LOCK configuration, it can be necessary to configure all of
- * them during the first write access to the TIMx_BDTR register.
- * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
- * a timer instance provides a break input.
- * @param TIMx Timer Instance
- * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Break and Dead Time is initialized
- * - ERROR: not applicable
- */
-ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
-{
- uint32_t tmpbdtr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
- assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
- assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
- assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
- assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
- assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
-
- /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
-
- /* Set the BDTR bits */
- MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
- MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
- MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
- MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
-
- /* Set TIMx_BDTR */
- LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
-
- return SUCCESS;
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
- * @brief Private functions
- * @{
- */
-/**
- * @brief Configure the TIMx output channel 1.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
-
- /* Set the Output Compare Mode */
- MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the complementary output Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
-
- /* Set the complementary output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
-
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
-
- /* Set the complementary output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx output channel 2.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr1 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
-
- /* Select the Output Compare Mode */
- MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the complementary output Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
-
- /* Set the complementary output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
-
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
-
- /* Set the complementary output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR1 */
- LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx output channel 3.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
-
- /* Select the Output Compare Mode */
- MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the complementary output Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
-
- /* Set the complementary output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
-
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
-
- /* Set the complementary output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR2 */
- LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx output channel 4.
- * @param TIMx Timer Instance
- * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
-{
- uint32_t tmpccmr2 = 0U;
- uint32_t tmpccer = 0U;
- uint32_t tmpcr2 = 0U;
-
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
- assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
- assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
-
- /* Get the TIMx CCER register value */
- tmpccer = LL_TIM_ReadReg(TIMx, CCER);
-
- /* Get the TIMx CR2 register value */
- tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
-
- /* Reset Capture/Compare selection Bits */
- CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
-
- /* Select the Output Compare Mode */
- MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
-
- /* Set the Output Compare Polarity */
- MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
-
- /* Set the Output State */
- MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
-
- if (IS_TIM_BREAK_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
- assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
-
- /* Set the Output Idle state */
- MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
- }
-
- /* Write to TIMx CR2 */
- LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
-
- /* Write to TIMx CCMR2 */
- LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
-
- /* Set the Capture Compare Register value */
- LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
-
- /* Write to TIMx CCER */
- LL_TIM_WriteReg(TIMx, CCER, tmpccer);
-
- return SUCCESS;
-}
-
-
-/**
- * @brief Configure the TIMx input channel 1.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC1_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR1,
- (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
-
- /* Select the Polarity and set the CC1E Bit */
- MODIFY_REG(TIMx->CCER,
- (TIM_CCER_CC1P | TIM_CCER_CC1NP),
- (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx input channel 2.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC2_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR1,
- (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
-
- /* Select the Polarity and set the CC2E Bit */
- MODIFY_REG(TIMx->CCER,
- (TIM_CCER_CC2P | TIM_CCER_CC2NP),
- ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx input channel 3.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC3_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR2,
- (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
-
- /* Select the Polarity and set the CC3E Bit */
- MODIFY_REG(TIMx->CCER,
- (TIM_CCER_CC3P | TIM_CCER_CC3NP),
- ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
-
- return SUCCESS;
-}
-
-/**
- * @brief Configure the TIMx input channel 4.
- * @param TIMx Timer Instance
- * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: TIMx registers are de-initialized
- * - ERROR: not applicable
- */
-static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_CC4_INSTANCE(TIMx));
- assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
- assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
- assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
- assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
-
- /* Select the Input and set the filter and the prescaler value */
- MODIFY_REG(TIMx->CCMR2,
- (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
- (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
-
- /* Select the Polarity and set the CC4E Bit */
- MODIFY_REG(TIMx->CCER,
- TIM_CCER_CC4P,
- ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
-
- return SUCCESS;
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
-
-/**
- * @}
- */
-
-#endif /* USE_FULL_LL_DRIVER */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c b/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c
deleted file mode 100644
index d2b47fd63381ca72bf4345f021817960672db08a..0000000000000000000000000000000000000000
--- a/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c
+++ /dev/null
@@ -1,621 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f1xx_ll_utils.c
- * @author MCD Application Team
- * @brief UTILS LL module driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_rcc.h"
-#include "stm32f1xx_ll_utils.h"
-#include "stm32f1xx_ll_system.h"
-#ifdef USE_FULL_ASSERT
-#include "stm32_assert.h"
-#else
-#define assert_param(expr) ((void)0U)
-#endif
-
-/** @addtogroup STM32F1xx_LL_Driver
- * @{
- */
-
-/** @addtogroup UTILS_LL
- * @{
- */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Constants
- * @{
- */
-
-/* Defines used for PLL range */
-#define UTILS_PLL_OUTPUT_MAX RCC_MAX_FREQUENCY /*!< Frequency max for PLL output, in Hz */
-
-/* Defines used for HSE range */
-#define UTILS_HSE_FREQUENCY_MIN RCC_HSE_MIN /*!< Frequency min for HSE frequency, in Hz */
-#define UTILS_HSE_FREQUENCY_MAX RCC_HSE_MAX /*!< Frequency max for HSE frequency, in Hz */
-
-/* Defines used for FLASH latency according to HCLK Frequency */
-#if defined(FLASH_ACR_LATENCY)
-#define UTILS_LATENCY1_FREQ 24000000U /*!< SYSCLK frequency to set FLASH latency 1 */
-#define UTILS_LATENCY2_FREQ 48000000U /*!< SYSCLK frequency to set FLASH latency 2 */
-#else
- /*!< No Latency Configuration in this device */
-#endif
-/**
- * @}
- */
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Private_Macros
- * @{
- */
-#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
- || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
-
-#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
- || ((__VALUE__) == LL_RCC_APB1_DIV_16))
-
-#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
- || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
- || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
- || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
- || ((__VALUE__) == LL_RCC_APB2_DIV_16))
-
-#if defined(RCC_CFGR_PLLMULL6_5)
-#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_4) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_6_5))
-#else
-#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_2) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_3) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_4) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_5) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_6) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_7) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_8) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_9) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_10) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_11) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_12) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_13) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_14) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_15) \
- || ((__VALUE__) == LL_RCC_PLL_MUL_16))
-#endif /* RCC_CFGR_PLLMULL6_5 */
-
-#if defined(RCC_CFGR2_PREDIV1)
-#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_3) || ((__VALUE__) == LL_RCC_PREDIV_DIV_4) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_5) || ((__VALUE__) == LL_RCC_PREDIV_DIV_6) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_7) || ((__VALUE__) == LL_RCC_PREDIV_DIV_8) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_9) || ((__VALUE__) == LL_RCC_PREDIV_DIV_10) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_11) || ((__VALUE__) == LL_RCC_PREDIV_DIV_12) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_13) || ((__VALUE__) == LL_RCC_PREDIV_DIV_14) || \
- ((__VALUE__) == LL_RCC_PREDIV_DIV_15) || ((__VALUE__) == LL_RCC_PREDIV_DIV_16))
-#else
-#define IS_LL_UTILS_PREDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PREDIV_DIV_1) || ((__VALUE__) == LL_RCC_PREDIV_DIV_2))
-#endif /*RCC_PREDIV1_DIV_2_16_SUPPORT*/
-
-#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((__VALUE__) <= UTILS_PLL_OUTPUT_MAX)
-
-
-#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
- || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
-
-#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
-/**
- * @}
- */
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
- * @{
- */
-static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
- LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
-#if defined(FLASH_ACR_LATENCY)
-static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
-#endif /* FLASH_ACR_LATENCY */
-static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-static ErrorStatus UTILS_PLL_IsBusy(void);
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UTILS_LL_Exported_Functions
- * @{
- */
-
-/** @addtogroup UTILS_LL_EF_DELAY
- * @{
- */
-
-/**
- * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
- * @note When a RTOS is used, it is recommended to avoid changing the Systick
- * configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param HCLKFrequency HCLK frequency in Hz
- * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
- * @retval None
- */
-void LL_Init1msTick(uint32_t HCLKFrequency)
-{
- /* Use frequency provided in argument */
- LL_InitTick(HCLKFrequency, 1000U);
-}
-
-/**
- * @brief This function provides accurate delay (in milliseconds) based
- * on SysTick counter flag
- * @note When a RTOS is used, it is recommended to avoid using blocking delay
- * and use rather osDelay service.
- * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
- * will configure Systick to 1ms
- * @param Delay specifies the delay time length, in milliseconds.
- * @retval None
- */
-void LL_mDelay(uint32_t Delay)
-{
- __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
- /* Add this code to indicate that local variable is not used */
- ((void)tmp);
-
- /* Add a period to guaranty minimum wait */
- if (Delay < LL_MAX_DELAY)
- {
- Delay++;
- }
-
- while (Delay)
- {
- if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
- {
- Delay--;
- }
- }
-}
-
-/**
- * @}
- */
-
-/** @addtogroup UTILS_EF_SYSTEM
- * @brief System Configuration functions
- *
- @verbatim
- ===============================================================================
- ##### System Configuration functions #####
- ===============================================================================
- [..]
- System, AHB and APB buses clocks configuration
-
- (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.
- @endverbatim
- @internal
- Depending on the SYSCLK frequency, the flash latency should be adapted accordingly:
- (++) +-----------------------------------------------+
- (++) | Latency | SYSCLK clock frequency (MHz) |
- (++) |---------------|-------------------------------|
- (++) |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
- (++) |---------------|-------------------------------|
- (++) |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
- (++) |---------------|-------------------------------|
- (++) |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
- (++) +-----------------------------------------------+
- @endinternal
- * @{
- */
-
-/**
- * @brief This function sets directly SystemCoreClock CMSIS variable.
- * @note Variable can be calculated also through SystemCoreClockUpdate function.
- * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
- * @retval None
- */
-void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
-{
- /* HCLK clock frequency */
- SystemCoreClock = HCLKFrequency;
-}
-
-/**
- * @brief This function configures system clock with HSI as clock source of the PLL
- * @note The application need to ensure that PLL is disabled.
- * @note Function is based on the following formula:
- * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
- * - PREDIV: Set to 2 for few devices
- * - PLLMUL: The application software must set correctly the PLL multiplication factor to
- * not exceed 72MHz
- * @note FLASH latency can be modified through this function.
- * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
- * the configuration information for the PLL.
- * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
- * the configuration information for the BUS prescalers.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Max frequency configuration done
- * - ERROR: Max frequency configuration not done
- */
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
- LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
- ErrorStatus status = SUCCESS;
- uint32_t pllfreq = 0U;
-
- /* Check if one of the PLL is enabled */
- if (UTILS_PLL_IsBusy() == SUCCESS)
- {
-#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
- /* Check PREDIV value */
- assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
-#else
- /* Force PREDIV value to 2 */
- UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
-#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
- /* Calculate the new PLL output frequency */
- pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
-
- /* Enable HSI if not enabled */
- if (LL_RCC_HSI_IsReady() != 1U)
- {
- LL_RCC_HSI_Enable();
- while (LL_RCC_HSI_IsReady() != 1U)
- {
- /* Wait for HSI ready */
- }
- }
-
- /* Configure PLL */
- LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
-
- /* Enable PLL and switch system clock to PLL */
- status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- }
- else
- {
- /* Current PLL configuration cannot be modified */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @brief This function configures system clock with HSE as clock source of the PLL
- * @note The application need to ensure that PLL is disabled.
- * @note Function is based on the following formula:
- * - PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
- * - PREDIV: Set to 2 for few devices
- * - PLLMUL: The application software must set correctly the PLL multiplication factor to
- * not exceed @ref UTILS_PLL_OUTPUT_MAX
- * @note FLASH latency can be modified through this function.
- * @param HSEFrequency Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
- * @param HSEBypass This parameter can be one of the following values:
- * @arg @ref LL_UTILS_HSEBYPASS_ON
- * @arg @ref LL_UTILS_HSEBYPASS_OFF
- * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
- * the configuration information for the PLL.
- * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
- * the configuration information for the BUS prescalers.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Max frequency configuration done
- * - ERROR: Max frequency configuration not done
- */
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
- LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
- ErrorStatus status = SUCCESS;
- uint32_t pllfreq = 0U;
-
- /* Check the parameters */
- assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
- assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
-
- /* Check if one of the PLL is enabled */
- if (UTILS_PLL_IsBusy() == SUCCESS)
- {
- assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
-
- /* Calculate the new PLL output frequency */
- pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
-
- /* Enable HSE if not enabled */
- if (LL_RCC_HSE_IsReady() != 1U)
- {
- /* Check if need to enable HSE bypass feature or not */
- if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
- {
- LL_RCC_HSE_EnableBypass();
- }
- else
- {
- LL_RCC_HSE_DisableBypass();
- }
-
- /* Enable HSE */
- LL_RCC_HSE_Enable();
- while (LL_RCC_HSE_IsReady() != 1U)
- {
- /* Wait for HSE ready */
- }
- }
-
- /* Configure PLL */
- LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
-
- /* Enable PLL and switch system clock to PLL */
- status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
- }
- else
- {
- /* Current PLL configuration cannot be modified */
- status = ERROR;
- }
-
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @addtogroup UTILS_LL_Private_Functions
- * @{
- */
-/**
- * @brief Update number of Flash wait states in line with new frequency and current
- voltage range.
- * @param Frequency SYSCLK frequency
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: Latency has been modified
- * - ERROR: Latency cannot be modified
- */
-#if defined(FLASH_ACR_LATENCY)
-static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
-{
- ErrorStatus status = SUCCESS;
-
- uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
-
- /* Frequency cannot be equal to 0 */
- if (Frequency == 0U)
- {
- status = ERROR;
- }
- else
- {
- if (Frequency > UTILS_LATENCY2_FREQ)
- {
- /* 48 < SYSCLK <= 72 => 2WS (3 CPU cycles) */
- latency = LL_FLASH_LATENCY_2;
- }
- else
- {
- if (Frequency > UTILS_LATENCY1_FREQ)
- {
- /* 24 < SYSCLK <= 48 => 1WS (2 CPU cycles) */
- latency = LL_FLASH_LATENCY_1;
- }
- /* else SYSCLK < 24MHz default LL_FLASH_LATENCY_0 0WS */
- }
-
- LL_FLASH_SetLatency(latency);
-
- /* Check that the new number of wait states is taken into account to access the Flash
- memory by reading the FLASH_ACR register */
- if (LL_FLASH_GetLatency() != latency)
- {
- status = ERROR;
- }
- }
- return status;
-}
-#endif /* FLASH_ACR_LATENCY */
-
-/**
- * @brief Function to check that PLL can be modified
- * @param PLL_InputFrequency PLL input frequency (in Hz)
- * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
- * the configuration information for the PLL.
- * @retval PLL output frequency (in Hz)
- */
-static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
-{
- uint32_t pllfreq = 0U;
-
- /* Check the parameters */
- assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
-
- /* Check different PLL parameters according to RM */
-#if defined (RCC_CFGR2_PREDIV1)
- pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
-#elif defined(RCC_CFGR2_PREDIV1SRC)
- pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv);
-#else
- pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
-#endif /*RCC_CFGR2_PREDIV1SRC*/
- assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
-
- return pllfreq;
-}
-
-/**
- * @brief Function to check that PLL can be modified
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: PLL modification can be done
- * - ERROR: PLL is busy
- */
-static ErrorStatus UTILS_PLL_IsBusy(void)
-{
- ErrorStatus status = SUCCESS;
-
- /* Check if PLL is busy*/
- if (LL_RCC_PLL_IsReady() != 0U)
- {
- /* PLL configuration cannot be modified */
- status = ERROR;
- }
-#if defined(RCC_PLL2_SUPPORT)
- /* Check if PLL2 is busy*/
- if (LL_RCC_PLL2_IsReady() != 0U)
- {
- /* PLL2 configuration cannot be modified */
- status = ERROR;
- }
-#endif /* RCC_PLL2_SUPPORT */
-
-#if defined(RCC_PLLI2S_SUPPORT)
- /* Check if PLLI2S is busy*/
- if (LL_RCC_PLLI2S_IsReady() != 0U)
- {
- /* PLLI2S configuration cannot be modified */
- status = ERROR;
- }
-#endif /* RCC_PLLI2S_SUPPORT */
-
- return status;
-}
-
-/**
- * @brief Function to enable PLL and switch system clock to PLL
- * @param SYSCLK_Frequency SYSCLK frequency
- * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
- * the configuration information for the BUS prescalers.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: No problem to switch system to PLL
- * - ERROR: Problem to switch system to PLL
- */
-static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
-{
- ErrorStatus status = SUCCESS;
-#if defined(FLASH_ACR_LATENCY)
- uint32_t sysclk_frequency_current = 0U;
-#endif /* FLASH_ACR_LATENCY */
-
- assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
- assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
- assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
-
-#if defined(FLASH_ACR_LATENCY)
- /* Calculate current SYSCLK frequency */
- sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]);
-#endif /* FLASH_ACR_LATENCY */
-
- /* Increasing the number of wait states because of higher CPU frequency */
-#if defined (FLASH_ACR_LATENCY)
- if (sysclk_frequency_current < SYSCLK_Frequency)
- {
- /* Set FLASH latency to highest latency */
- status = UTILS_SetFlashLatency(SYSCLK_Frequency);
- }
-#endif /* FLASH_ACR_LATENCY */
-
- /* Update system clock configuration */
- if (status == SUCCESS)
- {
-#if defined(RCC_PLL2_SUPPORT)
- /* Enable PLL2 */
- LL_RCC_PLL2_Enable();
- while (LL_RCC_PLL2_IsReady() != 1U)
- {
- /* Wait for PLL2 ready */
- }
-
-#endif /* RCC_PLL2_SUPPORT */
- /* Enable PLL */
- LL_RCC_PLL_Enable();
- while (LL_RCC_PLL_IsReady() != 1U)
- {
- /* Wait for PLL ready */
- }
-
- /* Sysclk activation on the main PLL */
- LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
- LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
- while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
- {
- /* Wait for system clock switch to PLL */
- }
-
- /* Set APB1 & APB2 prescaler*/
- LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
- LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
- }
-
- /* Decreasing the number of wait states because of lower CPU frequency */
-#if defined (FLASH_ACR_LATENCY)
- if (sysclk_frequency_current > SYSCLK_Frequency)
- {
- /* Set FLASH latency to lowest latency */
- status = UTILS_SetFlashLatency(SYSCLK_Frequency);
- }
-#endif /* FLASH_ACR_LATENCY */
-
- /* Update SystemCoreClock variable */
- if (status == SUCCESS)
- {
- LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
- }
-
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/led.h b/Inc/led.h
deleted file mode 100644
index ae801a07f036ecc13dec9b4cce036f0996ac6fff..0000000000000000000000000000000000000000
--- a/Inc/led.h
+++ /dev/null
@@ -1,50 +0,0 @@
-#ifndef __LED_H
-#define __LED_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "main.h"
-
-extern volatile uint16_t Led_dataLow;
-extern volatile uint16_t Led_dataHigh;
-extern volatile uint16_t Led_dataUser;
-extern volatile uint8_t Led_dmaBusy;
-
-void Led_Init(void);
-
-__attribute__((always_inline)) static inline void Led_EndHandler(void)
-{
- LL_TIM_DisableCounter(TIM2);
- LL_TIM_SetCounter(TIM2, PERIOD);
- LL_TIM_DisableDMAReq_UPDATE(TIM2);
- LL_TIM_DisableDMAReq_CC1(TIM2);
- LL_TIM_DisableDMAReq_CC2(TIM2);
- LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_2);
- LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_5);
- LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_7);
- LL_DMA_SetMemoryAddress(DMA1, LL_DMA_CHANNEL_5, (uint32_t)spiBufferRead);
- LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_2, LED_NO * 24);
- LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_5, LED_NO * 24);
- LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_7, LED_NO * 24);
- Led_dmaBusy = 0;
-}
-
-__attribute__((always_inline)) static inline void Led_StartHandler(void)
-{
- Led_dmaBusy = 1;
- LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
- LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_5);
- LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_7);
- LL_TIM_EnableDMAReq_UPDATE(TIM2);
- LL_TIM_EnableDMAReq_CC1(TIM2);
- LL_TIM_EnableDMAReq_CC2(TIM2);
- LL_TIM_EnableCounter(TIM2);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MAIN_H */
\ No newline at end of file
diff --git a/Inc/main.h b/Inc/main.h
deleted file mode 100644
index 8eac56c26135475941ddf9307b67723802cf301d..0000000000000000000000000000000000000000
--- a/Inc/main.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
- ******************************************************************************
- * @file : main.h
- * @brief : Header for main.c file.
- * This file contains the common defines of the application.
- ******************************************************************************
- ** This notice applies to any and all portions of this file
- * that are not between comment pairs USER CODE BEGIN and
- * USER CODE END. Other portions of this file, whether
- * inserted by the user or by software development tools
- * are owned by their respective copyright owners.
- *
- * COPYRIGHT(c) 2019 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/* USER CODE END Header */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MAIN_H
-#define __MAIN_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f1xx_ll_dma.h"
-#include "stm32f1xx_ll_rcc.h"
-#include "stm32f1xx_ll_bus.h"
-#include "stm32f1xx_ll_system.h"
-#include "stm32f1xx_ll_exti.h"
-#include "stm32f1xx_ll_cortex.h"
-#include "stm32f1xx_ll_utils.h"
-#include "stm32f1xx_ll_pwr.h"
-#include "stm32f1xx_ll_spi.h"
-#include "stm32f1xx_ll_tim.h"
-#include "stm32f1xx.h"
-#include "stm32f1xx_ll_gpio.h"
-
-#if defined(USE_FULL_ASSERT)
-#include "stm32_assert.h"
-#endif /* USE_FULL_ASSERT */
-
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
-
-/* USER CODE END Includes */
-
-/* Exported types ------------------------------------------------------------*/
-/* USER CODE BEGIN ET */
-
-/* USER CODE END ET */
-
-/* Exported constants --------------------------------------------------------*/
-/* USER CODE BEGIN EC */
-
-/* USER CODE END EC */
-
-/* Exported macro ------------------------------------------------------------*/
-/* USER CODE BEGIN EM */
-
-/* USER CODE END EM */
-
-/* Exported functions prototypes ---------------------------------------------*/
-void Error_Handler(void);
-
-/* USER CODE BEGIN EFP */
-
-/* USER CODE END EFP */
-
-/* Private defines -----------------------------------------------------------*/
-#define PERIOD 108
-#define B1_Pin LL_GPIO_PIN_13
-#define B1_GPIO_Port GPIOC
-#define NSS_Pin LL_GPIO_PIN_12
-#define NSS_GPIO_Port GPIOB
-#define NSS_EXTI_IRQn EXTI15_10_IRQn
-#define MX_Pin LL_GPIO_PIN_8
-#define MX_GPIO_Port GPIOA
-#define TMS_Pin LL_GPIO_PIN_13
-#define TMS_GPIO_Port GPIOA
-#define TCK_Pin LL_GPIO_PIN_14
-#define TCK_GPIO_Port GPIOA
-#define SWO_Pin LL_GPIO_PIN_3
-#define SWO_GPIO_Port GPIOB
-#ifndef NVIC_PRIORITYGROUP_0
-#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority,
- 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority,
- 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
- 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
- 1 bit for subpriority */
-#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
- 0 bit for subpriority */
-#endif
-/* USER CODE BEGIN Private defines */
-#define LED_NO 40
-#define BUFF_SIZE LED_NO*24*2
-extern uint16_t spiBuffer1[BUFF_SIZE];
-extern uint16_t spiBuffer2[BUFF_SIZE];
-extern uint16_t *spiBufferRead;
-extern uint16_t *spiBufferReadNext;
-/* USER CODE END Private defines */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MAIN_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32_assert.h b/Inc/stm32_assert.h
deleted file mode 100644
index 4c9aa9c2754fec6cea08ec68b37ff2562473f5c4..0000000000000000000000000000000000000000
--- a/Inc/stm32_assert.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32_assert.h
- * @brief STM32 assert file.
- ******************************************************************************
- ** This notice applies to any and all portions of this file
- * that are not between comment pairs USER CODE BEGIN and
- * USER CODE END. Other portions of this file, whether
- * inserted by the user or by software development tools
- * are owned by their respective copyright owners.
- *
- * COPYRIGHT(c) 2019 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_ASSERT_H
-#define __STM32_ASSERT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Includes ------------------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function
- * which reports the name of the source file and the source
- * line number of the call that failed.
- * If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32_ASSERT_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32f1xx_it.h b/Inc/stm32f1xx_it.h
deleted file mode 100644
index 27f07030a11e6e0aeb4f614dd52fceaf96050736..0000000000000000000000000000000000000000
--- a/Inc/stm32f1xx_it.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
- ******************************************************************************
- * @file stm32f1xx_it.h
- * @brief This file contains the headers of the interrupt handlers.
- ******************************************************************************
- *
- * COPYRIGHT(c) 2019 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/* USER CODE END Header */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F1xx_IT_H
-#define __STM32F1xx_IT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
-
-/* USER CODE END Includes */
-
-#include "stm32f1xx.h"
-#include "stm32f1xx_ll_system.h"
-#include "stm32f1xx_ll_gpio.h"
-#include "stm32f1xx_ll_exti.h"
-/* Exported types ------------------------------------------------------------*/
-/* USER CODE BEGIN ET */
-
-/* USER CODE END ET */
-
-/* Exported constants --------------------------------------------------------*/
-/* USER CODE BEGIN EC */
-
-/* USER CODE END EC */
-
-/* Exported macro ------------------------------------------------------------*/
-/* USER CODE BEGIN EM */
-
-/* USER CODE END EM */
-
-/* Exported functions prototypes ---------------------------------------------*/
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void DMA1_Channel2_IRQHandler(void);
-void DMA1_Channel4_IRQHandler(void);
-void DMA1_Channel5_IRQHandler(void);
-void DMA1_Channel7_IRQHandler(void);
-void TIM3_IRQHandler(void);
-void EXTI15_10_IRQHandler(void);
-/* USER CODE BEGIN EFP */
-
-/* USER CODE END EFP */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F1xx_IT_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Makefile b/Makefile
deleted file mode 100644
index d9c7e73d7d3d716d3f78ab98f7ea37d3703f31b8..0000000000000000000000000000000000000000
--- a/Makefile
+++ /dev/null
@@ -1,190 +0,0 @@
-##########################################################################################################################
-# File automatically-generated by tool: [projectgenerator] version: [3.0.0] date: [Mon Feb 04 00:09:29 CET 2019]
-##########################################################################################################################
-
-# ------------------------------------------------
-# Generic Makefile (based on gcc)
-#
-# ChangeLog :
-# 2017-02-10 - Several enhancements + project update mode
-# 2015-07-22 - first version
-# ------------------------------------------------
-
-######################################
-# target
-######################################
-TARGET = MiniMatrix
-
-
-######################################
-# building variables
-######################################
-# debug build?
-DEBUG = 1
-# optimization
-OPT = -Og
-
-
-#######################################
-# paths
-#######################################
-# Build path
-BUILD_DIR = build
-
-######################################
-# source
-######################################
-# C sources
-C_SOURCES = \
-Src/main.c \
-Src/stm32f1xx_it.c \
-Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_gpio.c \
-Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_dma.c \
-Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_exti.c \
-Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_tim.c \
-Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_rcc.c \
-Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_utils.c \
-Src/system_stm32f1xx.c \
-Src/led.c \
-Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c \
-Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_pwr.c
-
-# ASM sources
-ASM_SOURCES = \
-startup_stm32f103xb.s
-
-
-#######################################
-# binaries
-#######################################
-PREFIX = arm-none-eabi-
-# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx)
-# either it can be added to the PATH environment variable.
-ifdef GCC_PATH
-CC = $(GCC_PATH)/$(PREFIX)gcc
-AS = $(GCC_PATH)/$(PREFIX)gcc -x assembler-with-cpp
-CP = $(GCC_PATH)/$(PREFIX)objcopy
-SZ = $(GCC_PATH)/$(PREFIX)size
-else
-CC = $(PREFIX)gcc
-AS = $(PREFIX)gcc -x assembler-with-cpp
-CP = $(PREFIX)objcopy
-SZ = $(PREFIX)size
-endif
-HEX = $(CP) -O ihex
-BIN = $(CP) -O binary -S
-
-#######################################
-# CFLAGS
-#######################################
-# cpu
-CPU = -mcpu=cortex-m3
-
-# fpu
-# NONE for Cortex-M0/M0+/M3
-
-# float-abi
-
-
-# mcu
-MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI)
-
-# macros for gcc
-# AS defines
-AS_DEFS =
-
-# C defines
-C_DEFS = \
--DUSE_FULL_LL_DRIVER \
--DSTM32F103xB \
--DHSE_VALUE=8000000 \
--DHSE_STARTUP_TIMEOUT=100 \
--DLSE_STARTUP_TIMEOUT=5000 \
--DLSE_VALUE=32768 \
--DHSI_VALUE=8000000 \
--DLSI_VALUE=40000 \
--DVDD_VALUE=3300 \
--DPREFETCH_ENABLE=1
-
-
-# AS includes
-AS_INCLUDES =
-
-# C includes
-C_INCLUDES = \
--IInc \
--IDrivers/STM32F1xx_HAL_Driver/Inc \
--IDrivers/CMSIS/Device/ST/STM32F1xx/Include \
--IDrivers/CMSIS/Include
-
-
-# compile gcc flags
-ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
-
-CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections
-
-ifeq ($(DEBUG), 1)
-CFLAGS += -g -gdwarf-2
-endif
-
-
-# Generate dependency information
-CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
-
-
-#######################################
-# LDFLAGS
-#######################################
-# link script
-LDSCRIPT = STM32F103RBTx_FLASH.ld
-
-# libraries
-LIBS = -lc -lm -lnosys
-LIBDIR =
-LDFLAGS = $(MCU) -specs=nano.specs -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
-
-# default action: build all
-all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
-
-
-#######################################
-# build the application
-#######################################
-# list of objects
-OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o)))
-vpath %.c $(sort $(dir $(C_SOURCES)))
-# list of ASM program objects
-OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(ASM_SOURCES:.s=.o)))
-vpath %.s $(sort $(dir $(ASM_SOURCES)))
-
-$(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR)
- $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@
-
-$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR)
- $(AS) -c $(CFLAGS) $< -o $@
-
-$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile
- $(CC) $(OBJECTS) $(LDFLAGS) -o $@
- $(SZ) $@
-
-$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
- $(HEX) $< $@
-
-$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR)
- $(BIN) $< $@
-
-$(BUILD_DIR):
- mkdir $@
-
-#######################################
-# clean up
-#######################################
-clean:
- -rm -fR $(BUILD_DIR)
-
-#######################################
-# dependencies
-#######################################
--include $(wildcard $(BUILD_DIR)/*.d)
-
-# *** EOF ***
diff --git a/MiniMatrix.ioc b/MiniMatrix.ioc
deleted file mode 100644
index c6afe21fe2525497e58310f790fb19f82bcbae63..0000000000000000000000000000000000000000
--- a/MiniMatrix.ioc
+++ /dev/null
@@ -1,213 +0,0 @@
-#MicroXplorer Configuration settings - do not modify
-Dma.Request0=TIM2_UP
-Dma.Request1=TIM2_CH1
-Dma.Request2=TIM2_CH2/CH4
-Dma.Request3=SPI2_RX
-Dma.RequestsNb=4
-Dma.SPI2_RX.3.Direction=DMA_PERIPH_TO_MEMORY
-Dma.SPI2_RX.3.Instance=DMA1_Channel4
-Dma.SPI2_RX.3.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
-Dma.SPI2_RX.3.MemInc=DMA_MINC_ENABLE
-Dma.SPI2_RX.3.Mode=DMA_NORMAL
-Dma.SPI2_RX.3.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
-Dma.SPI2_RX.3.PeriphInc=DMA_PINC_DISABLE
-Dma.SPI2_RX.3.Priority=DMA_PRIORITY_LOW
-Dma.SPI2_RX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
-Dma.TIM2_CH1.1.Direction=DMA_MEMORY_TO_PERIPH
-Dma.TIM2_CH1.1.Instance=DMA1_Channel5
-Dma.TIM2_CH1.1.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
-Dma.TIM2_CH1.1.MemInc=DMA_MINC_ENABLE
-Dma.TIM2_CH1.1.Mode=DMA_NORMAL
-Dma.TIM2_CH1.1.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
-Dma.TIM2_CH1.1.PeriphInc=DMA_PINC_DISABLE
-Dma.TIM2_CH1.1.Priority=DMA_PRIORITY_MEDIUM
-Dma.TIM2_CH1.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
-Dma.TIM2_CH2/CH4.2.Direction=DMA_MEMORY_TO_PERIPH
-Dma.TIM2_CH2/CH4.2.Instance=DMA1_Channel7
-Dma.TIM2_CH2/CH4.2.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
-Dma.TIM2_CH2/CH4.2.MemInc=DMA_MINC_DISABLE
-Dma.TIM2_CH2/CH4.2.Mode=DMA_NORMAL
-Dma.TIM2_CH2/CH4.2.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
-Dma.TIM2_CH2/CH4.2.PeriphInc=DMA_PINC_DISABLE
-Dma.TIM2_CH2/CH4.2.Priority=DMA_PRIORITY_MEDIUM
-Dma.TIM2_CH2/CH4.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
-Dma.TIM2_UP.0.Direction=DMA_MEMORY_TO_PERIPH
-Dma.TIM2_UP.0.Instance=DMA1_Channel2
-Dma.TIM2_UP.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
-Dma.TIM2_UP.0.MemInc=DMA_MINC_DISABLE
-Dma.TIM2_UP.0.Mode=DMA_NORMAL
-Dma.TIM2_UP.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
-Dma.TIM2_UP.0.PeriphInc=DMA_PINC_DISABLE
-Dma.TIM2_UP.0.Priority=DMA_PRIORITY_MEDIUM
-Dma.TIM2_UP.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
-File.Version=6
-KeepUserPlacement=true
-Mcu.Family=STM32F1
-Mcu.IP0=DMA
-Mcu.IP1=NVIC
-Mcu.IP2=RCC
-Mcu.IP3=SPI2
-Mcu.IP4=SYS
-Mcu.IP5=TIM2
-Mcu.IP6=TIM3
-Mcu.IPNb=7
-Mcu.Name=STM32F103R(8-B)Tx
-Mcu.Package=LQFP64
-Mcu.Pin0=PC13-TAMPER-RTC
-Mcu.Pin1=PB12
-Mcu.Pin10=VP_TIM2_VS_ClockSourceINT
-Mcu.Pin11=VP_TIM2_VS_no_output1
-Mcu.Pin12=VP_TIM2_VS_no_output2
-Mcu.Pin13=VP_TIM3_VS_ClockSourceINT
-Mcu.Pin2=PB13
-Mcu.Pin3=PB14
-Mcu.Pin4=PB15
-Mcu.Pin5=PA8
-Mcu.Pin6=PA13
-Mcu.Pin7=PA14
-Mcu.Pin8=PB3
-Mcu.Pin9=VP_SYS_VS_Systick
-Mcu.PinsNb=14
-Mcu.ThirdPartyNb=0
-Mcu.UserConstants=PERIOD,108
-Mcu.UserName=STM32F103RBTx
-MxCube.Version=5.0.1
-MxDb.Version=DB.5.0.1
-NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true
-NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:false
-NVIC.DMA1_Channel4_IRQn=true\:0\:0\:false\:false\:true\:false
-NVIC.DMA1_Channel5_IRQn=true\:0\:0\:false\:false\:true\:false
-NVIC.DMA1_Channel7_IRQn=true\:0\:0\:false\:false\:true\:false
-NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true
-NVIC.EXTI15_10_IRQn=true\:0\:0\:false\:false\:true\:true
-NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true
-NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true
-NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true
-NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true
-NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
-NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true
-NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true
-NVIC.TIM3_IRQn=true\:0\:0\:false\:false\:true\:true
-NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true
-PA13.GPIOParameters=GPIO_Label
-PA13.GPIO_Label=TMS
-PA13.Locked=true
-PA13.Mode=Trace_Asynchronous_SW
-PA13.Signal=SYS_JTMS-SWDIO
-PA14.GPIOParameters=GPIO_Label
-PA14.GPIO_Label=TCK
-PA14.Locked=true
-PA14.Mode=Trace_Asynchronous_SW
-PA14.Signal=SYS_JTCK-SWCLK
-PA8.GPIOParameters=GPIO_Speed,GPIO_Label,GPIO_ModeDefaultOutputPP
-PA8.GPIO_Label=MX
-PA8.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
-PA8.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
-PA8.Locked=true
-PA8.Signal=GPIO_Output
-PB12.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI
-PB12.GPIO_Label=NSS
-PB12.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING
-PB12.Locked=true
-PB12.Signal=GPXTI12
-PB13.Mode=Full_Duplex_Slave
-PB13.Signal=SPI2_SCK
-PB14.Mode=Full_Duplex_Slave
-PB14.Signal=SPI2_MISO
-PB15.Mode=Full_Duplex_Slave
-PB15.Signal=SPI2_MOSI
-PB3.GPIOParameters=GPIO_Label
-PB3.GPIO_Label=SWO
-PB3.Locked=true
-PB3.Mode=Trace_Asynchronous_SW
-PB3.Signal=SYS_JTDO-TRACESWO
-PC13-TAMPER-RTC.GPIOParameters=GPIO_Label
-PC13-TAMPER-RTC.GPIO_Label=B1
-PC13-TAMPER-RTC.Locked=true
-PC13-TAMPER-RTC.Signal=GPIO_Input
-PCC.Checker=false
-PCC.Line=STM32F103
-PCC.MCU=STM32F103R(8-B)Tx
-PCC.PartNumber=STM32F103RBTx
-PCC.Seq0=0
-PCC.Series=STM32F1
-PCC.Temperature=25
-PCC.Vdd=3.3
-PinOutPanel.RotationAngle=0
-ProjectManager.AskForMigrate=true
-ProjectManager.BackupPrevious=false
-ProjectManager.CompilerOptimize=6
-ProjectManager.ComputerToolchain=false
-ProjectManager.CoupleFile=false
-ProjectManager.CustomerFirmwarePackage=
-ProjectManager.DefaultFWLocation=true
-ProjectManager.DeletePrevious=true
-ProjectManager.DeviceId=STM32F103RBTx
-ProjectManager.FirmwarePackage=STM32Cube FW_F1 V1.7.0
-ProjectManager.FreePins=false
-ProjectManager.HalAssertFull=false
-ProjectManager.HeapSize=0x200
-ProjectManager.KeepUserCode=true
-ProjectManager.LastFirmware=true
-ProjectManager.LibraryCopy=1
-ProjectManager.MainLocation=Src
-ProjectManager.NoMain=false
-ProjectManager.PreviousToolchain=
-ProjectManager.ProjectBuild=false
-ProjectManager.ProjectFileName=MiniMatrix.ioc
-ProjectManager.ProjectName=MiniMatrix
-ProjectManager.StackSize=0x400
-ProjectManager.TargetToolchain=Makefile
-ProjectManager.ToolChainLocation=
-ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-MX_DMA_Init-DMA-false-LL-true,3-SystemClock_Config-RCC-false-LL-false,4-MX_TIM2_Init-TIM2-false-LL-true,5-MX_TIM3_Init-TIM3-false-LL-true,6-MX_SPI2_Init-SPI2-false-LL-true
-RCC.ADCFreqValue=32000000
-RCC.AHBFreq_Value=64000000
-RCC.APB1CLKDivider=RCC_HCLK_DIV2
-RCC.APB1Freq_Value=32000000
-RCC.APB1TimFreq_Value=64000000
-RCC.APB2Freq_Value=64000000
-RCC.APB2TimFreq_Value=64000000
-RCC.FCLKCortexFreq_Value=64000000
-RCC.FamilyName=M
-RCC.HCLKFreq_Value=64000000
-RCC.IPParameters=ADCFreqValue,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,PLLMUL,RTCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TimSysFreq_Value,USBFreq_Value,VCOOutput2Freq_Value
-RCC.MCOFreq_Value=64000000
-RCC.PLLCLKFreq_Value=64000000
-RCC.PLLMCOFreq_Value=32000000
-RCC.PLLMUL=RCC_PLL_MUL16
-RCC.RTCFreq_Value=40000
-RCC.SYSCLKFreq_VALUE=64000000
-RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
-RCC.TimSysFreq_Value=64000000
-RCC.USBFreq_Value=64000000
-RCC.VCOOutput2Freq_Value=4000000
-SH.GPXTI12.0=GPIO_EXTI12
-SH.GPXTI12.ConfNb=1
-SPI2.CalculateBaudRate=16.0 MBits/s
-SPI2.DataSize=SPI_DATASIZE_16BIT
-SPI2.Direction=SPI_DIRECTION_2LINES
-SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize
-SPI2.Mode=SPI_MODE_SLAVE
-SPI2.VirtualType=VM_SLAVE
-TIM2.Channel-Output\ Compare1\ No\ Output=TIM_CHANNEL_1
-TIM2.Channel-Output\ Compare2\ No\ Output=TIM_CHANNEL_2
-TIM2.IPParameters=Channel-Output Compare1 No Output,Channel-Output Compare2 No Output,Period,Pulse-Output Compare1 No Output,Pulse-Output Compare2 No Output
-TIM2.Period=PERIOD
-TIM2.Pulse-Output\ Compare1\ No\ Output=22
-TIM2.Pulse-Output\ Compare2\ No\ Output=87
-TIM3.IPParameters=Period,Prescaler
-TIM3.Period=6399
-TIM3.Prescaler=165
-VP_SYS_VS_Systick.Mode=SysTick
-VP_SYS_VS_Systick.Signal=SYS_VS_Systick
-VP_TIM2_VS_ClockSourceINT.Mode=Internal
-VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT
-VP_TIM2_VS_no_output1.Mode=Output Compare1 No Output
-VP_TIM2_VS_no_output1.Signal=TIM2_VS_no_output1
-VP_TIM2_VS_no_output2.Mode=Output Compare2 No Output
-VP_TIM2_VS_no_output2.Signal=TIM2_VS_no_output2
-VP_TIM3_VS_ClockSourceINT.Mode=Internal
-VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT
-board=NUCLEO-F103RB
-boardIOC=true
diff --git a/STM32F103RBTx_FLASH.ld b/STM32F103RBTx_FLASH.ld
deleted file mode 100644
index e625e1389fd197bd5167de57062bf4ceda96745b..0000000000000000000000000000000000000000
--- a/STM32F103RBTx_FLASH.ld
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-*****************************************************************************
-**
-
-** File : LinkerScript.ld
-**
-** Abstract : Linker script for STM32F103RBTx Device with
-** 128KByte FLASH, 20KByte RAM
-**
-** Set heap size, stack size and stack location according
-** to application requirements.
-**
-** Set memory bank area and size if external memory is used.
-**
-** Target : STMicroelectronics STM32
-**
-**
-** Distribution: The file is distributed as is, without any warranty
-** of any kind.
-**
-** (c)Copyright Ac6.
-** You may use this file as-is or modify it according to the needs of your
-** project. Distribution of this file (unmodified or modified) is not
-** permitted. Ac6 permit registered System Workbench for MCU users the
-** rights to distribute the assembled, compiled & linked contents of this
-** file as part of an application binary file, provided that it is built
-** using the System Workbench for MCU toolchain.
-**
-*****************************************************************************
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = 0x20005000; /* end of RAM */
-/* Generate a link error if heap and stack don't fit into RAM */
-_Min_Heap_Size = 0x200; /* required amount of heap */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Specify the memory areas */
-MEMORY
-{
-RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
-FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K
-}
-
-/* Define output sections */
-SECTIONS
-{
- /* The startup code goes first into FLASH */
- .isr_vector :
- {
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } >FLASH
-
- /* The program code and other data goes into FLASH */
- .text :
- {
- . = ALIGN(4);
- *(.text) /* .text sections (code) */
- *(.text*) /* .text* sections (code) */
- *(.glue_7) /* glue arm to thumb code */
- *(.glue_7t) /* glue thumb to arm code */
- *(.eh_frame)
-
- KEEP (*(.init))
- KEEP (*(.fini))
-
- . = ALIGN(4);
- _etext = .; /* define a global symbols at end of code */
- } >FLASH
-
- /* Constant data goes into FLASH */
- .rodata :
- {
- . = ALIGN(4);
- *(.rodata) /* .rodata sections (constants, strings, etc.) */
- *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
- . = ALIGN(4);
- } >FLASH
-
- .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
- .ARM : {
- __exidx_start = .;
- *(.ARM.exidx*)
- __exidx_end = .;
- } >FLASH
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array*))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >FLASH
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array*))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >FLASH
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT(.fini_array.*)))
- KEEP (*(.fini_array*))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >FLASH
-
- /* used by the startup to initialize data */
- _sidata = LOADADDR(.data);
-
- /* Initialized data sections goes into RAM, load LMA copy after code */
- .data :
- {
- . = ALIGN(4);
- _sdata = .; /* create a global symbol at data start */
- *(.data) /* .data sections */
- *(.data*) /* .data* sections */
-
- . = ALIGN(4);
- _edata = .; /* define a global symbol at data end */
- } >RAM AT> FLASH
-
-
- /* Uninitialized data section */
- . = ALIGN(4);
- .bss :
- {
- /* This is used by the startup in order to initialize the .bss secion */
- _sbss = .; /* define a global symbol at bss start */
- __bss_start__ = _sbss;
- *(.bss)
- *(.bss*)
- *(COMMON)
-
- . = ALIGN(4);
- _ebss = .; /* define a global symbol at bss end */
- __bss_end__ = _ebss;
- } >RAM
-
- /* User_heap_stack section, used to check that there is enough RAM left */
- ._user_heap_stack :
- {
- . = ALIGN(8);
- PROVIDE ( end = . );
- PROVIDE ( _end = . );
- . = . + _Min_Heap_Size;
- . = . + _Min_Stack_Size;
- . = ALIGN(8);
- } >RAM
-
-
-
- /* Remove information from the standard libraries */
- /DISCARD/ :
- {
- libc.a ( * )
- libm.a ( * )
- libgcc.a ( * )
- }
-
- .ARM.attributes 0 : { *(.ARM.attributes) }
-}
-
-
diff --git a/Src/led.c b/Src/led.c
deleted file mode 100644
index 89a0f8a81029910a2761a84598497cfe2d9c5a32..0000000000000000000000000000000000000000
--- a/Src/led.c
+++ /dev/null
@@ -1,30 +0,0 @@
-#include "led.h"
-
-volatile uint16_t Led_dataLow = 0x0000;
-volatile uint16_t Led_dataUser = 0x0000;
-volatile uint16_t Led_dataHigh = 0x0100;
-volatile uint8_t Led_dmaBusy = 0;
-
-void Led_Init(void)
-{
- LL_DMA_SetPeriphAddress(DMA1, LL_DMA_CHANNEL_2, (uint32_t)&GPIOA->ODR);
- LL_DMA_SetPeriphAddress(DMA1, LL_DMA_CHANNEL_5, (uint32_t)&GPIOA->ODR);
- LL_DMA_SetPeriphAddress(DMA1, LL_DMA_CHANNEL_7, (uint32_t)&GPIOA->ODR);
- LL_DMA_SetMemoryAddress(DMA1, LL_DMA_CHANNEL_2, (uint32_t)&Led_dataHigh);
- LL_DMA_SetMemoryAddress(DMA1, LL_DMA_CHANNEL_5, (uint32_t)spiBufferRead);
- LL_DMA_SetMemoryAddress(DMA1, LL_DMA_CHANNEL_7, (uint32_t)&Led_dataLow);
- LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_2, LED_NO * 24);
- LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_5, LED_NO * 24);
- LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_7, LED_NO * 24);
- LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_7);
- LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_2);
- LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_5);
- LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_7);
- LL_TIM_EnableDMAReq_UPDATE(TIM2);
- LL_TIM_EnableDMAReq_CC1(TIM2);
- LL_TIM_EnableDMAReq_CC2(TIM2);
- LL_TIM_SetCounter(TIM2, PERIOD);
- LL_TIM_EnableIT_UPDATE(TIM3);
- //LL_TIM_EnableCounter(TIM3);
-}
-
diff --git a/Src/main.c b/Src/main.c
deleted file mode 100644
index d1768eb76c22d2883df0e45bb0d2c1398199971a..0000000000000000000000000000000000000000
--- a/Src/main.c
+++ /dev/null
@@ -1,522 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
- ******************************************************************************
- * @file : main.c
- * @brief : Main program body
- ******************************************************************************
- ** This notice applies to any and all portions of this file
- * that are not between comment pairs USER CODE BEGIN and
- * USER CODE END. Other portions of this file, whether
- * inserted by the user or by software development tools
- * are owned by their respective copyright owners.
- *
- * COPYRIGHT(c) 2019 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/* USER CODE END Header */
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
-#include "led.h"
-/* USER CODE END Includes */
-
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN PTD */
-
-/* USER CODE END PTD */
-
-/* Private define ------------------------------------------------------------*/
-/* USER CODE BEGIN PD */
-
-/* USER CODE END PD */
-
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN PM */
-
-/* USER CODE END PM */
-
-/* Private variables ---------------------------------------------------------*/
-
-/* USER CODE BEGIN PV */
-uint16_t spiBuffer1[BUFF_SIZE] = {0};
-uint16_t spiBuffer2[BUFF_SIZE] = {0};
-uint16_t *spiBufferRead = spiBuffer1;
-uint16_t *spiBufferReadNext = spiBuffer2;
-/* USER CODE END PV */
-
-/* Private function prototypes -----------------------------------------------*/
-void SystemClock_Config(void);
-static void MX_GPIO_Init(void);
-static void MX_DMA_Init(void);
-static void MX_TIM2_Init(void);
-static void MX_TIM3_Init(void);
-static void MX_SPI2_Init(void);
-/* USER CODE BEGIN PFP */
-
-/* USER CODE END PFP */
-
-/* Private user code ---------------------------------------------------------*/
-/* USER CODE BEGIN 0 */
-
-/* USER CODE END 0 */
-
-/**
- * @brief The application entry point.
- * @retval int
- */
-int main(void)
-{
- /* USER CODE BEGIN 1 */
-
- /* USER CODE END 1 */
-
- /* MCU Configuration--------------------------------------------------------*/
-
- /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
-
-
- LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
- LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
-
- NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
- /* System interrupt init*/
-
- /**NOJTAG: JTAG-DP Disabled and SW-DP Enabled
- */
- LL_GPIO_AF_Remap_SWJ_NOJTAG();
-
- /* USER CODE BEGIN Init */
-
- /* USER CODE END Init */
-
- /* Configure the system clock */
- SystemClock_Config();
-
- /* USER CODE BEGIN SysInit */
-
- /* USER CODE END SysInit */
-
- /* Initialize all configured peripherals */
- MX_GPIO_Init();
- MX_DMA_Init();
- MX_TIM2_Init();
- MX_TIM3_Init();
- MX_SPI2_Init();
- /* USER CODE BEGIN 2 */
- Led_Init();
- LL_DMA_SetPeriphAddress(DMA1, LL_DMA_CHANNEL_4, (uint32_t)&SPI2->DR);
- LL_DMA_SetMemoryAddress(DMA1, LL_DMA_CHANNEL_4, (uint32_t)spiBufferReadNext);
- LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_4, BUFF_SIZE);
- LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_4);
- LL_SPI_EnableDMAReq_RX(SPI2);
- LL_SPI_Enable(SPI2);
- LL_TIM_EnableCounter(TIM3);
- /* USER CODE END 2 */
-
- /* Infinite loop */
- /* USER CODE BEGIN WHILE */
- while (1)
- {
- if(Led_dmaBusy == 0)
- {
- if(LL_GPIO_IsInputPinSet(B1_GPIO_Port, B1_Pin))
- {
- Led_dataUser = 0x0000;
- }
- else
- {
- Led_dataUser = 0x0100;
- }
- }
- /* USER CODE END WHILE */
-
- /* USER CODE BEGIN 3 */
- }
- /* USER CODE END 3 */
-}
-
-/**
- * @brief System Clock Configuration
- * @retval None
- */
-void SystemClock_Config(void)
-{
- LL_FLASH_SetLatency(LL_FLASH_LATENCY_2);
-
- if(LL_FLASH_GetLatency() != LL_FLASH_LATENCY_2)
- {
- Error_Handler();
- }
- LL_RCC_HSI_SetCalibTrimming(16);
- LL_RCC_HSI_Enable();
-
- /* Wait till HSI is ready */
- while(LL_RCC_HSI_IsReady() != 1)
- {
-
- }
- LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, LL_RCC_PLL_MUL_16);
- LL_RCC_PLL_Enable();
-
- /* Wait till PLL is ready */
- while(LL_RCC_PLL_IsReady() != 1)
- {
-
- }
- LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
- LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
- LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
- LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
-
- /* Wait till System clock is ready */
- while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
- {
-
- }
- LL_Init1msTick(64000000);
- LL_SYSTICK_SetClkSource(LL_SYSTICK_CLKSOURCE_HCLK);
- LL_SetSystemCoreClock(64000000);
-}
-
-/**
- * @brief SPI2 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_SPI2_Init(void)
-{
-
- /* USER CODE BEGIN SPI2_Init 0 */
-
- /* USER CODE END SPI2_Init 0 */
-
- LL_SPI_InitTypeDef SPI_InitStruct = {0};
-
- LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
-
- /* Peripheral clock enable */
- LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2);
-
- LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOB);
- /**SPI2 GPIO Configuration
- PB13 ------> SPI2_SCK
- PB14 ------> SPI2_MISO
- PB15 ------> SPI2_MOSI
- */
- GPIO_InitStruct.Pin = LL_GPIO_PIN_13|LL_GPIO_PIN_15;
- GPIO_InitStruct.Mode = LL_GPIO_MODE_FLOATING;
- LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
- GPIO_InitStruct.Pin = LL_GPIO_PIN_14;
- GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
- GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
- GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
- LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
- /* SPI2 DMA Init */
-
- /* SPI2_RX Init */
- LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_4, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
-
- LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_4, LL_DMA_PRIORITY_LOW);
-
- LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_4, LL_DMA_MODE_NORMAL);
-
- LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_4, LL_DMA_PERIPH_NOINCREMENT);
-
- LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_4, LL_DMA_MEMORY_INCREMENT);
-
- LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_4, LL_DMA_PDATAALIGN_HALFWORD);
-
- LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_4, LL_DMA_MDATAALIGN_HALFWORD);
-
- /* USER CODE BEGIN SPI2_Init 1 */
-
- /* USER CODE END SPI2_Init 1 */
- /* SPI2 parameter configuration*/
- SPI_InitStruct.TransferDirection = LL_SPI_FULL_DUPLEX;
- SPI_InitStruct.Mode = LL_SPI_MODE_SLAVE;
- SPI_InitStruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
- SPI_InitStruct.ClockPolarity = LL_SPI_POLARITY_LOW;
- SPI_InitStruct.ClockPhase = LL_SPI_PHASE_1EDGE;
- SPI_InitStruct.NSS = LL_SPI_NSS_SOFT;
- SPI_InitStruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
- SPI_InitStruct.BitOrder = LL_SPI_MSB_FIRST;
- SPI_InitStruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
- SPI_InitStruct.CRCPoly = 10;
- LL_SPI_Init(SPI2, &SPI_InitStruct);
- /* USER CODE BEGIN SPI2_Init 2 */
-
- /* USER CODE END SPI2_Init 2 */
-
-}
-
-/**
- * @brief TIM2 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM2_Init(void)
-{
-
- /* USER CODE BEGIN TIM2_Init 0 */
-
- /* USER CODE END TIM2_Init 0 */
-
- LL_TIM_InitTypeDef TIM_InitStruct = {0};
- LL_TIM_OC_InitTypeDef TIM_OC_InitStruct = {0};
-
- /* Peripheral clock enable */
- LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
-
- /* TIM2 DMA Init */
-
- /* TIM2_UP Init */
- LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_2, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
-
- LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_2, LL_DMA_PRIORITY_MEDIUM);
-
- LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MODE_NORMAL);
-
- LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_2, LL_DMA_PERIPH_NOINCREMENT);
-
- LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MEMORY_NOINCREMENT);
-
- LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_2, LL_DMA_PDATAALIGN_HALFWORD);
-
- LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MDATAALIGN_HALFWORD);
-
- /* TIM2_CH1 Init */
- LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_5, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
-
- LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_5, LL_DMA_PRIORITY_MEDIUM);
-
- LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_5, LL_DMA_MODE_NORMAL);
-
- LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_5, LL_DMA_PERIPH_NOINCREMENT);
-
- LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_5, LL_DMA_MEMORY_INCREMENT);
-
- LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_5, LL_DMA_PDATAALIGN_HALFWORD);
-
- LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_5, LL_DMA_MDATAALIGN_HALFWORD);
-
- /* TIM2_CH2_CH4 Init */
- LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_7, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
-
- LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_7, LL_DMA_PRIORITY_MEDIUM);
-
- LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_7, LL_DMA_MODE_NORMAL);
-
- LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_7, LL_DMA_PERIPH_NOINCREMENT);
-
- LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_7, LL_DMA_MEMORY_NOINCREMENT);
-
- LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_7, LL_DMA_PDATAALIGN_HALFWORD);
-
- LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_7, LL_DMA_MDATAALIGN_HALFWORD);
-
- /* USER CODE BEGIN TIM2_Init 1 */
-
- /* USER CODE END TIM2_Init 1 */
- TIM_InitStruct.Prescaler = 0;
- TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
- TIM_InitStruct.Autoreload = PERIOD;
- TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- LL_TIM_Init(TIM2, &TIM_InitStruct);
- LL_TIM_DisableARRPreload(TIM2);
- LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL);
- TIM_OC_InitStruct.OCMode = LL_TIM_OCMODE_FROZEN;
- TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE;
- TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE;
- TIM_OC_InitStruct.CompareValue = 22;
- TIM_OC_InitStruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH;
- LL_TIM_OC_Init(TIM2, LL_TIM_CHANNEL_CH1, &TIM_OC_InitStruct);
- LL_TIM_OC_DisableFast(TIM2, LL_TIM_CHANNEL_CH1);
- TIM_OC_InitStruct.OCState = LL_TIM_OCSTATE_DISABLE;
- TIM_OC_InitStruct.OCNState = LL_TIM_OCSTATE_DISABLE;
- TIM_OC_InitStruct.CompareValue = 87;
- LL_TIM_OC_Init(TIM2, LL_TIM_CHANNEL_CH2, &TIM_OC_InitStruct);
- LL_TIM_OC_DisableFast(TIM2, LL_TIM_CHANNEL_CH2);
- LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_RESET);
- LL_TIM_DisableMasterSlaveMode(TIM2);
- /* USER CODE BEGIN TIM2_Init 2 */
-
- /* USER CODE END TIM2_Init 2 */
-
-}
-
-/**
- * @brief TIM3 Initialization Function
- * @param None
- * @retval None
- */
-static void MX_TIM3_Init(void)
-{
-
- /* USER CODE BEGIN TIM3_Init 0 */
-
- /* USER CODE END TIM3_Init 0 */
-
- LL_TIM_InitTypeDef TIM_InitStruct = {0};
-
- /* Peripheral clock enable */
- LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3);
-
- /* TIM3 interrupt Init */
- NVIC_SetPriority(TIM3_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
- NVIC_EnableIRQ(TIM3_IRQn);
-
- /* USER CODE BEGIN TIM3_Init 1 */
-
- /* USER CODE END TIM3_Init 1 */
- TIM_InitStruct.Prescaler = 165;
- TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
- TIM_InitStruct.Autoreload = 6399;
- TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
- LL_TIM_Init(TIM3, &TIM_InitStruct);
- LL_TIM_DisableARRPreload(TIM3);
- LL_TIM_SetClockSource(TIM3, LL_TIM_CLOCKSOURCE_INTERNAL);
- LL_TIM_SetTriggerOutput(TIM3, LL_TIM_TRGO_RESET);
- LL_TIM_DisableMasterSlaveMode(TIM3);
- /* USER CODE BEGIN TIM3_Init 2 */
-
- /* USER CODE END TIM3_Init 2 */
-
-}
-
-/**
- * Enable DMA controller clock
- */
-static void MX_DMA_Init(void)
-{
- /* Init with LL driver */
- /* DMA controller clock enable */
- LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
-
- /* DMA interrupt init */
- /* DMA1_Channel2_IRQn interrupt configuration */
- NVIC_SetPriority(DMA1_Channel2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
- NVIC_EnableIRQ(DMA1_Channel2_IRQn);
- /* DMA1_Channel4_IRQn interrupt configuration */
- NVIC_SetPriority(DMA1_Channel4_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
- NVIC_EnableIRQ(DMA1_Channel4_IRQn);
- /* DMA1_Channel5_IRQn interrupt configuration */
- NVIC_SetPriority(DMA1_Channel5_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
- NVIC_EnableIRQ(DMA1_Channel5_IRQn);
- /* DMA1_Channel7_IRQn interrupt configuration */
- NVIC_SetPriority(DMA1_Channel7_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
- NVIC_EnableIRQ(DMA1_Channel7_IRQn);
-
-}
-
-/**
- * @brief GPIO Initialization Function
- * @param None
- * @retval None
- */
-static void MX_GPIO_Init(void)
-{
- LL_EXTI_InitTypeDef EXTI_InitStruct = {0};
- LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
-
- /* GPIO Ports Clock Enable */
- LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOC);
- LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOB);
- LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOA);
-
- /**/
- LL_GPIO_ResetOutputPin(MX_GPIO_Port, MX_Pin);
-
- /**/
- GPIO_InitStruct.Pin = B1_Pin;
- GPIO_InitStruct.Mode = LL_GPIO_MODE_FLOATING;
- LL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
-
- /**/
- GPIO_InitStruct.Pin = MX_Pin;
- GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
- GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_HIGH;
- GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
- LL_GPIO_Init(MX_GPIO_Port, &GPIO_InitStruct);
-
- /**/
- LL_GPIO_AF_SetEXTISource(LL_GPIO_AF_EXTI_PORTB, LL_GPIO_AF_EXTI_LINE12);
-
- /**/
- EXTI_InitStruct.Line_0_31 = LL_EXTI_LINE_12;
- EXTI_InitStruct.LineCommand = ENABLE;
- EXTI_InitStruct.Mode = LL_EXTI_MODE_IT;
- EXTI_InitStruct.Trigger = LL_EXTI_TRIGGER_RISING;
- LL_EXTI_Init(&EXTI_InitStruct);
-
- /**/
- LL_GPIO_SetPinMode(NSS_GPIO_Port, NSS_Pin, LL_GPIO_MODE_FLOATING);
-
- /* EXTI interrupt init*/
- NVIC_SetPriority(EXTI15_10_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
- NVIC_EnableIRQ(EXTI15_10_IRQn);
-
-}
-
-/* USER CODE BEGIN 4 */
-
-/* USER CODE END 4 */
-
-/**
- * @brief This function is executed in case of error occurrence.
- * @retval None
- */
-void Error_Handler(void)
-{
- /* USER CODE BEGIN Error_Handler_Debug */
- /* User can add his own implementation to report the HAL error return state */
-
- /* USER CODE END Error_Handler_Debug */
-}
-
-#ifdef USE_FULL_ASSERT
-/**
- * @brief Reports the name of the source file and the source line number
- * where the assert_param error has occurred.
- * @param file: pointer to the source file name
- * @param line: assert_param error line source number
- * @retval None
- */
-void assert_failed(uint8_t *file, uint32_t line)
-{
- /* USER CODE BEGIN 6 */
- /* User can add his own implementation to report the file name and line number,
- tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
- /* USER CODE END 6 */
-}
-#endif /* USE_FULL_ASSERT */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32f1xx_it.c b/Src/stm32f1xx_it.c
deleted file mode 100644
index 2f97dff06479ec9a367c4b0d62ab51877470433f..0000000000000000000000000000000000000000
--- a/Src/stm32f1xx_it.c
+++ /dev/null
@@ -1,315 +0,0 @@
-/* USER CODE BEGIN Header */
-/**
- ******************************************************************************
- * @file stm32f1xx_it.c
- * @brief Interrupt Service Routines.
- ******************************************************************************
- *
- * COPYRIGHT(c) 2019 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/* USER CODE END Header */
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-#include "stm32f1xx_it.h"
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
-#include "led.h"
-/* USER CODE END Includes */
-
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN TD */
-
-/* USER CODE END TD */
-
-/* Private define ------------------------------------------------------------*/
-/* USER CODE BEGIN PD */
-
-/* USER CODE END PD */
-
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN PM */
-
-/* USER CODE END PM */
-
-/* Private variables ---------------------------------------------------------*/
-/* USER CODE BEGIN PV */
-
-/* USER CODE END PV */
-
-/* Private function prototypes -----------------------------------------------*/
-/* USER CODE BEGIN PFP */
-
-/* USER CODE END PFP */
-
-/* Private user code ---------------------------------------------------------*/
-/* USER CODE BEGIN 0 */
-
-/* USER CODE END 0 */
-
-/* External variables --------------------------------------------------------*/
-/* USER CODE BEGIN EV */
-
-/* USER CODE END EV */
-
-/******************************************************************************/
-/* Cortex-M3 Processor Interruption and Exception Handlers */
-/******************************************************************************/
-/**
- * @brief This function handles Non maskable interrupt.
- */
-void NMI_Handler(void)
-{
- /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
-
- /* USER CODE END NonMaskableInt_IRQn 0 */
- /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
-
- /* USER CODE END NonMaskableInt_IRQn 1 */
-}
-
-/**
- * @brief This function handles Hard fault interrupt.
- */
-void HardFault_Handler(void)
-{
- /* USER CODE BEGIN HardFault_IRQn 0 */
-
- /* USER CODE END HardFault_IRQn 0 */
- while (1)
- {
- /* USER CODE BEGIN W1_HardFault_IRQn 0 */
- /* USER CODE END W1_HardFault_IRQn 0 */
- }
-}
-
-/**
- * @brief This function handles Memory management fault.
- */
-void MemManage_Handler(void)
-{
- /* USER CODE BEGIN MemoryManagement_IRQn 0 */
-
- /* USER CODE END MemoryManagement_IRQn 0 */
- while (1)
- {
- /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
- /* USER CODE END W1_MemoryManagement_IRQn 0 */
- }
-}
-
-/**
- * @brief This function handles Prefetch fault, memory access fault.
- */
-void BusFault_Handler(void)
-{
- /* USER CODE BEGIN BusFault_IRQn 0 */
-
- /* USER CODE END BusFault_IRQn 0 */
- while (1)
- {
- /* USER CODE BEGIN W1_BusFault_IRQn 0 */
- /* USER CODE END W1_BusFault_IRQn 0 */
- }
-}
-
-/**
- * @brief This function handles Undefined instruction or illegal state.
- */
-void UsageFault_Handler(void)
-{
- /* USER CODE BEGIN UsageFault_IRQn 0 */
-
- /* USER CODE END UsageFault_IRQn 0 */
- while (1)
- {
- /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
- /* USER CODE END W1_UsageFault_IRQn 0 */
- }
-}
-
-/**
- * @brief This function handles System service call via SWI instruction.
- */
-void SVC_Handler(void)
-{
- /* USER CODE BEGIN SVCall_IRQn 0 */
-
- /* USER CODE END SVCall_IRQn 0 */
- /* USER CODE BEGIN SVCall_IRQn 1 */
-
- /* USER CODE END SVCall_IRQn 1 */
-}
-
-/**
- * @brief This function handles Debug monitor.
- */
-void DebugMon_Handler(void)
-{
- /* USER CODE BEGIN DebugMonitor_IRQn 0 */
-
- /* USER CODE END DebugMonitor_IRQn 0 */
- /* USER CODE BEGIN DebugMonitor_IRQn 1 */
-
- /* USER CODE END DebugMonitor_IRQn 1 */
-}
-
-/**
- * @brief This function handles Pendable request for system service.
- */
-void PendSV_Handler(void)
-{
- /* USER CODE BEGIN PendSV_IRQn 0 */
-
- /* USER CODE END PendSV_IRQn 0 */
- /* USER CODE BEGIN PendSV_IRQn 1 */
-
- /* USER CODE END PendSV_IRQn 1 */
-}
-
-/**
- * @brief This function handles System tick timer.
- */
-void SysTick_Handler(void)
-{
- /* USER CODE BEGIN SysTick_IRQn 0 */
-
- /* USER CODE END SysTick_IRQn 0 */
-
- /* USER CODE BEGIN SysTick_IRQn 1 */
-
- /* USER CODE END SysTick_IRQn 1 */
-}
-
-/******************************************************************************/
-/* STM32F1xx Peripheral Interrupt Handlers */
-/* Add here the Interrupt Handlers for the used peripherals. */
-/* For the available peripheral interrupt handler names, */
-/* please refer to the startup file (startup_stm32f1xx.s). */
-/******************************************************************************/
-
-/**
- * @brief This function handles DMA1 channel2 global interrupt.
- */
-void DMA1_Channel2_IRQHandler(void)
-{
- /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */
-
- /* USER CODE END DMA1_Channel2_IRQn 0 */
-
- /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */
-
- /* USER CODE END DMA1_Channel2_IRQn 1 */
-}
-
-/**
- * @brief This function handles DMA1 channel4 global interrupt.
- */
-void DMA1_Channel4_IRQHandler(void)
-{
- /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
-
- /* USER CODE END DMA1_Channel4_IRQn 0 */
-
- /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
-
- /* USER CODE END DMA1_Channel4_IRQn 1 */
-}
-
-/**
- * @brief This function handles DMA1 channel5 global interrupt.
- */
-void DMA1_Channel5_IRQHandler(void)
-{
- /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */
-
- /* USER CODE END DMA1_Channel5_IRQn 0 */
-
- /* USER CODE BEGIN DMA1_Channel5_IRQn 1 */
-
- /* USER CODE END DMA1_Channel5_IRQn 1 */
-}
-
-/**
- * @brief This function handles DMA1 channel7 global interrupt.
- */
-void DMA1_Channel7_IRQHandler(void)
-{
- /* USER CODE BEGIN DMA1_Channel7_IRQn 0 */
- LL_DMA_ClearFlag_TC7(DMA1);
- Led_EndHandler();
- /* USER CODE END DMA1_Channel7_IRQn 0 */
-
- /* USER CODE BEGIN DMA1_Channel7_IRQn 1 */
-
- /* USER CODE END DMA1_Channel7_IRQn 1 */
-}
-
-/**
- * @brief This function handles TIM3 global interrupt.
- */
-void TIM3_IRQHandler(void)
-{
- /* USER CODE BEGIN TIM3_IRQn 0 */
- LL_TIM_ClearFlag_UPDATE(TIM3);
- Led_StartHandler();
- /* USER CODE END TIM3_IRQn 0 */
- /* USER CODE BEGIN TIM3_IRQn 1 */
-
- /* USER CODE END TIM3_IRQn 1 */
-}
-
-/**
- * @brief This function handles EXTI line[15:10] interrupts.
- */
-void EXTI15_10_IRQHandler(void)
-{
- /* USER CODE BEGIN EXTI15_10_IRQn 0 */
-
- /* USER CODE END EXTI15_10_IRQn 0 */
- if (LL_EXTI_IsActiveFlag_0_31(LL_EXTI_LINE_12) != RESET)
- {
- LL_EXTI_ClearFlag_0_31(LL_EXTI_LINE_12);
- /* USER CODE BEGIN LL_EXTI_LINE_12 */
- uint16_t* tmp = spiBufferRead;
- spiBufferRead = spiBufferReadNext;
- spiBufferReadNext = tmp;
- LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_4);
- LL_DMA_SetMemoryAddress(DMA1, LL_DMA_CHANNEL_4, (uint32_t)spiBufferReadNext);
- LL_DMA_SetDataLength(DMA1, LL_DMA_CHANNEL_4, BUFF_SIZE);
- LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_4);
- /* USER CODE END LL_EXTI_LINE_12 */
- }
- /* USER CODE BEGIN EXTI15_10_IRQn 1 */
-
- /* USER CODE END EXTI15_10_IRQn 1 */
-}
-
-/* USER CODE BEGIN 1 */
-
-/* USER CODE END 1 */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/system_stm32f1xx.c b/Src/system_stm32f1xx.c
deleted file mode 100644
index af3759a3b63a876025c29823c8d69a8566155a90..0000000000000000000000000000000000000000
--- a/Src/system_stm32f1xx.c
+++ /dev/null
@@ -1,448 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f1xx.c
- * @author MCD Application Team
- * @version V4.2.0
- * @date 31-March-2017
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
- * factors, AHB/APBx prescalers and Flash settings).
- * This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f1xx_xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f1xx_xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on
- * the product used), refer to "HSE_VALUE".
- * When HSE is used as system clock source, directly or through PLL, and you
- * are using different crystal you have to adapt the HSE value to your own
- * configuration.
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f1xx_system
- * @{
- */
-
-/** @addtogroup STM32F1xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f1xx.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F1xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F1xx_System_Private_Defines
- * @{
- */
-
-#if !defined (HSE_VALUE)
- #define HSE_VALUE 8000000U /*!< Default value of the External oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE 8000000U /*!< Default value of the Internal oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to use external SRAM */
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-/* #define DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F1xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F1xx_System_Private_Variables
- * @{
- */
-
-/*******************************************************************************
-* Clock Definitions
-*******************************************************************************/
-#if defined(STM32F100xB) ||defined(STM32F100xE)
- uint32_t SystemCoreClock = 24000000U; /*!< System Clock Frequency (Core Clock) */
-#else /*!< HSI Selected as System Clock source */
- uint32_t SystemCoreClock = 72000000U; /*!< System Clock Frequency (Core Clock) */
-#endif
-
-const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8U] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes
- * @{
- */
-
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-#ifdef DATA_IN_ExtSRAM
- static void SystemInit_ExtMemCtl(void);
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F1xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemCoreClock variable.
- * @note This function should be used only after reset.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
- /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
- /* Set HSION bit */
- RCC->CR |= 0x00000001U;
-
- /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
-#if !defined(STM32F105xC) && !defined(STM32F107xC)
- RCC->CFGR &= 0xF8FF0000U;
-#else
- RCC->CFGR &= 0xF0FF0000U;
-#endif /* STM32F105xC */
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= 0xFEF6FFFFU;
-
- /* Reset HSEBYP bit */
- RCC->CR &= 0xFFFBFFFFU;
-
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
- RCC->CFGR &= 0xFF80FFFFU;
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- /* Reset PLL2ON and PLL3ON bits */
- RCC->CR &= 0xEBFFFFFFU;
-
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x00FF0000U;
-
- /* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000U;
-#elif defined(STM32F100xB) || defined(STM32F100xE)
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000U;
-
- /* Reset CFGR2 register */
- RCC->CFGR2 = 0x00000000U;
-#else
- /* Disable all interrupts and clear pending bits */
- RCC->CIR = 0x009F0000U;
-#endif /* STM32F105xC */
-
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
- #ifdef DATA_IN_ExtSRAM
- SystemInit_ExtMemCtl();
- #endif /* DATA_IN_ExtSRAM */
-#endif
-
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
- * 8 MHz or 25 MHz, depending on the product used), user has to ensure
- * that HSE_VALUE is same as the real frequency of the crystal used.
- * Otherwise, this function may have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
-
-#if defined(STM32F105xC) || defined(STM32F107xC)
- uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
-#endif /* STM32F105xC */
-
-#if defined(STM32F100xB) || defined(STM32F100xE)
- uint32_t prediv1factor = 0U;
-#endif /* STM32F100xB or STM32F100xE */
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00U: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04U: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08U: /* PLL used as system clock */
-
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-#if !defined(STM32F105xC) && !defined(STM32F107xC)
- pllmull = ( pllmull >> 18U) + 2U;
-
- if (pllsource == 0x00U)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
- }
- else
- {
- #if defined(STM32F100xB) || defined(STM32F100xE)
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- #else
- /* HSE selected as PLL clock entry */
- if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
- {/* HSE oscillator clock divided by 2 */
- SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
- }
- else
- {
- SystemCoreClock = HSE_VALUE * pllmull;
- }
- #endif
- }
-#else
- pllmull = pllmull >> 18U;
-
- if (pllmull != 0x0DU)
- {
- pllmull += 2U;
- }
- else
- { /* PLL multiplication factor = PLL input clock * 6.5 */
- pllmull = 13U / 2U;
- }
-
- if (pllsource == 0x00U)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;
- }
- else
- {/* PREDIV1 selected as PLL clock entry */
-
- /* Get PREDIV1 clock source and division factor */
- prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;
-
- if (prediv1source == 0U)
- {
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- }
- else
- {/* PLL2 clock selected as PREDIV1 clock entry */
-
- /* Get PREDIV2 division factor and PLL2 multiplication factor */
- prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;
- pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U;
- SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
- }
- }
-#endif /* STM32F105xC */
- break;
-
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
-
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
-/**
- * @brief Setup the external memory controller. Called in startup_stm32f1xx.s
- * before jump to __main
- * @param None
- * @retval None
- */
-#ifdef DATA_IN_ExtSRAM
-/**
- * @brief Setup the external memory controller.
- * Called in startup_stm32f1xx_xx.s/.c before jump to main.
- * This function configures the external SRAM mounted on STM3210E-EVAL
- * board (STM32 High density devices). This SRAM will be used as program
- * data memory (including heap and stack).
- * @param None
- * @retval None
- */
-void SystemInit_ExtMemCtl(void)
-{
- __IO uint32_t tmpreg;
- /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
- required, then adjust the Register Addresses */
-
- /* Enable FSMC clock */
- RCC->AHBENR = 0x00000114U;
-
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);
-
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
- RCC->APB2ENR = 0x000001E0U;
-
- /* Delay after an RCC peripheral clock enabling */
- tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);
-
- (void)(tmpreg);
-
-/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
-/*---------------- SRAM Address lines configuration -------------------------*/
-/*---------------- NOE and NWE configuration --------------------------------*/
-/*---------------- NE3 configuration ----------------------------------------*/
-/*---------------- NBL0, NBL1 configuration ---------------------------------*/
-
- GPIOD->CRL = 0x44BB44BBU;
- GPIOD->CRH = 0xBBBBBBBBU;
-
- GPIOE->CRL = 0xB44444BBU;
- GPIOE->CRH = 0xBBBBBBBBU;
-
- GPIOF->CRL = 0x44BBBBBBU;
- GPIOF->CRH = 0xBBBB4444U;
-
- GPIOG->CRL = 0x44BBBBBBU;
- GPIOG->CRH = 0x444B4B44U;
-
-/*---------------- FSMC Configuration ---------------------------------------*/
-/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
-
- FSMC_Bank1->BTCR[4U] = 0x00001091U;
- FSMC_Bank1->BTCR[5U] = 0x00110212U;
-}
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/openocd-0.10.0/NEWS-0.2.0.txt b/openocd-0.10.0/NEWS-0.2.0.txt
deleted file mode 100644
index 742692684ce31199450c9d700ab50b817c8155a5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/NEWS-0.2.0.txt
+++ /dev/null
@@ -1,80 +0,0 @@
-The OpenOCD 0.2.0 source archive release includes numerous improvements
-that were made since the initial 0.1.0 source archive release. Many
-contributors helped make this release a great success, and the community
-of developers and maintainers look forward to any response.
-
-In addition to the list of changes below, countless bug fixing and
-cleaning was performed across the tree. Various TCL command parameters
-must past stricter value checks, and many more error conditions have
-been handled correctly. These efforts helped to make the 0.2.0 release
-more stable and robust, though some changes may expose latent bugs in
-your existing configuration scripts.
-
-This release does not maintain backward compatibility in all respects,
-so some target or configuration scripts may need to be updated. In some
-cases, you may also see warnings; resolve those, because they indicate
-commands that will be removed in the future.
-
-The following areas of OpenOCD functionality changed in this release:
-
-JTAG Layer:
-- Improves modularity: core, TCL, driver commands, and interface have
- been separated, encapsulated, and documented for developers. Mostly.
-- Improves JTAG TAP transition tables:
- * Makes TAP paths variable length, rather than being fixed at 7 steps.
- * Fixes problems with some targets that did not like longer paths.
-- Improves JTAG driver/minidriver modularity and encapsulation.
-- New drivers:
- * Adds stub minidriver for developing new embedded JTAG interfaces.
-- Improves drivers:
- * ft2232+ftd2xx:
- + Adds initial high-speed device support: --enable-ftd2xx-highspeed
- + Supports more types of FTDI-based devices.
- * jlink:
- + Works with more versions of the firmware (v3 and newer)
- + Supports dynamically detects device capabilities and limits
- * vsllink:
- + Supports very long scan chains
- * amtjtagaccel:
- + Fixes broken ID code detection problems.
-
-Target Layer:
-- New devices: AVR, FA526
-- Improved support: ARM ADI, ARM11, MIPS
-- Numerous other bug fixes and improvements
-
-Flash Layer:
-- Improved drivers: mflash
-- New drivers: AT91SAM3, AVR, Davinci NAND
-
-Board, Interface, and Target Configuration Scripts:
-- Many new and improved targets and boards are now available.
-- Better separation of "board" and "target" configuration
-- Moved all TCL files to top-level "tcl" directory in the source tree
-- Installation moved from '$pkglibdir/' to '$pkgdatadir/scripts/'.
-- Site-specific files should be installed under '$pkgdatadir/site/';
- files that exist this tree will be used in preference to default
- distribution configurations in '$pkgdatadir/scripts/'.
-
-Documentation:
-- Updated User Guide: http://openocd.berlios.de/doc/html/index.html
- * Partially re-written and re-organized.
- * Standardized presentation for all commands.
- * Covers many drivers and commands that were previously omitted.
- * New index for commands and drivers.
-- Added Developer Manual: http://openocd.berlios.de/doc/doxygen/index.html
- * Now includes architecture, technical primers, style guides, and more.
- * Available in-tree and on-line.
-
-Build and Release:
-- Increased configuration and compilation warning coverage.
- * Use --disable-werror to work around build errors caused by warnings.
-- Use libtool to produce helper libraries as a step toward "libopenocd".
-- New processes and scripting to facilitate future source releases.
-
-For more details about what has changed since 0.1.0, see the ChangeLog
-associated with this release.
-
-For more information about contributing test reports, bug fixes, or new
-features and device support, please read the new Developer Manual (or
-the BUGS and PATCHES files in the source archive).
diff --git a/openocd-0.10.0/NEWS-0.3.0.txt b/openocd-0.10.0/NEWS-0.3.0.txt
deleted file mode 100644
index 80e8823c4219f0da142b63face5db69a60d7e595..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/NEWS-0.3.0.txt
+++ /dev/null
@@ -1,82 +0,0 @@
-This file should include highlights of the changes made in the
-OpenOCD openocd-0.3.0 source archive release. See the repository
-history for details about what changed, including bugfixes and
-other issues not mentioned here.
-
-JTAG Layer:
- FT2232H (high speed USB) support doesn't need separate configuration
- New FT2232H JTAG adapters: Amontec, Olimex, Signalyzer
- New reset_config options for SRST gating the JTAG clock (or not)
- TAP declaration no longer requires ircapture and mask attributes
- Scan chain setup should be more robust, with better diagnostics
- New TAP events:
- "post-reset" for TAP-invariant setup code (TAPs not usable yet)
- "setup" for use once TAPs are addressable (e.g. with ICEpick)
- Overridable Tcl "init_reset" and "jtag_init" procedures
- Simple "autoprobe" mechanism to help simplify server setup
-
-Boundary Scan:
- SVF bugfixes ... parsing fixes, better STATE switch conformance
- XSVF bugfixes ... be more correct, handle Xilinx tool output
-
-Target Layer:
- Warn on use of obsolete numeric target IDs
- New commands for use with Cortex-M3 processors:
- "cortex_m3 disassemble" ... Thumb2 disassembly (UAL format)
- "cortex_m3 vector_catch" ... traps certain hardware faults
- without tying up breakpoint resources
- If you're willing to help debug it
- VERY EARLY Cortex-A8 and ARMv7A support
- Updated BeagleBoard.org hardware support
- you may need to explicitly "reset" after connect-to-Beagle
- New commands for use with XScale processors: "xscale vector_table"
- ARM
- bugfixes to single-stepping Thumb code
- ETM: unavailable registers are not listed
- ETB, ETM: report actual hardware status
- ARM9
- name change: "arm9 vector_catch" not "arm9tdmi vector_catch"
- ARM11
- single stepping support for i.MX31
- bugfix for missing "arm11" prefix on "arm11 memwrite ..."
- GDB support
- gdb_attach command is gone
-
-Flash Layer:
- The lpc2000 driver handles the new NXP LPC1700 (Cortex-M3) chips
- New drivers:
- lpc2900, for NXP LPC2900 chips (ARM968 based)
- mx3_nand, for imx31
- New "last" flag for NOR "flash erase_sector" and "flash protect"
- The "nand erase N" command now erases all of bank N
- Speed up davinci_nand by about 3x
-
-Board, Target, and Interface Configuration Scripts:
- Amontec JTAGkey2 support
- Cleanup and additions for the TI/Luminary Stellaris scripts
- LPC1768 target (and flash) support
- Keil MCB1700 eval board
- Samsung s3c2450
- Mini2440 board
- Numeric TAP and Target identifiers now trigger warnings
- PXA255 partially enumerates
-
-Documentation:
- Capture more debugging and setup advice
- Notes on target source code changes that may help debugging
-
-Build and Release:
- Repository moved from SVN at Berlios to GIT at SourceForge
- Clean builds on (32-bit) Cygwin
- Clean builds on 64-bit MinGW
-
-For more details about what has changed since the last release,
-see the git repository history. With gitweb, you can browse that
-in various levels of detail.
-
-For older NEWS, see the NEWS files associated with each release
-(i.e. NEWS-<version>).
-
-For more information about contributing test reports, bug fixes, or new
-features and device support, please read the new Developer Manual (or
-the BUGS and PATCHES files in the source archive).
diff --git a/openocd-0.10.0/NEWS-0.4.0.txt b/openocd-0.10.0/NEWS-0.4.0.txt
deleted file mode 100644
index cbd552617788c2c7d073a463356bc7cc8057356b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/NEWS-0.4.0.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-This file includes highlights of the changes made in the
-OpenOCD 0.4.0 source archive release. See the repository
-history for details about what changed, including bugfixes
-and other issues not mentioned here.
-
-JTAG Layer:
- Support KT-Link JTAG adapter.
- Support USB-JTAG, Altera USB-Blaster and compatibles.
-
-Boundary Scan:
-
-Target Layer:
- General
- - Removed commands which have been obsolete for at least
- a year (from both documentation and, sometimes, code).
- - new "reset-assert" event, for systems without SRST
- ARM
- - supports "reset-assert" event (except on Cortex-M3)
- - renamed "armv4_5" command prefix as "arm"
- - recognize TrustZone "Secure Monitor" mode
- - "arm regs" command output changed
- - register names use "sp" not "r13"
- - add top-level "mcr" and "mrc" commands, replacing
- various core-specific operations
- - basic semihosting support (ARM7/ARM9 only, for now)
- ARM11
- - Should act much more like other ARM cores:
- * Preliminary ETM and ETB hookup
- * accelerated "flash erase_check"
- * accelerated GDB memory checksum
- * support "arm regs" command
- * can access all core modes and registers
- * watchpoint support
- - Shares some core debug code with Cortex-A8
- Cortex-A8
- - Should act much more like other ARM cores:
- * support "arm regs" command
- * can access all core modes and registers
- * watchpoint support
- - Shares some core debug code with ARM11
- Cortex-M3
- - Exposed DWT registers like cycle counter
- - vector_catch settings not clobbered by resets
- - no longer interferes with firmware's fault handling
- ETM, ETB
- - "trigger_percent" command moved ETM --> ETB
- - "etm trigger_debug" command added
- MIPS
- - use fastdata writes
- Freescale DSP563xx cores (partial support)
-
-Flash Layer:
- 'flash bank' and 'nand device' take <bank_name> as first argument.
- With this, flash/NAND commands allow referencing banks by name:
- - <bank_name>: reference the bank with its defined name
- - <driver_name>[.N]: reference the driver's Nth bank
- New 'nand verify' command to check bank against an image file.
- The "flash erase_address" command now rejects partial sectors;
- previously it would silently erase extra data. If you
- want to erase the rest of the first and/or last sectors
- instead of failing, you must pass an explicit "pad" flag.
- New at91sam9 NAND controller driver.
- New s3c64xx NAND controller driver.
-
-Board, Target, and Interface Configuration Scripts:
- ARM9
- - ETM and ETB hookup for iMX2* targets
- Add $HOME/.openocd to the search path.
- Handle Rev C of LM3S811 eval boards.
- - use "luminary-lm3s811.cfg" for older boards
- - use "luminary.cfg" for RevC and newer
-
-Core Jim/TCL Scripting:
- New 'usage' command to provide terse command help.
- Improved command 'help' command output (sorted and indented).
- Improved command handling:
- - Most boolean settings now accept any of the following:
- on/off, enable/disable, true/false, yes/no, 1/0
- - More error checking and reporting.
-
-Documentation:
- New built-in command development documentation and primer.
-
-Build and Release:
- Use --enable-doxygen-pdf to build PDF developer documentation.
- Consider upgrading to libftdi 0.17 if you use that library; it
- includes bugfixes which improve FT2232H support.
-
-For more details about what has changed since the last release,
-see the git repository history. With gitweb, you can browse that
-in various levels of detail.
-
-For older NEWS, see the NEWS files associated with each release
-(i.e. NEWS-<version>).
-
-For more information about contributing test reports, bug fixes, or new
-features and device support, please read the new Developer Manual (or
-the BUGS and PATCHES.txt files in the source archive).
diff --git a/openocd-0.10.0/NEWS-0.5.0.txt b/openocd-0.10.0/NEWS-0.5.0.txt
deleted file mode 100644
index add6c1e9035498574967489daeda9eb5cb3aab56..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/NEWS-0.5.0.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-This file includes highlights of the changes made in the
-OpenOCD 0.5.0 source archive release. See the repository
-history for details about what changed, including bugfixes
-and other issues not mentioned here.
-
-JTAG Layer:
- New driver for "Bus Pirate"
- Rename various commands so they're not JTAG-specific
- There are migration procedures for most of these, but you should
- convert your scripts to the new names, since those procedures
- will not be around forever.
- jtag jinterface ... is now adapter_name
- jtag_khz ... is now adapter_khz
- jtag_nsrst_delay ... is now adapter_nsrst_delay
- jtag_nsrst_assert_width ... is now adapter_nsrst_assert_width
- Support Voipac VPACLink JTAG Adapter.
-
-Boundary Scan:
-
-Transport framework core ... supporting future work for SWD, SPI, and other
-non-JTAG ways to debug targets or program flash.
-
-Target Layer:
- ARM:
- - basic semihosting support for ARMv7M.
- - renamed "armv7m" command prefix as "arm"
- MIPS:
- - "ejtag_srst" variant removed. The same functionality is
- obtained by using "reset_config none".
- - added PIC32MX software reset support, this means srst is not
- required to be connected anymore.
- OTHER:
- - preliminary AVR32 AP7000 support.
-
-Flash Layer:
- New "stellaris recover" command, implements the procedure
- to recover locked devices (restoring non-volatile
- state to the factory defaults, including erasing
- the flash and its protection bits, and possibly
- re-enabling hardware debugging).
- PIC32MX now uses algorithm for flash programming, this
- has increased the performance by approx 96%.
- New 'pic32mx unlock' cmd to remove readout protection.
- New STM32 Value Line Support.
- New 'virtual' flash driver, used to associate other addresses
- with a flash bank. See pic32mx.cfg for usage.
- New iMX27 NAND flash controller driver.
-
-Board, Target, and Interface Configuration Scripts:
- Support IAR LPC1768 kickstart board (by Olimex)
- Support Voipac PXA270/PXA270M module.
- New $PARPORTADDR tcl variable used to change default
- parallel port address used.
- Remove lm3s811.cfg; use "stellaris.cfg" instead
-
-Core Jim/TCL Scripting:
- New "add_script_search_dir" command, behaviour is the same
- as the "-s" cmd line option.
-
-Documentation:
-
-Build and Release:
-
-For more details about what has changed since the last release,
-see the git repository history. With gitweb, you can browse that
-in various levels of detail.
-
-For older NEWS, see the NEWS files associated with each release
-(i.e. NEWS-<version>).
-
-For more information about contributing test reports, bug fixes, or new
-features and device support, please read the new Developer Manual (or
-the BUGS and PATCHES.txt files in the source archive).
-
diff --git a/openocd-0.10.0/NEWS-0.6.0.txt b/openocd-0.10.0/NEWS-0.6.0.txt
deleted file mode 100644
index 0acd2420822911907c34c89424f94625f90143fd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/NEWS-0.6.0.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-This file includes highlights of the changes made in the
-OpenOCD source archive release. See the
-repository history for details about what changed, including
-bugfixes and other issues not mentioned here.
-
-JTAG Layer:
- New STLINK V1/V2 JTAG/SWD adapter support.
- New OSJTAG adapter support.
- New Tincantools Flyswatter2 support.
- Improved ULINK driver.
- Improved RLINK driver.
- Support for adapters based on FT232H chips.
- New experimental driver for FTDI based adapters, using libusb-1.0 in asynchronous mode.
-
-Boundary Scan:
-
-Target Layer:
- New Cortex-M0 support.
- New Cortex-M4 support.
- Improved Working area algorithm.
- New RTOS support. Currently linux, FreeRTOS, ThreadX and eCos.
- Connecting under reset to Cortex-Mx and MIPS chips.
-
-Flash Layer:
- New SST39WF1601 support.
- New EN29LV800BB support.
- New async algorithm support for selected targets, stm32, stellaris and pic32.
- New Atmel SAM3S, SAM3N support.
- New ST STM32L support.
- New Microchip PIC32MX1xx/2xx support.
- New Freescale Kinetis K40 support.
-
-Board, Target, and Interface Configuration Scripts:
- Support Dangerous Prototypes Bus Blaster.
- Support ST SPEAr Family.
- Support Gumstix Verdex boards.
- Support TI Beaglebone.
-
-Documentation:
- Improved HACKING info for submitting patches.
- Fixed numerous broken links.
-
-Build and Release:
-
-For more details about what has changed since the last release,
-see the git repository history. With gitweb, you can browse that
-in various levels of detail.
-
-For older NEWS, see the NEWS files associated with each release
-(i.e. NEWS-<version>).
-
-For more information about contributing test reports, bug fixes, or new
-features and device support, please read the new Developer Manual (or
-the BUGS and PATCHES.txt files in the source archive).
diff --git a/openocd-0.10.0/NEWS-0.7.0.txt b/openocd-0.10.0/NEWS-0.7.0.txt
deleted file mode 100644
index 47a8fa66276dfa16b14b0e88c6ec043f52b51015..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/NEWS-0.7.0.txt
+++ /dev/null
@@ -1,43 +0,0 @@
-This file includes highlights of the changes made in the
-OpenOCD source archive release. See the
-repository history for details about what changed, including
-bugfixes and other issues not mentioned here.
-
-JTAG Layer:
- New TI ICDI adapter support.
- Support Latest OSBDM firmware.
- Improved MIPS EJTAG Support.
-
-Boundary Scan:
-
-Target Layer:
- New ARMv7R and Cortex-R4 support.
- Added ChibiOS/RT support.
-
-Flash Layer:
- New NXP LPC1850 support.
- New NXP LPC4300 support.
- New NXP SPIFI support.
- New Energy Micro EFM32 support.
- New ST STM32W support.
- New ST STM32f2 write protection and lock/unlock support.
- Ability to override STM32 flash bank size.
-
-Board, Target, and Interface Configuration Scripts:
- Support Freescale i.MX6 series targets.
-
-Documentation:
- New MIPS debugging info.
-
-Build and Release:
-
-For more details about what has changed since the last release,
-see the git repository history. With gitweb, you can browse that
-in various levels of detail.
-
-For older NEWS, see the NEWS files associated with each release
-(i.e. NEWS-<version>).
-
-For more information about contributing test reports, bug fixes, or new
-features and device support, please read the new Developer Manual (or
-the BUGS and PATCHES.txt files in the source archive).
diff --git a/openocd-0.10.0/NEWS-0.8.0.txt b/openocd-0.10.0/NEWS-0.8.0.txt
deleted file mode 100644
index 33b3af401ea8067069ac955b0244ca37d9818ac2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/NEWS-0.8.0.txt
+++ /dev/null
@@ -1,111 +0,0 @@
-This file includes highlights of the changes made in the OpenOCD
-source archive release.
-
-JTAG Layer:
- * New CMSIS-DAP driver
- * Andes AICE debug adapter support
- * New OpenJTAG driver
- * New BCM2835 (RaspberryPi) driver
- * JTAG VPI client driver (for OpenRISC Reference Platform SoC)
- * Xilinx BSCAN_* for OpenRISC support
- * ST-LINKv2-1 support
- * ST-LINKv2 SWO tracing support (UART emulation)
- * JLink-OB (onboard) support
- * Altera USB Blaster driver rewrite, initial Blaster II
- support
- * ULINK driver ported to libusb-1.0, OpenULINK build fixes
- * Support up to 64 bit IR lengths
- * SVF playback (FPGA programming) fixes
- * "ftdi" interface driver got extensive testing and is now
- recommended over the old ft2232 implementation
-
-Boundary Scan:
-
-Target Layer:
- * New target: Andes nds32
- * New target: OpenRISC OR1K
- * New target: Intel Quark X10xx
- * MIPS EJTAG 1.5/2.0 support
- * MIPS speed improvements
- * Cortex-M, Cortex-A (MEM-AP, APB-AP) targets working with BE
- hosts now
- * XScale vector_catch support, reset fixes
- * dsp563xx ad-hoc breakpoint/watchpoint support
- * RTOS support for embKernel
- * Target profiling improvements
- * Memory access functions testbench
-
-Flash Layer:
- * STM32 family sync with reference manuals, other bugfixes
- * STM32F401, STM32F07x support
- * Atmel SAM4L, SAMG5x support
- * at91sam3sd8{a,b}, at91sam3s8{a,b,c}, at91sam4s,
- at91sam3n0{a,b,0a,0b} support, bugfixes
- * Atmel SAMD support
- * Milandr 1986ВЕ* support
- * Kinetis KL, K21 support
- * Nuvoton NuMicro MINI5{1,2,4} support
- * Nuvoton NUC910 series support
- * NXP LPC43xx, LPC2000 fixes
- * NXP LPC800, LPC810 support
- * More ATmega parts supported
- * Fujitsu MB9Ax family support
- * EFM32 Wonder Gecko family support
- * Nordic nRF51 support
-
-Board, Target, and Interface Configuration Scripts:
- * STM32W108xx generic target config
- * STM32F429 discovery board config
- * STM32 Nucleo boards configs
- * DENX M53EVK board config
- * Altera Cyclone V SoC, SoCkit config
- * New TI Launchpads board configs
- * TI am43xx devices, AM437x GP EVM, AM438x ePOS EVM board
- configs
- * Marvell Armada 370 family initial support
- * TI TMDX570LS31USB (TMS570, Cortex-R4) support scripts
- * Freescale FRDM-KL25Z, KL46Z board configs
- * Digilent Zedboard config
- * Asus RT-N16, Linksys WRT54GL, BT HomeHub board configs
- * Atmel Xplained initial support
- * Broadcom bcm28155_ap board config
- * TUMPA, TUMPA Lite interface configs
- * Digilent JTAG-SMT2 interface config
- * New RAM testing functions
- * Easy-to-use firmware recovery helpers targetting ordinary
- users with common equipment
-
-Server Layer:
- * Auto-generation of GDB target description for ARMv7-M,
- ARM4, nds32, OR1K, Quark
- * GDB File-I/O Remote Protocol extension support
- * Default GDB flashing events handlers to initialise and reset
- the target automatically when "load" is used
-
-Documentation:
- * Extensive README* changes
- * The official User's Guide was proofread
- * Example cross-build script
- * RTOS documentation improvements
- * Tcl RPC documentation and examples added
-
-Build and Release:
- * *BSD, OS X, clang, ARM, windows build fixes
- * New pkg-config support changes the way libusb (and other
- dependencies) are handled. Many adapter drivers are now
- selected automatically during the configure stage.
-
-
-This release also contains a number of other important functional and
-cosmetic bugfixes. For more details about what has changed since the
-last release, see the git repository history:
-
-http://sourceforge.net/p/openocd/code/ci/v0.8.0/log/?path=
-
-
-For older NEWS, see the NEWS files associated with each release
-(i.e. NEWS-<version>).
-
-For more information about contributing test reports, bug fixes, or new
-features and device support, please read the new Developer Manual (or
-the BUGS and PATCHES.txt files in the source archive).
diff --git a/openocd-0.10.0/NEWS-0.9.0.txt b/openocd-0.10.0/NEWS-0.9.0.txt
deleted file mode 100644
index 77ae4b07061f3b37d8b8dfc2224ee2f5caba7aa5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/NEWS-0.9.0.txt
+++ /dev/null
@@ -1,110 +0,0 @@
-This file includes highlights of the changes made in the OpenOCD
-source archive release.
-
-JTAG Layer:
- * SWD support with FTDI, Versaloon, J-Link, sysfsgpio
- * CMSIS-DAP massive speed and stability improvements
- * Versaloon driver ported to libusb-1.0
- * STLink can reestablish communication with a target that was
- disconnected or rebooted
- * STLink FAULT and WAIT SWD handling improved
- * New hla_serial command to distinguish between several HLA
- adapters attached to a single machine
- * Serial number support for CMSIS-DAP and J-Link adapters
- * Support for more J-Link adapters
- * TAP autoprobing improvements
- * Big speedup for SVF playback with USB Blaster
-
-Boundary Scan:
-
-Target Layer:
- * Stability improvements for targets that get disconnected or
- rebooted during a debug session
- * MIPS speed and reliability improvements
- * MIPS 1.5/2.0 fixes
- * ARMv7-R improvements
- * Cortex-A improvements, A7, A15 MPCores support
- * FPU support for ARMv7-M (Cortex-M4F)
- * TPIU/ITM support (including SWO/SWV tracing), can be
- captured with external tools or STLink
- * JTAG Serial Port (Advanced Debug System softcore) support
- * Profiling support for OpenRISC
- * ChibiOS/RT 3.0 support (with and without FPU)
- * FreeRTOS current versions support
- * Freescale MQX RTOS support
- * GDB target description support for MIPS
- * The last created target is auto-selected as the current
-
-Flash Layer:
- * nRF51 async loader to improve flashing performance and stability
- * Cypress PSoC 41xx/42xx and CCG1 families flash driver
- * Silabs SiM3 family flash driver
- * Marvell Wireless Microcontroller SPI flash driver
- * Kinetis mass erase (part unsecuring) implemented
- * lpcspifi stability fixes
- * STM32 family sync with reference manuals, L0 support, bugfixes
- * LPC2000 driver automatically determines part and flash size
- * NXP LPC11(x)xx, LPC13xx, LPC15xx, LPC8xx, LPC5410x, LPC407x support
- * Atmel SAMD, SAMR, SAML21 devices support
- * Atmel SAM4E16 support
- * ZeroGecko family support
- * TI Tiva C Blizzard and Snowflake families support
- * Nuvoton NuMicro M051 support
- * EZR32 support in EFM32 driver
-
-Board, Target, and Interface Configuration Scripts:
- * Normal target configs can work with HLA (STLink, ICDI) adapters
- * STM32 discovery and Nucleo boards configs
- * Gumstix AeroCore board config
- * General Plus GP326XXXA target config
- * Micrel KS869x target config
- * ASUS RT-N66U board config
- * Atmel SAM4E-EK board config
- * Atmel AT91SAM4L proper reset handling implemented
- * TI OMAP/AM 3505, 3517 target configs
- * nRF51822-mKIT board config
- * RC Module К1879ХБ1Я target config
- * TI TMDX570LS20SUSB board config
- * TI TMS570 USB Kit board config
- * TI CC2538, CC26xx target configs
- * TI AM437x major config improvements, DDR support
- * TI AM437X IDK board config
- * TI SimpleLink Wi-Fi CC3200 LaunchPad configs
- * Silicon Labs EM357, EM358 target configs
- * Infineon XMC1000, XMC4000 family targets and boards configs
- * Atheros AR9331 target config
- * TP-LINK TL-MR3020 board config
- * Alphascale asm9260t target and eval kit configs
- * Olimex SAM7-LA2 (AT91SAM7A2) board config
- * EFM32 Gecko boards configs
- * Spansion FM4 target and SK-FM4-176L-S6E2CC board configs
- * LPC1xxx target configs were restructured
- * IoT-LAB debug adapter config
- * DP BusBlaster KT-Link compatible config
-
-Server Layer:
- * Polling period can be configured
- * "shutdown" command has an immediate effect
- * The "program" command doesn't lead to a shutdown by
- default, use optional "exit" parameter for the old behaviour
- * Proper OS signal handling was implemented
- * Async target notifications for the Tcl RPC
-
-Documentation:
-
-Build and Release:
-
-
-This release also contains a number of other important functional and
-cosmetic bugfixes. For more details about what has changed since the
-last release, see the git repository history:
-
-http://sourceforge.net/p/openocd/code/ci/v0.9.0/log/?path=
-
-
-For older NEWS, see the NEWS files associated with each release
-(i.e. NEWS-<version>).
-
-For more information about contributing test reports, bug fixes, or new
-features and device support, please read the new Developer Manual (or
-the BUGS and PATCHES.txt files in the source archive).
diff --git a/openocd-0.10.0/NEWS.txt b/openocd-0.10.0/NEWS.txt
deleted file mode 100644
index e3b1e2565e5f0f87b3e95e065b655df3a6b0fd7a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/NEWS.txt
+++ /dev/null
@@ -1,155 +0,0 @@
-This file includes highlights of the changes made in the OpenOCD
-source archive release.
-
-JTAG Layer:
- * New driver for J-Link adapters based on libjaylink
- (including support for FPGA configuration, SWO and EMUCOM)
- * FTDI improvements to work at 30MHz clock
- * BCM2835 native driver SWD and Raspberry Pi2 support
- * BCM2835 is set to 4ma drive, slow slew rate
- * ixo-usb-jtag (emulation of an Altera Bus Blaster I on
- Cypress FX2 IC) support
- * JTAG pass-through mode for CMSIS-DAP (including support for
- FPGA configuration)
- * OpenJTAG support for Cypress CY7C65215
- * connect_assert_srst support for SWD
- * Xilinx Virtex-II Series7 bitstream loading support
- * Use JEP106 data to decode IDs
- * Deprecated "ft2232" driver removed (use "ftdi" instead)
- * GPL-incompatible FTDI D2XX library support dropped (Presto,
- OpenJTAG and USB-Blaster I are using libftdi only now)
- * ZY1000 support dropped (unmaintained since long)
- * oocd_trace support dropped
-
-Boundary Scan:
-
-Target Layer:
- * ARMv7-A, Cortex-M, Cortex-A/R important fixes and
- improvements (allowing e.g. simultaneous debugging of A8 and
- M3 cores, JTAG WAIT support etc.)
- * ARM Cortex-A,R allow interrupt disable during single-step
- (maskisr command)
- * Semihosting support for ARMv7-A
- * ARM Cortex-M7 support
- * Intel Quark mcu D2000 support
- * Freescale LS102x SAP support
- * ThreadX RTOS support on ARM926E-JS
- * Cortex-M RTOS stack alignment fixes
- * FreeRTOS FPU support
- * uC/OS-III RTOS support
- * bridging semihosting to GDB's File-I/O support
- * -defer-examine option added to target create command
- * verify_image_checksum command added
-
-Flash Layer:
- * Atmel SAM4S, SAM4N, SAM4C support
- * Atmel SAMV, SAMS, SAME (Cortex-M7) support
- * Atmel AT91SAMD handle reset run/halt in DSU, other fixes
- * Atmel AT91SAML21, SAML22, SAMC20/SAMC21, SAMD09 support
- * ST STM32F4x support
- * ST STM32F74x/76x/77x, STM32L4 support
- * ST STM32L0 categories 1, 2 and 5 support
- * Kinetis K02, K21, K22, K24, K26, K63, K64, K66 support
- * Kinetis KE, KVx, K8x families support
- * Kinetis FlexNVM handling
- * Kinetis flash protection, security, mass_erase improvements
- * Infineon XMC4xxx family support
- * Infineon XMC1000 flash driver
- * Energy Micro EFM32 Happy Gecko support
- * Energy Micro EFM32 debug interface lock support
- * Analog Devices ADuCM360 support
- * Unified Nuvoton NuMicro flash driver
- * NIIET K1921VK01T (Cortex-M4) support
- * Nordic Semiconductor nRF51 improvements
- * Spansion FM4 flash (including MB9BFx64/x65, S6E2DH) driver
- * Ambiq Micro Apollo flash driver
- * PIC32MX new device IDs, 17x/27x flash support
- * read_bank() and verify_bank() NOR flash internal API to
- allow reading (and verifying) non-memory-mapped devices
- * JTAGSPI driver to access SPI NOR flashes via a trivial
- FPGA proxy
- * Milandr read/verify for Info memory support
- * Various discrete SPI NOR flashes support
- * CFI 16-bit flash reversed endianness support
-
-Board, Target, and Interface Configuration Scripts:
- * Digilent JTAG-HS2, JTAG-HS3 interfaces configs
- * FTDI UM232H module as JTAG interface config
- * 100ask's OpenJTAG interface config
- * MBFTDI interface config
- * XDS100v3 interface config
- * Freescale Vybrid VF6xx target config
- * EmCraft VF6 SOM and baseboard configs
- * Freescale SabreSD board config
- * Freescale VF65GS10 tower board config
- * Pipistrello Xilinx Spartan6 LX45 FPGA board config
- * miniSpartan6+ board config
- * Xilinx Kintex7 Development board config
- * Parallella-I board config
- * Digilent Atlys and Analog Discovery board configs
- * Numato Opsis board config
- * Xilinx Spartan 6 FPGA "Device DNA" reading support
- * Altera 10M50 FPGA (MAX10 family) target config
- * Altera EPM240 CPLD (MAXII family) target config
- * Marsohod2, Marsohod3 FPGA, Marsohod CPLD boards configs
- * Novena's integrated FPGA board config
- * XMOS XS1-XAU8A-10's ARM core config
- * XMOS xCORE-XA Core Module board config
- * Exynos5250 target config
- * Arndale board config
- * FM4 MB9BFxxx family configs
- * Spansion SK-FM4-U120-9B560 board config
- * Diolan LPC4357-DB1 board config
- * ST STM32F469 discovery board config
- * ST STM32F7-DISCO, STM327[4|5]6G-EVAL boards configs
- * ST STM32L4 discovery, NUCLEO L476RG, STM32F429I-DISC1 boards
- configs
- * Atheros AR2313, AR2315 targets config
- * Netgear WP102 board config
- * La Fonera FON2200 board config
- * Linksys WAG200G board config
- * LPC-Link2 board config
- * NXP LPC4370 target config
- * Atmel SAMV, SAMS, SAME target configs
- * Atmel SAM E70 Xplained, SAM V71 Xplained Ultra boards
- configs
- * Nordic nRF52 target config
- * Nordic nRF51-DK, nRF52-DK boards configs
- * Infineon XMC4700 Relax Kit, XMC4800 Relax EtherCAT Kit,
- XMC4300 Relax EtherCAT Kit boards configs
- * Renesas S7G2 target config
- * Renesas DK-S7G2 board config
- * Altera EP3C10 FPGA (Cyclone III family) target config
- * TI MSP432P4xx target config
- * Cypress PSoC 5LP target config
- * Analog Devices ADSP-SC58x target config (Cortex-A5 core only)
-
-Server Layer:
- * tcl_trace command for async target trace output via Tcl RPC
-
-Documentation:
-
-Build and Release:
- * Various fixes thanks to http://coccinellery.org/
- * libftdi is now autodetected with pkgconfig
- * Releases should now support reproducible builds
- * Conversion to non-recursive make, requires automake >= 1.14
- * Udev rules modified to add uaccess tag and moved to
- 60-openocd.rules
- * Support searching for scripts relative to the openocd binary
- for all major architectures
-
-
-This release also contains a number of other important functional and
-cosmetic bugfixes. For more details about what has changed since the
-last release, see the git repository history:
-
-http://sourceforge.net/p/openocd/code/ci/v0.10.0/log/?path=
-
-
-For older NEWS, see the NEWS files associated with each release
-(i.e. NEWS-<version>).
-
-For more information about contributing test reports, bug fixes, or new
-features and device support, please read the new Developer Manual (or
-the BUGS and PATCHES.txt files in the source archive).
diff --git "a/openocd-0.10.0/OpenOCD User\342\200\231s Guide.pdf" "b/openocd-0.10.0/OpenOCD User\342\200\231s Guide.pdf"
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deleted file mode 100644
index 612c34b44b07356a977199bd22a80d7f368805d6..0000000000000000000000000000000000000000
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diff --git a/openocd-0.10.0/bin-x64/libusb-1.0.dll b/openocd-0.10.0/bin-x64/libusb-1.0.dll
deleted file mode 100644
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diff --git a/openocd-0.10.0/bin-x64/openocd.exe b/openocd-0.10.0/bin-x64/openocd.exe
deleted file mode 100644
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diff --git a/openocd-0.10.0/bin/libgcc_s_sjlj-1.dll b/openocd-0.10.0/bin/libgcc_s_sjlj-1.dll
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diff --git a/openocd-0.10.0/bin/libwinpthread-1.dll b/openocd-0.10.0/bin/libwinpthread-1.dll
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diff --git a/openocd-0.10.0/bin/openocd.exe b/openocd-0.10.0/bin/openocd.exe
deleted file mode 100644
index c6171419c6bebbc75a874ec18ba8a087f9bee29a..0000000000000000000000000000000000000000
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diff --git a/openocd-0.10.0/info.txt b/openocd-0.10.0/info.txt
deleted file mode 100644
index 9d77d1b9f827a6b136c6f45bb420062c1d2b2638..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/info.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-openocd-0.10.0
-commit date: 2017-01-22 20:31:28
-build date: 2017-01-23
-package date: 2017-01-23
-build system: Linux 4.8.13-1-ARCH #1 SMP PREEMPT Fri Dec 9 07:24:34 CET 2016 x86_64 GNU/Linux
-compiler: i686-w64-mingw32-gcc 6.3.1, x86_64-w64-mingw32-gcc 6.3.1
-
-Libraries used:
-hidapi-0.8.0-rc1
-libftdi-1.3
-libusb-win32-1.2.6.0
-libusb-1.0.21
-
-Build commands used for 32-bit version:
-../configure --host=i686-w64-mingw32 --prefix= --enable-aice --enable-amtjtagaccel --enable-armjtagew --enable-cmsis-dap
- --enable-dummy --enable-ftdi --enable-gw16012 --enable-jlink --enable-jtag_vpi --enable-opendous --enable-openjtag
- --enable-osbdm --enable-parport --disable-parport-ppdev --enable-parport-giveio --enable-presto
- --enable-remote-bitbang --enable-rlink --enable-stlink --enable-ti-icdi --enable-ulink --enable-usb-blaster
- --enable-usb-blaster-2 --enable-usbprog --enable-vsllink
-make bindir="bin" pkgdatadir=
-i686-w64-mingw32-strip src/openocd.exe
-
-Build commands used for 64-bit version:
-../configure --host=x86_64-w64-mingw32 --prefix= --enable-aice --enable-amtjtagaccel --enable-armjtagew
- --enable-cmsis-dap --enable-dummy --enable-ftdi --enable-gw16012 --enable-jlink --enable-jtag_vpi --enable-opendous
- --enable-openjtag --enable-osbdm --enable-parport --disable-parport-ppdev --enable-parport-giveio --enable-presto
- --enable-remote-bitbang --enable-rlink --enable-stlink --enable-ti-icdi --enable-ulink --enable-usb-blaster
- --enable-usb-blaster-2 --enable-usbprog --enable-vsllink
-make bindir="bin-x64" pkgdatadir=
-x86_64-w64-mingw32-strip src/openocd.exe
-
-This package and info about it can be found on Freddie Chopin's website:
-http://www.freddiechopin.info/
-
diff --git a/openocd-0.10.0/license-hidapi.txt b/openocd-0.10.0/license-hidapi.txt
deleted file mode 100644
index e3f33808299600e580b63aee36a0eb18daaae916..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/license-hidapi.txt
+++ /dev/null
@@ -1,9 +0,0 @@
- HIDAPI - Multi-Platform library for
- communication with HID devices.
-
- Copyright 2009, Alan Ott, Signal 11 Software.
- All Rights Reserved.
-
- This software may be used by anyone for any reason so
- long as the copyright notice in the source files
- remains intact.
diff --git a/openocd-0.10.0/license-libftdi.txt b/openocd-0.10.0/license-libftdi.txt
deleted file mode 100644
index e38ffa83741b7c84a681b9031f9fc26fd801b6c5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/license-libftdi.txt
+++ /dev/null
@@ -1,481 +0,0 @@
- GNU LIBRARY GENERAL PUBLIC LICENSE
- Version 2, June 1991
-
- Copyright (C) 1991 Free Software Foundation, Inc.
- 59 Temple Place - Suite 330
- Boston, MA 02111-1307, USA.
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
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- numbered 2 because it goes with version 2 of the ordinary GPL.]
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diff --git a/openocd-0.10.0/license-libusb-win32.txt b/openocd-0.10.0/license-libusb-win32.txt
deleted file mode 100644
index 65c5ca88a67c30becee01c5a8816d964b03862f9..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/license-libusb-win32.txt
+++ /dev/null
@@ -1,165 +0,0 @@
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diff --git a/openocd-0.10.0/license-libusb.txt b/openocd-0.10.0/license-libusb.txt
deleted file mode 100644
index 5ab7695ab8cabe0c5c8a814bb0ab1e8066578fbb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/license-libusb.txt
+++ /dev/null
@@ -1,504 +0,0 @@
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-If any portion of this section is held invalid or unenforceable under any
-particular circumstance, the balance of the section is intended to apply,
-and the section as a whole is intended to apply in other circumstances.
-
-It is not the purpose of this section to induce you to infringe any
-patents or other property right claims or to contest validity of any
-such claims; this section has the sole purpose of protecting the
-integrity of the free software distribution system which is
-implemented by public license practices. Many people have made
-generous contributions to the wide range of software distributed
-through that system in reliance on consistent application of that
-system; it is up to the author/donor to decide if he or she is willing
-to distribute software through any other system and a licensee cannot
-impose that choice.
-
-This section is intended to make thoroughly clear what is believed to
-be a consequence of the rest of this License.
-
- 12. If the distribution and/or use of the Library is restricted in
-certain countries either by patents or by copyrighted interfaces, the
-original copyright holder who places the Library under this License may add
-an explicit geographical distribution limitation excluding those countries,
-so that distribution is permitted only in or among countries not thus
-excluded. In such case, this License incorporates the limitation as if
-written in the body of this License.
-
- 13. The Free Software Foundation may publish revised and/or new
-versions of the Lesser General Public License from time to time.
-Such new versions will be similar in spirit to the present version,
-but may differ in detail to address new problems or concerns.
-
-Each version is given a distinguishing version number. If the Library
-specifies a version number of this License which applies to it and
-"any later version", you have the option of following the terms and
-conditions either of that version or of any later version published by
-the Free Software Foundation. If the Library does not specify a
-license version number, you may choose any version ever published by
-the Free Software Foundation.
-
- 14. If you wish to incorporate parts of the Library into other free
-programs whose distribution conditions are incompatible with these,
-write to the author to ask for permission. For software which is
-copyrighted by the Free Software Foundation, write to the Free
-Software Foundation; we sometimes make exceptions for this. Our
-decision will be guided by the two goals of preserving the free status
-of all derivatives of our free software and of promoting the sharing
-and reuse of software generally.
-
- NO WARRANTY
-
- 15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO
-WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW.
-EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR
-OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY
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-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE
-LIBRARY IS WITH YOU. SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME
-THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
-
- 16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN
-WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY
-AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU
-FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR
-CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE
-LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING
-RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A
-FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF
-SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
-DAMAGES.
-
- END OF TERMS AND CONDITIONS
-
- How to Apply These Terms to Your New Libraries
-
- If you develop a new library, and you want it to be of the greatest
-possible use to the public, we recommend making it free software that
-everyone can redistribute and change. You can do so by permitting
-redistribution under these terms (or, alternatively, under the terms of the
-ordinary General Public License).
-
- To apply these terms, attach the following notices to the library. It is
-safest to attach them to the start of each source file to most effectively
-convey the exclusion of warranty; and each file should have at least the
-"copyright" line and a pointer to where the full notice is found.
-
- <one line to give the library's name and a brief idea of what it does.>
- Copyright (C) <year> <name of author>
-
- This library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- This library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with this library; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
-
-Also add information on how to contact you by electronic and paper mail.
-
-You should also get your employer (if you work as a programmer) or your
-school, if any, to sign a "copyright disclaimer" for the library, if
-necessary. Here is a sample; alter the names:
-
- Yoyodyne, Inc., hereby disclaims all copyright interest in the
- library `Frob' (a library for tweaking knobs) written by James Random Hacker.
-
- <signature of Ty Coon>, 1 April 1990
- Ty Coon, President of Vice
-
-That's all there is to it!
-
-
diff --git a/openocd-0.10.0/license-openocd.txt b/openocd-0.10.0/license-openocd.txt
deleted file mode 100644
index d159169d1050894d3ea3b98e1c965c4058208fe1..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/license-openocd.txt
+++ /dev/null
@@ -1,339 +0,0 @@
- GNU GENERAL PUBLIC LICENSE
- Version 2, June 1991
-
- Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
- Everyone is permitted to copy and distribute verbatim copies
- of this license document, but changing it is not allowed.
-
- Preamble
-
- The licenses for most software are designed to take away your
-freedom to share and change it. By contrast, the GNU General Public
-License is intended to guarantee your freedom to share and change free
-software--to make sure the software is free for all its users. This
-General Public License applies to most of the Free Software
-Foundation's software and to any other program whose authors commit to
-using it. (Some other Free Software Foundation software is covered by
-the GNU Lesser General Public License instead.) You can apply it to
-your programs, too.
-
- When we speak of free software, we are referring to freedom, not
-price. Our General Public Licenses are designed to make sure that you
-have the freedom to distribute copies of free software (and charge for
-this service if you wish), that you receive source code or can get it
-if you want it, that you can change the software or use pieces of it
-in new free programs; and that you know you can do these things.
-
- To protect your rights, we need to make restrictions that forbid
-anyone to deny you these rights or to ask you to surrender the rights.
-These restrictions translate to certain responsibilities for you if you
-distribute copies of the software, or if you modify it.
-
- For example, if you distribute copies of such a program, whether
-gratis or for a fee, you must give the recipients all the rights that
-you have. You must make sure that they, too, receive or can get the
-source code. And you must show them these terms so they know their
-rights.
-
- We protect your rights with two steps: (1) copyright the software, and
-(2) offer you this license which gives you legal permission to copy,
-distribute and/or modify the software.
-
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-that everyone understands that there is no warranty for this free
-software. If the software is modified by someone else and passed on, we
-want its recipients to know that what they have is not the original, so
-that any problems introduced by others will not reflect on the original
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-modification follow.
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- GNU GENERAL PUBLIC LICENSE
- TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
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- 0. This License applies to any program or other work which contains
-a notice placed by the copyright holder saying it may be distributed
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-that is to say, a work containing the Program or a portion of it,
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-Activities other than copying, distribution and modification are not
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-is covered only if its contents constitute a work based on the
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-copyright notice and disclaimer of warranty; keep intact all the
-notices that refer to this License and to the absence of any warranty;
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-along with the Program.
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-You may charge a fee for the physical act of transferring a copy, and
-you may at your option offer warranty protection in exchange for a fee.
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-distribute the same sections as part of a whole which is a work based
-on the Program, the distribution of the whole must be on the terms of
-this License, whose permissions for other licensees extend to the
-entire whole, and thus to each and every part regardless of who wrote it.
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-your rights to work written entirely by you; rather, the intent is to
-exercise the right to control the distribution of derivative or
-collective works based on the Program.
-
-In addition, mere aggregation of another work not based on the Program
-with the Program (or with a work based on the Program) on a volume of
-a storage or distribution medium does not bring the other work under
-the scope of this License.
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-under Section 2) in object code or executable form under the terms of
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-If any portion of this section is held invalid or unenforceable under
-any particular circumstance, the balance of the section is intended to
-apply and the section as a whole is intended to apply in other
-circumstances.
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-It is not the purpose of this section to induce you to infringe any
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-integrity of the free software distribution system, which is
-implemented by public license practices. Many people have made
-generous contributions to the wide range of software distributed
-through that system in reliance on consistent application of that
-system; it is up to the author/donor to decide if he or she is willing
-to distribute software through any other system and a licensee cannot
-impose that choice.
-
-This section is intended to make thoroughly clear what is believed to
-be a consequence of the rest of this License.
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- 8. If the distribution and/or use of the Program is restricted in
-certain countries either by patents or by copyrighted interfaces, the
-original copyright holder who places the Program under this License
-may add an explicit geographical distribution limitation excluding
-those countries, so that distribution is permitted only in or among
-countries not thus excluded. In such case, this License incorporates
-the limitation as if written in the body of this License.
-
- 9. The Free Software Foundation may publish revised and/or new versions
-of the General Public License from time to time. Such new versions will
-be similar in spirit to the present version, but may differ in detail to
-address new problems or concerns.
-
-Each version is given a distinguishing version number. If the Program
-specifies a version number of this License which applies to it and "any
-later version", you have the option of following the terms and conditions
-either of that version or of any later version published by the Free
-Software Foundation. If the Program does not specify a version number of
-this License, you may choose any version ever published by the Free Software
-Foundation.
-
- 10. If you wish to incorporate parts of the Program into other free
-programs whose distribution conditions are different, write to the author
-to ask for permission. For software which is copyrighted by the Free
-Software Foundation, write to the Free Software Foundation; we sometimes
-make exceptions for this. Our decision will be guided by the two goals
-of preserving the free status of all derivatives of our free software and
-of promoting the sharing and reuse of software generally.
-
- NO WARRANTY
-
- 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
-FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
-OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
-PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
-OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
-TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
-PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
-REPAIR OR CORRECTION.
-
- 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
-WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
-REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
-INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
-OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
-TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
-YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
-PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGES.
-
- END OF TERMS AND CONDITIONS
-
- How to Apply These Terms to Your New Programs
-
- If you develop a new program, and you want it to be of the greatest
-possible use to the public, the best way to achieve this is to make it
-free software which everyone can redistribute and change under these terms.
-
- To do so, attach the following notices to the program. It is safest
-to attach them to the start of each source file to most effectively
-convey the exclusion of warranty; and each file should have at least
-the "copyright" line and a pointer to where the full notice is found.
-
- <one line to give the program's name and a brief idea of what it does.>
- Copyright (C) <year> <name of author>
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-
-Also add information on how to contact you by electronic and paper mail.
-
-If the program is interactive, make it output a short notice like this
-when it starts in an interactive mode:
-
- Gnomovision version 69, Copyright (C) year name of author
- Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
- This is free software, and you are welcome to redistribute it
- under certain conditions; type `show c' for details.
-
-The hypothetical commands `show w' and `show c' should show the appropriate
-parts of the General Public License. Of course, the commands you use may
-be called something other than `show w' and `show c'; they could even be
-mouse-clicks or menu items--whatever suits your program.
-
-You should also get your employer (if you work as a programmer) or your
-school, if any, to sign a "copyright disclaimer" for the program, if
-necessary. Here is a sample; alter the names:
-
- Yoyodyne, Inc., hereby disclaims all copyright interest in the program
- `Gnomovision' (which makes passes at compilers) written by James Hacker.
-
- <signature of Ty Coon>, 1 April 1989
- Ty Coon, President of Vice
-
-This General Public License does not permit incorporating your program into
-proprietary programs. If your program is a subroutine library, you may
-consider it more useful to permit linking proprietary applications with the
-library. If this is what you want to do, use the GNU Lesser General
-Public License instead of this License.
diff --git a/openocd-0.10.0/scripts/bitsbytes.tcl b/openocd-0.10.0/scripts/bitsbytes.tcl
deleted file mode 100644
index 2c4fd2907074f0008d2a585d320cffc7bfb61bf8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/bitsbytes.tcl
+++ /dev/null
@@ -1,61 +0,0 @@
-#----------------------------------------
-# Purpose - Create some $BIT variables
-# Create $K and $M variables
-# and some bit field extraction variables.
-# Creat helper variables ...
-# BIT0.. BIT31
-
-for { set x 0 } { $x < 32 } { set x [expr $x + 1]} {
- set vn [format "BIT%d" $x]
- global $vn
- set $vn [expr (1 << $x)]
-}
-
-# Create K bytes values
-# __1K ... to __2048K
-for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} {
- set vn [format "__%dK" $x]
- global $vn
- set $vn [expr (1024 * $x)]
-}
-
-# Create M bytes values
-# __1M ... to __2048K
-for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} {
- set vn [format "__%dM" $x]
- global $vn
- set $vn [expr (1024 * 1024 * $x)]
-}
-
-proc create_mask { MSB LSB } {
- return [expr (((1 << ($MSB - $LSB + 1))-1) << $LSB)]
-}
-
-# Cut Bits $MSB to $LSB out of this value.
-# Example: % format "0x%08x" [extract_bitfield 0x12345678 27 16]
-# Result: 0x02340000
-
-proc extract_bitfield { VALUE MSB LSB } {
- return [expr [create_mask $MSB $LSB] & $VALUE]
-}
-
-
-# Cut bits $MSB to $LSB out of this value
-# and shift (normalize) them down to bit 0.
-#
-# Example: % format "0x%08x" [normalize_bitfield 0x12345678 27 16]
-# Result: 0x00000234
-#
-proc normalize_bitfield { VALUE MSB LSB } {
- return [expr [extract_bitfield $VALUE $MSB $LSB ] >> $LSB]
-}
-
-proc show_normalize_bitfield { VALUE MSB LSB } {
- set m [create_mask $MSB $LSB]
- set mr [expr $VALUE & $m]
- set sr [expr $mr >> $LSB]
- echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr]
- return $sr
-}
-
-
diff --git a/openocd-0.10.0/scripts/board/actux3.cfg b/openocd-0.10.0/scripts/board/actux3.cfg
deleted file mode 100644
index 5435ff885fbb75be7f903bbab56de01624168397..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/actux3.cfg
+++ /dev/null
@@ -1,69 +0,0 @@
-# board config file for AcTux3/XBA IXP42x board
-# Date: 2010-12-16
-# Author: Michael Schwingen <michael@schwingen.org>
-
-reset_config trst_and_srst separate
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
-source [find target/ixp42x.cfg]
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0
-
-$_TARGETNAME configure -event reset-init { init_actux3 }
-
-proc init_actux3 { } {
- ##########################################################################
- # setup expansion bus CS
- ##########################################################################
- mww 0xc4000000 0xbd113842 ;#CS0 : Flash, write enabled @0x50000000
- mww 0xc4000004 0x94d10013 ;#CS1
- mww 0xc4000008 0x95960003 ;#CS2
- mww 0xc400000c 0x00000000 ;#CS3
- mww 0xc4000010 0x80900003 ;#CS4
- mww 0xc4000014 0x9d520003 ;#CS5
- mww 0xc4000018 0x81860001 ;#CS6
- mww 0xc400001c 0x80900003 ;#CS7
-
- ixp42x_init_sdram $::IXP42x_SDRAM_16MB_4Mx16_1BANK 2100 3
-
- #mww 0xc4000020 0xffffee ;# CFG0: remove expansion bus boot flash mirror at 0x00000000
-
- ixp42x_set_bigendian
-
- flash probe 0
-}
-
-proc flash_boot { {FILE "/tftpboot/actux3/u-boot.bin"} } {
- echo "writing bootloader: $FILE"
- flash write_image erase $FILE 0x50000000 bin
-}
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME
-
-init
-reset init
-
-# setup to debug u-boot in flash
-proc uboot_debug {} {
- gdb_breakpoint_override hard
- xscale vector_catch 0xFF
-
- xscale vector_table low 1 0xe59ff018
- xscale vector_table low 2 0xe59ff018
- xscale vector_table low 3 0xe59ff018
- xscale vector_table low 4 0xe59ff018
- xscale vector_table low 5 0xe59ff018
- xscale vector_table low 6 0xe59ff018
- xscale vector_table low 7 0xe59ff018
-
- xscale vector_table high 1 0xe59ff018
- xscale vector_table high 2 0xe59ff018
- xscale vector_table high 3 0xe59ff018
- xscale vector_table high 4 0xe59ff018
- xscale vector_table high 5 0xe59ff018
- xscale vector_table high 6 0xe59ff018
- xscale vector_table high 7 0xe59ff018
-}
diff --git a/openocd-0.10.0/scripts/board/adapteva_parallella1.cfg b/openocd-0.10.0/scripts/board/adapteva_parallella1.cfg
deleted file mode 100644
index 83d1cd44b1bce98de578a9dab69c10c502755e5b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/adapteva_parallella1.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Adapteva Parallella-I board (via Porcupine-1 adapter board)
-#
-
-reset_config srst_only
-
-source [find target/zynq_7000.cfg]
diff --git a/openocd-0.10.0/scripts/board/alphascale_asm9260_ek.cfg b/openocd-0.10.0/scripts/board/alphascale_asm9260_ek.cfg
deleted file mode 100644
index 46e8a5b5b8c725033804eab256509d01b594326d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/alphascale_asm9260_ek.cfg
+++ /dev/null
@@ -1,69 +0,0 @@
-source [find target/alphascale_asm9260t.cfg]
-
-reset_config trst_and_srst
-
-$_TARGETNAME configure -event reset-init {
- echo "Configure clock"
- # Enable SRAM clk
- mww 0x80040024 0x4
- # Enable IRQ clk
- mww 0x80040034 0x100
- # Enable DMA0,1 clk
- mww 0x80040024 0x600
- # Make sysre syspll is enabled
- mww 0x80040238 0x750
- #CPU = PLLCLK/2
- mww 0x8004017C 0x2
- #SYSAHBCLK = CPUCLK/2
- mww 0x80040180 0x2
- # Set PLL freq to 480MHz
- mww 0x80040100 480
- # normally we shoul waiting here until we get 0x1 (0x80040104)&0x1)==0x0)
- sleep 100
-
- # select PLL as main source
- mww 0x80040120 0x1
- # disable and enble main clk to update changes?
- mww 0x80040124 0x0
- mww 0x80040124 0x1
-
- echo "Configure memory"
- #enable EMI CLK
- mww 0x80040024 0x40
-
- # configure memory controller for internal SRAM
- mww 0x80700000 0x1188
- # change default emi clk delay
- mww 0x8004034C 0xA0503
- # make sure chip_select_register2_low has correct value (why?)
- mww 0x8070001c 0x20000000
- # set type to sdram and size to 32MB
- mww 0x8070005c 0xa
- # configure internal SDRAM timing
- mww 0x80700004 0x024996d9
- # configure Static Memory timing
- mww 0x80700094 0x00542b4f
-
- echo "Configure uart4"
- # enable pinctrl clk
- mww 0x80040024 0x2000000
- # mux GPIO3_0 and GPIO3_1 to UART4
- mww 0x80044060 0x2
- mww 0x80044064 0x2
- # configure UART4CLKDIV
- mww 0x800401a8 0x1
- # enable uart4 clk
- mww 0x80040024 0x8000
- # clear softrst and clkgate on uart4
- mww 0x80010008 0xC0000000
- # set bandrate 115200 12M
- mww 0x80010030 0x00062070
- # enable Rx&Tx
- mww 0x80010024 0x301
- # clear hw control
- mww 0x80010028 0xc000
-}
-
-$_TARGETNAME configure -work-area-phys 0x21ffe000 -work-area-virt 0xc1ffe000 -work-area-size 0x1000
-$_TARGETNAME arm7_9 fast_memory_access enable
-$_TARGETNAME arm7_9 dcc_downloads enable
diff --git a/openocd-0.10.0/scripts/board/altera_sockit.cfg b/openocd-0.10.0/scripts/board/altera_sockit.cfg
deleted file mode 100644
index 569414331bb86474a960ecdf393d2e5c9e0621b5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/altera_sockit.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Cyclone V SocKit board
-# http://www.altera.com/b/arrow-sockit.html
-#
-# Software support page:
-# http://www.rocketboards.org/
-
-# openocd does not currently support the on-board USB Blaster II.
-# Install the JTAG header and use a USB Blaster instead.
-interface usb_blaster
-
-source [find target/altera_fpgasoc.cfg]
-
-# If the USB Blaster II were supported, these settings would be needed
-#usb_blaster_vid_pid 0x6810 0x09fb
-#usb_blaster_device_desc "USB-Blaster II"
-
-adapter_khz 100
-
diff --git a/openocd-0.10.0/scripts/board/am3517evm.cfg b/openocd-0.10.0/scripts/board/am3517evm.cfg
deleted file mode 100644
index 2bff51246ece5ad4ca3fecd1ba12c7ef46a15c41..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/am3517evm.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-# DANGER!!!! early work in progress for this PCB/target.
-#
-# The most basic operations work well enough that it is
-# useful to have this in the repository for cooperation
-# alpha testing purposes.
-#
-# TI AM3517
-#
-# http://focus.ti.com/docs/prod/folders/print/am3517.html
-# http://processors.wiki.ti.com/index.php/Debug_Access_Port_(DAP)
-# http://processors.wiki.ti.com/index.php?title=How_to_Find_the_Silicon_Revision_of_your_OMAP35x
-
-set CHIPTYPE "am35x"
-source [find target/amdm37x.cfg]
-
-# The TI-14 JTAG connector does not have srst. CPU reset is handled in
-# hardware.
-reset_config trst_only
-
-# "amdm37x_dbginit am35x.cpu" needs to be run after init.
-
diff --git a/openocd-0.10.0/scripts/board/arm_evaluator7t.cfg b/openocd-0.10.0/scripts/board/arm_evaluator7t.cfg
deleted file mode 100644
index 52de57afe70a2526d246de9397d6a4bbf60f34de..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/arm_evaluator7t.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# This board is from ARM and has an samsung s3c45101x01 chip
-
-source [find target/samsung_s3c4510.cfg]
-
-#
-# FIXME:
-# Add (A) sdram configuration
-# Add (B) flash cfi programing configuration
-#
-
diff --git a/openocd-0.10.0/scripts/board/asus-rt-n16.cfg b/openocd-0.10.0/scripts/board/asus-rt-n16.cfg
deleted file mode 100644
index 78f111d380286177514986eaa97a653399b908d2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/asus-rt-n16.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# http://wikidevi.com/wiki/ASUS_RT-N16
-#
-
-set partition_list {
- CFE { Bootloader 0xbc000000 0x00040000 }
- firmware { "Kernel+rootfs" 0xbc040000 0x01fa0000 }
- nvram { "Config space" 0xbdfe0000 0x00020000 }
-}
-
-source [find target/bcm4718.cfg]
-
-# External 32MB NOR Flash (Macronix MX29GL256EHTI2I-90Q)
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0xbc000000 0x02000000 1 1 $_TARGETNAME x16_as_x8
diff --git a/openocd-0.10.0/scripts/board/asus-rt-n66u.cfg b/openocd-0.10.0/scripts/board/asus-rt-n66u.cfg
deleted file mode 100644
index 4b255cf94e6a22d9f6460468691c234c8b810759..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/asus-rt-n66u.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# http://wikidevi.com/wiki/Asus_RT-N66U
-#
-
-echo "ATTENTION: you need to solder a 4.7-10k pullup resistor to pin 21 of flash IC"
-echo "to enable JTAG, see http://wl500g.info/album.php?albumid=28&attachmentid=8991 ,"
-echo "there is an unpopulated footprint near U8.\n"
-
-set partition_list {
- CFE { Bootloader 0xbc000000 0x00040000 }
- firmware { "Kernel+rootfs" 0xbc040000 0x01fa0000 }
- nvram { "Config space" 0xbdfe0000 0x00020000 }
-}
-
-source [find target/bcm4706.cfg]
-
-# External 32MB NOR Flash (Spansion S29GL256P10TF101
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0xbc000000 0x02000000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/at91cap7a-stk-sdram.cfg b/openocd-0.10.0/scripts/board/at91cap7a-stk-sdram.cfg
deleted file mode 100644
index 9bc02e8c0383bd563d1cda73202112c6dbf7bc2c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/at91cap7a-stk-sdram.cfg
+++ /dev/null
@@ -1,165 +0,0 @@
-# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4394
-#
-# use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst srst_pulls_trst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME cap7
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x40700f0f
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -event reset-start {
- # start off real slow when we're running off internal RC oscillator
- adapter_khz 32
-}
-
-proc peek32 {address} {
- mem2array t 32 $address 1
- return $t(0)
-}
-
-# Wait for an expression to be true with a timeout
-proc wait_state {expression} {
- for {set i 0} {$i < 1000} {set i [expr $i + 1]} {
- if {[uplevel 1 $expression] == 0} {
- return
- }
- }
- return -code 1 "Timed out"
-}
-
-# Use a global variable here to be able to tinker interactively with
-# post reset jtag frequency.
-global post_reset_khz
-# Danger!!!! Even 16MHz kinda works with this target, but
-# it needs to be as low as 2000kHz to be stable.
-set post_reset_khz 2000
-
-$_TARGETNAME configure -event reset-init {
- echo "Configuring master clock"
- # disable watchdog
- mww 0xfffffd44 0xff008000
- # enable user reset
- mww 0xfffffd08 0xa5000001
- # Enable main oscillator
- mww 0xFFFFFc20 0x00000f01
- wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}
-
- # Set PLLA to 96MHz
- mww 0xFFFFFc28 0x20072801
- wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}
-
- # Select prescaler
- mww 0xFFFFFC30 0x00000004
- wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
-
- # Select master clock to 48MHz
- mww 0xFFFFFC30 0x00000006
- wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
-
- echo "Master clock ok."
-
- # Now that we're up and running, crank up speed!
- global post_reset_khz ; adapter_khz $post_reset_khz
-
- echo "Configuring the SDRAM controller..."
-
- # Configure EBI Chip select for SDRAM
- mww 0xFFFFEF30 0x00000102
-
- # Enable clock on EBI PIOs
- mww 0xFFFFFC10 0x00000004
-
- # Configure PIO for SDRAM
- mww 0xFFFFF470 0xFFFF0000
- mww 0xFFFFF474 0x00000000
- mww 0xFFFFF404 0xFFFF0000
-
- # Configure SDRAMC CR
- mww 0xFFFFEA08 0xA63392F9
-
- # NOP command
- mww 0xFFFFEA00 0x1
- mww 0x20000000 0
-
- # Precharge All Banks command
- mww 0xFFFFEA00 0x2
- mww 0x20000000 0
-
- # Set 1st CBR
- mww 0xFFFFEA00 0x00000004
- mww 0x20000010 0x00000001
-
- # Set 2nd CBR
- mww 0xFFFFEA00 0x00000004
- mww 0x20000020 0x00000002
-
- # Set 3rd CBR
- mww 0xFFFFEA00 0x00000004
- mww 0x20000030 0x00000003
-
- # Set 4th CBR
- mww 0xFFFFEA00 0x00000004
- mww 0x20000040 0x00000004
-
- # Set 5th CBR
- mww 0xFFFFEA00 0x00000004
- mww 0x20000050 0x00000005
-
- # Set 6th CBR
- mww 0xFFFFEA00 0x00000004
- mww 0x20000060 0x00000006
-
- # Set 7th CBR
- mww 0xFFFFEA00 0x00000004
- mww 0x20000070 0x00000007
-
- # Set 8th CBR
- mww 0xFFFFEA00 0x00000004
- mww 0x20000080 0x00000008
-
- # Set LMR operation
- mww 0xFFFFEA00 0x00000003
-
- # Perform LMR burst=1, lat=2
- mww 0x20000020 0xCAFEDEDE
-
- # Set Refresh Timer
- mww 0xFFFFEA04 0x00000203
-
- # Set Normal mode
- mww 0xFFFFEA00 0x00000000
- mww 0x20000000 0x00000000
-
- #remap internal memory at address 0x0
- mww 0xffffef00 0x3
-
- echo "SDRAM configuration ok."
-}
-
-$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
-
-arm7_9 dcc_downloads enable
-arm7_9 fast_memory_access enable
-
-#set _FLASHNAME $_CHIPNAME.flash
-#flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
-
diff --git a/openocd-0.10.0/scripts/board/at91eb40a.cfg b/openocd-0.10.0/scripts/board/at91eb40a.cfg
deleted file mode 100644
index d8a82a59de533f05f7b03113896f3f01a8d81b50..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/at91eb40a.cfg
+++ /dev/null
@@ -1,67 +0,0 @@
-#Script for AT91EB40a
-
-# FIXME use some standard target config, maybe create one from this
-#
-# source [find target/...cfg]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME at91eb40a
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x1f0f0f0f
-}
-
-
-#Atmel ties SRST & TRST together, at which point it makes
-#no sense to use TRST, but use TMS instead.
-#
-#The annoying thing with tying SRST & TRST together is that
-#there is no way to halt the CPU *before and during* the
-#SRST reset, which means that the CPU will run a number
-#of cycles before it can be halted(as much as milliseconds).
-reset_config srst_only srst_pulls_trst
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-#target configuration
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# speed up memory downloads
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-#flash driver
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x01000000 0x200000 2 2 $_TARGETNAME
-
-# required for usable performance. Used for lots of
-# other things than flash programming.
-$_TARGETNAME configure -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0
-
-$_TARGETNAME configure -event reset-init {
- echo "Running reset init script for AT91EB40A"
- # Reset script for AT91EB40a
- reg cpsr 0x000000D3
- mww 0xFFE00020 0x1
- mww 0xFFE00024 0x00000000
- mww 0xFFE00000 0x01002539
- mww 0xFFFFF124 0xFFFFFFFF
- mww 0xffff0010 0x100
- mww 0xffff0034 0x100
-}
-
-# This target is pretty snappy...
-adapter_khz 16000
diff --git a/openocd-0.10.0/scripts/board/at91rm9200-dk.cfg b/openocd-0.10.0/scripts/board/at91rm9200-dk.cfg
deleted file mode 100644
index f484fded1f78faf5c6b6b83c44817a9844426bc6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/at91rm9200-dk.cfg
+++ /dev/null
@@ -1,82 +0,0 @@
-#
-# This is for the "at91rm9200-DK" (not the EK) eval board.
-#
-# The two are probably very simular.... I have DK...
-#
-# It has atmel at91rm9200 chip.
-source [find target/at91rm9200.cfg]
-
-reset_config trst_and_srst
-
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { at91rm9200_dk_init }
-
-#flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x10000000 0x00200000 2 2 $_TARGETNAME
-
-
-proc at91rm9200_dk_init { } {
- # Try to run at 1khz... Yea, that slow!
- # Chip is really running @ 32khz
- adapter_khz 8
-
- mww 0xfffffc64 0xffffffff
- ## disable all clocks but system clock
- mww 0xfffffc04 0xfffffffe
- ## disable all clocks to pioa and piob
- mww 0xfffffc14 0xffffffc3
- ## master clock = slow cpu = slow
- ## (means the CPU is running at 32khz!)
- mww 0xfffffc30 0
- ## main osc enable
- mww 0xfffffc20 0x0000ff01
- ## program pllA
- mww 0xfffffc28 0x20263e04
- ## program pllB
- mww 0xfffffc2c 0x10483e0e
- ## let pll settle... sleep 100msec
- sleep 100
- ## switch to fast clock
- mww 0xfffffc30 0x202
- ## Sleep some - (go read)
- sleep 100
-
- #========================================
- # CPU now runs at 180mhz
- # SYS runs at 60mhz.
- adapter_khz 40000
- #========================================
-
-
- ## set memc for all memories
- mww 0xffffff60 0x02
- ## program smc controller
- mww 0xffffff70 0x3284
- ## init sdram
- mww 0xffffff98 0x7fffffd0
- ## all banks precharge
- mww 0xffffff80 0x02
- ## touch sdram chip to make it work
- mww 0x20000000 0
- ## sdram controller mode register
- mww 0xffffff90 0x04
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- ## sdram controller mode register
- ## Refresh, etc....
- mww 0xffffff90 0x03
- mww 0x20000080 0
- mww 0xffffff94 0x1f4
- mww 0x20000080 0
- mww 0xffffff90 0x10
- mww 0x20000000 0
- mww 0xffffff00 0x01
-
-}
diff --git a/openocd-0.10.0/scripts/board/at91rm9200-ek.cfg b/openocd-0.10.0/scripts/board/at91rm9200-ek.cfg
deleted file mode 100644
index a3f253a26c602edbcfa17ca36b2537e05fd9d7ea..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/at91rm9200-ek.cfg
+++ /dev/null
@@ -1,114 +0,0 @@
-#
-# Copyright 2010 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
-#
-# under GPLv2 Only
-#
-# This is for the "at91rm9200-ek" eval board.
-#
-#
-# It has atmel at91rm9200 chip.
-source [find target/at91rm9200.cfg]
-
-reset_config trst_and_srst
-
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { at91rm9200_ek_init }
-
-## flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
-
-# The chip may run @ 32khz, so set a really low JTAG speed
-adapter_khz 8
-
-proc at91rm9200_ek_init { } {
- # Try to run at 1khz... Yea, that slow!
- # Chip is really running @ 32khz
- adapter_khz 8
-
- mww 0xfffffc64 0xffffffff
- ## disable all clocks but system clock
- mww 0xfffffc04 0xfffffffe
- ## disable all clocks to pioa and piob
- mww 0xfffffc14 0xffffffc3
- ## master clock = slow cpu = slow
- ## (means the CPU is running at 32khz!)
- mww 0xfffffc30 0
- ## main osc enable
- mww 0xfffffc20 0x0000ff01
- ## MC_PUP
- mww 0xFFFFFF50 0x00000000
- ## MC_PUER: Memory controller protection unit disable
- mww 0xFFFFFF54 0x00000000
- ## EBI_CFGR
- mww 0xFFFFFF64 0x00000000
- ## SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
- mww 0xFFFFFF70 0x00003284
-
- ## Init Clocks
- ## CKGR_PLLAR
- mww 0xFFFFFC28 0x2000BF05
- ## PLLAR: 179,712000 MHz for PCK
- mww 0xFFFFFC28 0x20263E04
- sleep 100
- ## PMC_MCKR
- mww 0xFFFFFC30 0x00000100
- sleep 100
- ## ;MCKR : PCK/3 = MCK Master Clock = 59,904000MHz from PLLA
- mww 0xFFFFFC30 0x00000202
- sleep 100
-
- #========================================
- # CPU now runs at 180mhz
- # SYS runs at 60mhz.
- adapter_khz 40000
- #========================================
-
- ## Init SDRAM
- ## PIOC_ASR: Configure PIOC as peripheral (D16/D31)
- mww 0xFFFFF870 0xFFFF0000
- ## PIOC_BSR:
- mww 0xFFFFF874 0x00000000
- ## PIOC_PDR:
- mww 0xFFFFF804 0xFFFF0000
- ## EBI_CSA : CS1=SDRAM
- mww 0xFFFFFF60 0x00000002
- ## EBI_CFGR:
- mww 0xFFFFFF64 0x00000000
- ## SDRC_CR :
- mww 0xFFFFFF98 0x2188c155
- ## SDRC_MR : Precharge All
- mww 0xFFFFFF90 0x00000002
- ## access SDRAM
- mww 0x20000000 0x00000000
- ## SDRC_MR : Refresh
- mww 0xFFFFFF90 0x00000004
- ## access SDRAM
- mww 0x20000000 0x00000000
- ## access SDRAM
- mww 0x20000000 0x00000000
- ## access SDRAM
- mww 0x20000000 0x00000000
- ## access SDRAM
- mww 0x20000000 0x00000000
- ## access SDRAM
- mww 0x20000000 0x00000000
- ## access SDRAM
- mww 0x20000000 0x00000000
- ## access SDRAM
- mww 0x20000000 0x00000000
- ## access SDRAM
- mww 0x20000000 0x00000000
- ## SDRC_MR : Load Mode Register
- mww 0xFFFFFF90 0x00000003
- ## access SDRAM
- mww 0x20000080 0x00000000
- ## SDRC_TR : Write refresh rate
- mww 0xFFFFFF94 0x000002E0
- ## access SDRAM
- mww 0x20000000 0x00000000
- ## SDRC_MR : Normal Mode
- mww 0xFFFFFF90 0x00000000
- ## access SDRAM
- mww 0x20000000 0x00000000
-}
diff --git a/openocd-0.10.0/scripts/board/at91sam9261-ek.cfg b/openocd-0.10.0/scripts/board/at91sam9261-ek.cfg
deleted file mode 100644
index 3963e9373d81dea38edb753572645bbc5ce3a73e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/at91sam9261-ek.cfg
+++ /dev/null
@@ -1,63 +0,0 @@
-################################################################################
-# Atmel AT91SAM9261-EK eval board
-################################################################################
-
-source [find mem_helper.tcl]
-source [find target/at91sam9261.cfg]
-uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
-uplevel #0 [list source [find chip/atmel/at91/at91sam9261.cfg]]
-uplevel #0 [list source [find chip/atmel/at91/at91sam9261_matrix.cfg]]
-uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
-
-# By default S1 is open and this means that NTRST is not connected.
-# The reset_config in target/at91sam9261.cfg is overridden here.
-# (or S1 must be populated with a 0 Ohm resistor)
-reset_config srst_only
-
-scan_chain
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { at91sam9261ek_reset_init }
-$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
-
-proc at91sam9261ek_reset_init { } {
-
- ;# for ppla at 199 Mhz
- set config(master_pll_div) 15
- set config(master_pll_mul) 162
-
- ;# for ppla at 239 Mhz
- ;# set master_pll_div 1
- ;# set master_pll_mul 13
-
- set val [expr $::AT91_WDT_WDV] ;# Counter Value
- set val [expr ($val | $::AT91_WDT_WDDIS)] ;# Watchdog Disable
- set val [expr ($val | $::AT91_WDT_WDD)] ;# Delta Value
- set val [expr ($val | $::AT91_WDT_WDDBGHLT)] ;# Debug Halt
- set val [expr ($val | $::AT91_WDT_WDIDLEHLT)] ;# Idle Halt
-
- set config(wdt_mr_val) $val
-
- ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
- set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBICSA
- set config(matrix_ebicsa_val) [expr ($::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC)]
-
- ;# SDRAMC_CR - Configuration register
- set val [expr $::AT91_SDRAMC_NC_9]
- set val [expr ($val | $::AT91_SDRAMC_NR_13)]
- set val [expr ($val | $::AT91_SDRAMC_NB_4)]
- set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
- set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
- set val [expr ($val | (2 << 8))] ;# Write Recovery Delay
- set val [expr ($val | (7 << 12))] ;# Row Cycle Delay
- set val [expr ($val | (3 << 16))] ;# Row Precharge Delay
- set val [expr ($val | (2 << 20))] ;# Row to Column Delay
- set val [expr ($val | (5 << 24))] ;# Active to Precharge Delay
- set val [expr ($val | (8 << 28))] ;# Exit Self Refresh to Active Delay
-
- set config(sdram_cr_val) $val
-
- set config(sdram_tr_val) 0x13c
-
- set config(sdram_base) $::AT91_CHIPSELECT_1
- at91sam9_reset_init $config
-}
diff --git a/openocd-0.10.0/scripts/board/at91sam9263-ek.cfg b/openocd-0.10.0/scripts/board/at91sam9263-ek.cfg
deleted file mode 100644
index 645b1a7bd098b905883674491d738da7af3dc21f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/at91sam9263-ek.cfg
+++ /dev/null
@@ -1,63 +0,0 @@
-################################################################################
-# Atmel AT91SAM9263-EK eval board
-################################################################################
-
-source [find mem_helper.tcl]
-source [find target/at91sam9263.cfg]
-uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
-uplevel #0 [list source [find chip/atmel/at91/at91sam9263.cfg]]
-uplevel #0 [list source [find chip/atmel/at91/at91sam9263_matrix.cfg]]
-uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
-
-# By default S1 is open and this means that NTRST is not connected.
-# The reset_config in target/at91sam9263.cfg is overridden here.
-# (or S1 must be populated with a 0 Ohm resistor)
-reset_config srst_only
-
-scan_chain
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { at91sam9263ek_reset_init }
-$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
-
-proc at91sam9263ek_reset_init { } {
-
- set config(master_pll_div) 14
- set config(master_pll_mul) 171
-
- set val [expr $::AT91_WDT_WDV] ;# Counter Value
- set val [expr ($val | $::AT91_WDT_WDDIS)] ;# Watchdog Disable
- set val [expr ($val | $::AT91_WDT_WDD)] ;# Delta Value
- set val [expr ($val | $::AT91_WDT_WDDBGHLT)] ;# Debug Halt
- set val [expr ($val | $::AT91_WDT_WDIDLEHLT)] ;# Idle Halt
-
- set config(wdt_mr_val) $val
-
- set config(sdram_piod) 1
- ;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
- set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBI0CSA
-
- set val [expr $::AT91_MATRIX_EBI0_DBPUC]
- set val [expr ($val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V)]
- set val [expr ($val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC)]
- set config(matrix_ebicsa_val) $val
-
- ;# SDRAMC_CR - Configuration register
- set val [expr $::AT91_SDRAMC_NC_9]
- set val [expr ($val | $::AT91_SDRAMC_NR_13)]
- set val [expr ($val | $::AT91_SDRAMC_NB_4)]
- set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
- set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
- set val [expr ($val | (1 << 8))] ;# Write Recovery Delay
- set val [expr ($val | (7 << 12))] ;# Row Cycle Delay
- set val [expr ($val | (2 << 16))] ;# Row Precharge Delay
- set val [expr ($val | (2 << 20))] ;# Row to Column Delay
- set val [expr ($val | (5 << 24))] ;# Active to Precharge Delay
- set val [expr ($val | (1 << 28))] ;# Exit Self Refresh to Active Delay
-
- set config(sdram_cr_val) $val
-
- set config(sdram_tr_val) 0x13c
-
- set config(sdram_base) $::AT91_CHIPSELECT_1
- at91sam9_reset_init $config
-}
diff --git a/openocd-0.10.0/scripts/board/at91sam9g20-ek.cfg b/openocd-0.10.0/scripts/board/at91sam9g20-ek.cfg
deleted file mode 100644
index 741d6018dc467e6feecf91cd1b711187e818dc15..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/at91sam9g20-ek.cfg
+++ /dev/null
@@ -1,219 +0,0 @@
-#################################################################################################
-# #
-# Author: Gary Carlson (gcarlson@carlson-minot.com) #
-# Generated for Atmel AT91SAM9G20-EK evaluation board using Atmel SAM-ICE (J-Link) version 8. #
-# #
-#################################################################################################
-
-# FIXME use some standard target config, maybe create one from this
-#
-# source [find target/...cfg]
-
-source [find target/at91sam9g20.cfg]
-
-set _FLASHTYPE nandflash_cs3
-
-# Set reset type. Note that the AT91SAM9G20-EK board has the trst signal disconnected. Therefore
-# the reset needs to be configured for "srst_only". If for some reason, a zero-ohm jumper is
-# added to the board to connect the trst signal, then this parameter may need to be changed.
-
-reset_config srst_only
-
-adapter_nsrst_delay 200
-jtag_ntrst_delay 200
-
-# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
-# AT91SAM9 family, the microcontroller is a lump on a log without initialization. Because this family has
-# some powerful features, we want to have a special function that handles "reset init". To do this we declare
-# an event handler where these special activities can take place.
-
-scan_chain
-$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}
-$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}
-
-# NandFlash configuration and definition
-
-nand device nandflash_cs3 at91sam9 $_TARGETNAME 0x40000000 0xfffffe800
-at91sam9 cle 0 22
-at91sam9 ale 0 21
-at91sam9 rdy_busy 0 0xfffff800 13
-at91sam9 ce 0 0xfffff800 14
-
-proc read_register {register} {
- set result ""
- mem2array result 32 $register 1
- return $result(0)
-}
-
-proc at91sam9g20_reset_start { } {
-
- # Make sure that the the jtag is running slow, since there are a number of different ways the board
- # can be configured coming into this state that can cause communication problems with the jtag
- # adapter. Also since this call can be made following a "reset init" where fast memory accesses
- # are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
- # jtag speed without causing GDB keep alive problem.
-
- arm7_9 fast_memory_access disable
- adapter_khz 2 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
- halt ;# Make sure processor is halted, or error will result in following steps.
- wait_halt 10000
- mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset.
-}
-
-proc at91sam9g20_reset_init { } {
-
- # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
- # a number of steps that must be carefully performed. The process outline below follows the
- # recommended procedure outlined in the AT91SAM9G20 technical manual.
- #
- # Several key and very important things to keep in mind:
- # The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts. This
- # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
- # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
-
- mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog.
-
- # Enable the main 18.432 MHz oscillator in CKGR_MOR register.
- # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
-
- mww 0xfffffc20 0x00004001
- while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
-
- # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
- # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
-
- mww 0xfffffc28 0x202a3f01
- while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
-
- # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
- # Wait for MCKRDY signal from PMC_SR to assert.
-
- mww 0xfffffc30 0x00000101
- while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
-
- # Now change PMC_MCKR register to select PLLA.
- # Wait for MCKRDY signal from PMC_SR to assert.
-
- mww 0xfffffc30 0x00001302
- while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
-
- # Processor and master clocks are now operating and stable at maximum frequency possible:
- # -> MCLK = 132.096 MHz
- # -> PCLK = 396.288 MHz
-
- # Switch over to adaptive clocking.
-
- adapter_khz 0
-
- # Enable faster DCC downloads and memory accesses.
-
- arm7_9 dcc_downloads enable
- arm7_9 fast_memory_access enable
-
- # To be able to use external SDRAM, several peripheral configuration registers must
- # be modified. The first change is made to PIO_ASR to select peripheral functions
- # for D15 through D31. The second change is made to the PIO_PDR register to disable
- # this for D15 through D31.
-
- mww 0xfffff870 0xffff0000
- mww 0xfffff804 0xffff0000
-
- # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
- # using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on
- # the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
-
- mww 0xffffef1c 0x000100a
-
- # The AT91SAM9G20-EK evaluation board has built-in NandFlash. The exact physical timing characteristics
- # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
- # a number of registers. The first step involves setting up the general I/O pins on the processor
- # to be able to interface and support the external memory.
-
- mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
- mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
- mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
- mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
- mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
-
- # The exact physical timing characteristics for the memory type used on the current board
- # (MT29F2G08AACWP) can be established by setting four registers in order: SMC_SETUP3,
- # SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3. Computing the exact values of these registers
- # is a little tedious to do here. If you have questions about how to do this, Atmel has
- # a decent application note #6255B that covers this process.
-
- mww 0xffffec30 0x00020002 ;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
- mww 0xffffec34 0x04040404 ;# SMC_PULSE3 : 4 clock cycle pulse for all signals
- mww 0xffffec38 0x00070006 ;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
- mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
-
- mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
- mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
-
- # Identify NandFlash bank 0.
-
- nand probe nandflash_cs3
-
- # The AT91SAM9G20-EK evaluation board has build-in serial data flash also.
-
- # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations
- # are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks). If you use this file as a reference
- # for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
- # into the SDRAM_CR register. Using the memory datasheet for the -75 grade part and assuming a master clock
- # of 132.096 MHz then the SDCLK period is equal to 7.6 ns. This means the device requires:
- #
- # CAS latency = 3 cycles
- # TXSR = 10 cycles
- # TRAS = 6 cycles
- # TRCD = 3 cycles
- # TRP = 3 cycles
- # TRC = 9 cycles
- # TWR = 2 cycles
- # 9 column, 13 row, 4 banks
- # refresh equal to or less then 7.8 us for commerical/industrial rated devices
- #
- # Thus SDRAM_CR = 0xa6339279
-
- mww 0xffffea08 0xa6339279
-
- # Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
- # the starting memory location for the SDRAM.
-
- mww 0xffffea00 0x00000001
- mww 0x20000000 0
-
- # Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
- # value into the starting memory location for the SDRAM.
-
- mww 0xffffea00 0x00000002
- mww 0x20000000 0
-
- # Now issue an 'Auto-Refresh' command through the SDRAMC_MR register. Follow this operation by writing
- # zero values eight times into the starting memory location for the SDRAM.
-
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
-
- # Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
- # the starting memory location for the SDRAM.
-
- mww 0xffffea00 0x3
- mww 0x20000000 0
-
- # Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting
- # memory location for the SDRAM.
-
- mww 0xffffea00 0x0
- mww 0x20000000 0
-
- # Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
-
- mww 0xffffea04 0x0000039c
-}
-
diff --git a/openocd-0.10.0/scripts/board/atmel_at91sam7s-ek.cfg b/openocd-0.10.0/scripts/board/atmel_at91sam7s-ek.cfg
deleted file mode 100644
index d7e8486548a733c69cab3d7e4685054e82468a7d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_at91sam7s-ek.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# Atmel AT91SAM7S-EK
-# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784
-
-set CHIPNAME at91sam7s256
-
-source [find target/at91sam7sx.cfg]
-
-
diff --git a/openocd-0.10.0/scripts/board/atmel_at91sam9260-ek.cfg b/openocd-0.10.0/scripts/board/atmel_at91sam9260-ek.cfg
deleted file mode 100644
index a37f1f5d89baf6d7ad779c5f6f4b6640ce9cb19c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_at91sam9260-ek.cfg
+++ /dev/null
@@ -1,81 +0,0 @@
-################################################################################
-# Atmel AT91SAM9260-EK eval board
-#
-# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
-#
-# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
-# OSCSEL configured for external 32.768 kHz crystal
-#
-# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
-#
-################################################################################
-
-# We add to the minimal configuration.
-source [find target/at91sam9260.cfg]
-
-# By default S1 is open and this means that NTRST is not connected.
-# The reset_config in target/at91sam9260.cfg is overridden here.
-# (or S1 must be populated with a 0 Ohm resistor)
-reset_config srst_only
-
-$_TARGETNAME configure -event reset-start {
- # At reset CPU runs at 32.768 kHz.
- # JTAG Frequency must be 6 times slower if RCLK is not supported.
- jtag_rclk 5
- halt
- # RSTC_MR : enable user reset, MMU may be enabled... use physical address
- mww phys 0xfffffd08 0xa5000501
-}
-
-$_TARGETNAME configure -event reset-init {
- mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
-
- mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
- sleep 20 ;# wait 20 ms
- mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
- sleep 10 ;# wait 10 ms
- mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198.656 MHz
- sleep 20 ;# wait 20 ms
- mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
- sleep 10 ;# wait 10 ms
- mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
- sleep 10 ;# wait 10 ms
-
- # Increase JTAG Speed to 6 MHz if RCLK is not supported
- jtag_rclk 6000
-
- arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
-
- mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
- mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
-
- mww 0xffffef1c 0x00010002 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
-
- mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
-
- mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
- mww 0x20000000 0
- mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
- mww 0x20000000 0
- mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
- mww 0x20000000 0
- mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
- mww 0x20000000 0
- mww 0xffffea04 0x2b6 ;# SDRAMC_TR : Set refresh timer count to 7us
-}
diff --git a/openocd-0.10.0/scripts/board/atmel_at91sam9rl-ek.cfg b/openocd-0.10.0/scripts/board/atmel_at91sam9rl-ek.cfg
deleted file mode 100644
index e18d1fdf3a3242dbc1bb6602aa0c80eaf5ec9d5f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_at91sam9rl-ek.cfg
+++ /dev/null
@@ -1,75 +0,0 @@
-################################################################################
-#
-# Generated for Atmel AT91SAM9RL-EK evaluation board using Atmel SAM-ICE (J-Link) V6
-#
-# Atmel AT91SAM9RL : PLL = 200 MHz, MCK = 100 MHz
-# OSCSEL configured for external 32.768 kHz crystal
-#
-# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
-#
-################################################################################
-
-# We add to the minimal configuration.
-source [find target/at91sam9rl.cfg]
-
-$_TARGETNAME configure -event reset-start {
- # At reset CPU runs at 32.768 kHz.
- # JTAG Frequency must be 6 times slower if RCLK is not supported.
- jtag_rclk 5
- halt
- # RSTC_MR : enable user reset, MMU may be enabled... use physical address
- mww phys 0xfffffd08 0xa5000501
-}
-
-$_TARGETNAME configure -event reset-init {
- mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
-
- mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
- sleep 20 ;# wait 20 ms
- mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
- sleep 10 ;# wait 10 ms
- mww 0xfffffc28 0x2031bf03 ;# CKGR_PLLR: Set PLL Register for 200 MHz
- sleep 20 ;# wait 20 ms
- mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
- sleep 10 ;# wait 10 ms
- mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLL is selected (100 MHz)
- sleep 10 ;# wait 10 ms
-
- # Increase JTAG Speed to 6 MHz if RCLK is not supported
- jtag_rclk 6000
-
- arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
-
- mww 0xfffff670 0xffff0000 ;# PIO_ASR : Select peripheral function for D16..D31 (PIOB)
- mww 0xfffff604 0xffff0000 ;# PIO_PDR : Disable PIO function for D16..D31 (PIOB)
-
- mww 0xffffef20 0x00010002 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
-
- mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
-
- mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
- mww 0x20000000 0
- mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
- mww 0x20000000 0
- mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
- mww 0x20000000 0
- mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
- mww 0x20000000 0
- mww 0xffffea04 0x2b6 ;# SDRAMC_TR : Set refresh timer count to 7us
-}
diff --git a/openocd-0.10.0/scripts/board/atmel_sam3n_ek.cfg b/openocd-0.10.0/scripts/board/atmel_sam3n_ek.cfg
deleted file mode 100644
index 2ae73ebface0dc15bc507166eb6e5ec490f44963..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_sam3n_ek.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-
-#
-# Board configuration for Atmel's SAM3N-EK
-#
-
-reset_config srst_only
-
-set CHIPNAME at91sam3n4c
-
-adapter_khz 32
-
-source [find target/at91sam3nXX.cfg]
diff --git a/openocd-0.10.0/scripts/board/atmel_sam3s_ek.cfg b/openocd-0.10.0/scripts/board/atmel_sam3s_ek.cfg
deleted file mode 100644
index 38b54b7b0e8ec3499679fc78de373fbfff39677b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_sam3s_ek.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-source [find target/at91sam3sXX.cfg]
-
-$_TARGETNAME configure -event gdb-attach { reset init }
diff --git a/openocd-0.10.0/scripts/board/atmel_sam3u_ek.cfg b/openocd-0.10.0/scripts/board/atmel_sam3u_ek.cfg
deleted file mode 100644
index 13d930b1d09fcf4ab254d23cfb7be55f8229b3a1..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_sam3u_ek.cfg
+++ /dev/null
@@ -1,4 +0,0 @@
-source [find target/at91sam3u4e.cfg]
-
-reset_config srst_only
-
diff --git a/openocd-0.10.0/scripts/board/atmel_sam3x_ek.cfg b/openocd-0.10.0/scripts/board/atmel_sam3x_ek.cfg
deleted file mode 100644
index bb8cd17130f47dc23ca0c529b8fc947b235e5145..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_sam3x_ek.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-source [find target/at91sam3ax_8x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/atmel_sam4e_ek.cfg b/openocd-0.10.0/scripts/board/atmel_sam4e_ek.cfg
deleted file mode 100644
index 75e67a94f507a697b544766dc4bb327c2ef2cef9..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_sam4e_ek.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-# This is an SAM4E-EK board with a single SAM4E16 chip.
-# http://www.atmel.com/tools/sam4e-ek.aspx
-
-# chip name
-set CHIPNAME SAM4E16E
-
-source [find target/at91sam4sXX.cfg]
diff --git a/openocd-0.10.0/scripts/board/atmel_sam4l8_xplained_pro.cfg b/openocd-0.10.0/scripts/board/atmel_sam4l8_xplained_pro.cfg
deleted file mode 100644
index 80ccc9f19fda2b312a34cbb02ba085629794231f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_sam4l8_xplained_pro.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Atmel SAM4L8 Xplained Pro evaluation kit.
-# http://www.atmel.com/tools/ATSAM4L8-XPRO.aspx
-#
-
-source [find interface/cmsis-dap.cfg]
-
-# chip name
-set CHIPNAME ATSAM4LC8CA
-
-source [find target/at91sam4lXX.cfg]
diff --git a/openocd-0.10.0/scripts/board/atmel_sam4s_ek.cfg b/openocd-0.10.0/scripts/board/atmel_sam4s_ek.cfg
deleted file mode 100644
index dcfa900dc55017023b324e11a09ba5b2c632fad0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_sam4s_ek.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-source [find target/at91sam4sXX.cfg]
-
-$_TARGETNAME configure -event gdb-attach { reset init }
diff --git a/openocd-0.10.0/scripts/board/atmel_sam4s_xplained_pro.cfg b/openocd-0.10.0/scripts/board/atmel_sam4s_xplained_pro.cfg
deleted file mode 100644
index d2acc487e55ff2700a6ee498cf4726b3965acbb8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_sam4s_xplained_pro.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Atmel SAM4S Xplained Pro evaluation kit.
-# http://www.atmel.com/tools/ATSAM4S-XPRO.aspx
-#
-
-source [find interface/cmsis-dap.cfg]
-
-# chip name
-set CHIPNAME ATSAM4SD32C
-
-source [find target/at91sam4sd32x.cfg]
diff --git a/openocd-0.10.0/scripts/board/atmel_samc20_xplained_pro.cfg b/openocd-0.10.0/scripts/board/atmel_samc20_xplained_pro.cfg
deleted file mode 100644
index 1278eb7f17af7cba2ad0b35c61ab00d183e059dd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_samc20_xplained_pro.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Atmel SAMC20 Xplained Pro evaluation kit.
-#
-
-source [find interface/cmsis-dap.cfg]
-
-# chip name
-set CHIPNAME at91samc20j18
-
-source [find target/at91samdXX.cfg]
diff --git a/openocd-0.10.0/scripts/board/atmel_samc21_xplained_pro.cfg b/openocd-0.10.0/scripts/board/atmel_samc21_xplained_pro.cfg
deleted file mode 100644
index ac269305c05dd518298033217b599fdd79927423..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_samc21_xplained_pro.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Atmel SAMC21 Xplained Pro evaluation kit.
-# http://www.atmel.com/tools/ATSAMC21-XPRO.aspx
-#
-
-source [find interface/cmsis-dap.cfg]
-
-# chip name
-set CHIPNAME at91samc21j18
-
-source [find target/at91samdXX.cfg]
diff --git a/openocd-0.10.0/scripts/board/atmel_samd20_xplained_pro.cfg b/openocd-0.10.0/scripts/board/atmel_samd20_xplained_pro.cfg
deleted file mode 100644
index 525aee069cee06f95c3dca5e999932c6a33f857f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_samd20_xplained_pro.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Atmel SAMD20 Xplained Pro evaluation kit.
-# http://www.atmel.com/tools/ATSAMD20-XPRO.aspx
-#
-
-source [find interface/cmsis-dap.cfg]
-
-# chip name
-set CHIPNAME at91samd20j18
-
-source [find target/at91samdXX.cfg]
diff --git a/openocd-0.10.0/scripts/board/atmel_samd21_xplained_pro.cfg b/openocd-0.10.0/scripts/board/atmel_samd21_xplained_pro.cfg
deleted file mode 100644
index 843b0ce216f9fed237b6e8abb2a0e9ebfdf83157..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_samd21_xplained_pro.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Atmel SAMD21 Xplained Pro evaluation kit.
-#
-
-source [find interface/cmsis-dap.cfg]
-
-# chip name
-set CHIPNAME at91samd21j18
-
-source [find target/at91samdXX.cfg]
diff --git a/openocd-0.10.0/scripts/board/atmel_same70_xplained.cfg b/openocd-0.10.0/scripts/board/atmel_same70_xplained.cfg
deleted file mode 100644
index a22e801a2bd7a0b46da4d1b830e1686900ef1945..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_same70_xplained.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Atmel SAME70 Xplained evaluation kit.
-# http://www.atmel.com/tools/ATSAME70-XPLD.aspx
-#
-# Connect using the EDBG chip on the dev kit over USB
-source [find interface/cmsis-dap.cfg]
-
-set CHIPNAME atsame70q21
-
-source [find target/atsamv.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/atmel_samg53_xplained_pro.cfg b/openocd-0.10.0/scripts/board/atmel_samg53_xplained_pro.cfg
deleted file mode 100644
index 06638cf56386a71da3a59cc1a51ab3c073b4ddb9..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_samg53_xplained_pro.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Atmel SAMG53 Xplained Pro evaluation kit.
-# http://www.atmel.com/tools/ATSAMG53-XPRO.aspx
-#
-
-source [find interface/cmsis-dap.cfg]
-
-# chip name
-set CHIPNAME ATSAMG53N19
-
-source [find target/at91samg5x.cfg]
diff --git a/openocd-0.10.0/scripts/board/atmel_saml21_xplained_pro.cfg b/openocd-0.10.0/scripts/board/atmel_saml21_xplained_pro.cfg
deleted file mode 100644
index 054bda4dabd2384171d6482b326d6a6f7ef37bde..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_saml21_xplained_pro.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Atmel SAML21 Xplained Pro evaluation kit.
-#
-
-source [find interface/cmsis-dap.cfg]
-
-# chip name
-set CHIPNAME at91saml21j18
-
-source [find target/at91samdXX.cfg]
diff --git a/openocd-0.10.0/scripts/board/atmel_samr21_xplained_pro.cfg b/openocd-0.10.0/scripts/board/atmel_samr21_xplained_pro.cfg
deleted file mode 100644
index 308e2bdb74042cea31c8740f220c37985cff39e5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_samr21_xplained_pro.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Atmel SAMR21 Xplained Pro evaluation kit.
-#
-
-source [find interface/cmsis-dap.cfg]
-
-# chip name
-set CHIPNAME at91samr21g18
-
-source [find target/at91samdXX.cfg]
diff --git a/openocd-0.10.0/scripts/board/atmel_samv71_xplained_ultra.cfg b/openocd-0.10.0/scripts/board/atmel_samv71_xplained_ultra.cfg
deleted file mode 100644
index 4e0865d996182644974f17b8f7b0186575f7d027..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/atmel_samv71_xplained_ultra.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Atmel SAMV71 Xplained Ultra evaluation kit.
-# http://www.atmel.com/tools/ATSAMV71-XULT.aspx
-#
-# To connect using the EDBG chip on the dev kit over USB, you will
-# first need to source [find interface/cmsis-dap.cfg]
-# however, since this board also has a SWD+ETM connector, we don't
-# automatically source that file here.
-
-set CHIPNAME samv71
-
-source [find target/atsamv.cfg]
diff --git a/openocd-0.10.0/scripts/board/balloon3-cpu.cfg b/openocd-0.10.0/scripts/board/balloon3-cpu.cfg
deleted file mode 100644
index 468b867b27293e35c855dbc9d82c1c8c2ade51ff..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/balloon3-cpu.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-# Config for balloon3 board, cpu JTAG port. http://balloonboard.org/
-# The board has separate JTAG ports for cpu and CPLD/FPGA devices
-# Chaining is done on IO interfaces if desired.
-
-source [find target/pxa270.cfg]
-
-# The board supports separate reset lines
-# Override this in the interface config for parallel dongles
-reset_config trst_and_srst separate
-
-# flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
-# 29LV650 64Mbit Flash
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x00000000 0x800000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/bcm28155_ap.cfg b/openocd-0.10.0/scripts/board/bcm28155_ap.cfg
deleted file mode 100644
index fb729e1917695bec3731157b64d6196129b8d34e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/bcm28155_ap.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-# BCM28155_AP
-
-adapter_khz 20000
-
-set CHIPNAME bcm28155
-source [find target/bcm281xx.cfg]
-
-reset_config trst_and_srst
-
diff --git a/openocd-0.10.0/scripts/board/bt-homehubv1.cfg b/openocd-0.10.0/scripts/board/bt-homehubv1.cfg
deleted file mode 100644
index c50c7d2b6054b62b543019965fc6bf1b414bd35b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/bt-homehubv1.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# BT HomeHub v1
-#
-
-set partition_list {
- CFE { Bootloader 0xbe400000 0x00020000 }
- firmware { "Kernel+rootfs" 0xbe420000 0x007d0000 }
- fisdir { "FIS Directory" 0xbebf0000 0x0000f000 }
- nvram { "Config space" 0xbebff000 0x00001000 }
-}
-
-source [find target/bcm6348.cfg]
-
-set _FLASHNAME $_CHIPNAME.norflash
-flash bank $_FLASHNAME cfi 0xbe400000 0x00800000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/colibri.cfg b/openocd-0.10.0/scripts/board/colibri.cfg
deleted file mode 100644
index 7c1f1cb513d0192c38279de3cb7ba94893e2c4dd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/colibri.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-# Toradex Colibri PXA270
-source [find target/pxa270.cfg]
-reset_config trst_and_srst srst_push_pull
-adapter_nsrst_assert_width 40
-
-# CS0 -- one bank of CFI flash, 32 MBytes
-# the bank is 32-bits wide, two 16-bit chips in parallel
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
-
-
-
-
diff --git a/openocd-0.10.0/scripts/board/crossbow_tech_imote2.cfg b/openocd-0.10.0/scripts/board/crossbow_tech_imote2.cfg
deleted file mode 100644
index 002b5372f721f1344ef52ff411226b70fa3af048..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/crossbow_tech_imote2.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-# Crossbow Technology iMote2
-
-set CHIPNAME imote2
-source [find target/pxa270.cfg]
-
-# longer-than-normal reset delay
-adapter_nsrst_delay 800
-
-reset_config trst_and_srst separate
-
-# works for P30 flash
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/csb337.cfg b/openocd-0.10.0/scripts/board/csb337.cfg
deleted file mode 100644
index 5e225f5f549de04f21d3dabe413cbe130d36ad26..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/csb337.cfg
+++ /dev/null
@@ -1,117 +0,0 @@
-# Cogent CSB337
-# http://cogcomp.com/csb_csb337.htm
-
-source [find target/at91rm9200.cfg]
-
-# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
-
-# ETM9 trace port connector present on this board, 16 data pins.
-if { [info exists ETM_DRIVER] } {
- etm config $_TARGETNAME 16 normal half $ETM_DRIVER
- # OpenOCD may someday support a real trace port driver...
- # system config file would need to configure it.
-} else {
- etm config $_TARGETNAME 16 normal half dummy
- etm_dummy config $_TARGETNAME
-}
-
-proc csb337_clk_init { } {
- # CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
- adapter_khz 8
-
- # CKGR_MOR: start main oscillator (3.6864 MHz)
- mww 0xfffffc20 0xff01
- sleep 10
-
- # CKGR_PLLAR: start PLL A for CPU and peripherals (184.32 MHz)
- mww 0xfffffc28 0x20313e01
- # CKGR_PLLBR: start PLL B for USB timing (96 MHz, with div2)
- mww 0xfffffc2c 0x12703e18
- # let PLLs lock
- sleep 10
-
- # PMC_MCKR: switch to CPU clock = PLLA, master clock = CPU/4
- mww 0xfffffc30 0x0302
- sleep 20
-
- # CPU is in Normal Mode ... allows faster JTAG clock speed
- adapter_khz 40000
-}
-
-proc csb337_nor_init { } {
- # SMC_CSR0: adjust timings (10 wait states)
- mww 0xffffff70 0x1100318a
-
- flash probe 0
-}
-
-proc csb337_sdram_init { } {
- # enable PIOC clock
- mww 0xfffffc10 0x0010
- # PC31..PC16 are D31..D16, with internal pullups like D15..D0
- mww 0xfffff870 0xffff0000
- mww 0xfffff874 0x0
- mww 0xfffff804 0xffff0000
-
- # SDRC_CR: set timings
- mww 0xffffff98 0x2188b0d5
-
- # SDRC_MR: issue all banks precharge to SDRAM
- mww 0xffffff90 2
- mww 0x20000000 0
-
- # SDRC_MR: 8 autorefresh cycles
- mww 0xffffff90 4
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
- mww 0x20000000 0
-
- # SDRC_MR: set SDRAM mode registers (CAS, burst len, etc)
- mww 0xffffff90 3
- mww 0x20000080 0
-
- # SDRC_TR: set refresh rate
- mww 0xffffff94 0x200
- mww 0x20000000 0
-
- # SDRC_MR: normal mode, 32 bit bus
- mww 0xffffff90 0
- mww 0x20000000 0
-}
-
-# The rm9200 chip has just been reset. Bring it up far enough
-# that we can write flash or run code from SDRAM.
-proc csb337_reset_init { } {
- csb337_clk_init
-
- # EBI_CSA: CS0 = NOR, CS1 = SDRAM
- mww 0xffffff60 0x02
-
- csb337_nor_init
- csb337_sdram_init
-
- # Update CP15 control register ... we don't seem to be able to
- # read/modify/write its value through a TCL variable, so just
- # write it. Fields are zero unless listed here ... and note
- # that OpenOCD numbers this register "2", not "1" (!).
- #
- # - Core to use Async Clocking mode (so it uses 184 MHz most
- # of the time instead of limiting to the master clock rate):
- # iA(31) = 1, nF(30) = 1
- # - Icache on (it's disabled now, slowing i-fetches)
- # I(12) = 1
- # - Reserved/ones
- # 6:3 = 1
- arm920t cp15 2 0xc0001078
-}
-
-$_TARGETNAME configure -event reset-init {csb337_reset_init}
-
-arm7_9 fast_memory_access enable
diff --git a/openocd-0.10.0/scripts/board/csb732.cfg b/openocd-0.10.0/scripts/board/csb732.cfg
deleted file mode 100644
index 4d6f0e489e6fe0e44c4d95e7ac82f114151ec055..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/csb732.cfg
+++ /dev/null
@@ -1,71 +0,0 @@
-# The Cogent CSB732 board has a single i.MX35 chip
-source [find target/imx35.cfg]
-
-# Determined by trial and error
-reset_config trst_and_srst combined
-adapter_nsrst_delay 200
-jtag_ntrst_delay 200
-
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { csb732_init }
-
-# Bare-bones initialization of core clocks and SDRAM
-proc csb732_init { } {
-
- # Disable fast writing only for init
- memwrite burst disable
-
- # All delay loops are omitted.
- # We assume the interpreter latency is enough.
-
- # Allow access to all coprocessors
- arm mcr 15 0 15 1 0 0x2001
-
- # Disable MMU, caches, write buffer
- arm mcr 15 0 1 0 0 0x78
-
- # Grant manager access to all domains
- arm mcr 15 0 3 0 0 0xFFFFFFFF
-
- # Set ARM clock to 532 MHz, AHB to 133 MHz
- mww 0x53F80004 0x1000
-
- # Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
- mww 0x53F8001C 0xB2C01
-
- set ESDMISC 0xB8001010
- set ESDCFG0 0xB8001004
- set ESDCTL0 0xB8001000
-
- # Enable DDR
- mww $ESDMISC 0x4
-
- # Timing
- mww $ESDCFG0 0x007fff3f
-
- # CS0
- mww $ESDCTL0 0x92120080
-
- # Precharge all dummy write
- mww 0x80000400 0
-
- # Enable CS) auto-refresh
- mww $ESDCTL0 0xA2120080
-
- # Refresh twice (dummy writes)
- mww 0x80000000 0
- mww 0x80000000 0
-
- # Enable CS0 load mode register
- mww $ESDCTL0 0xB2120080
-
- # Dummy writes
- mwb 0x80000033 0x01
- mwb 0x81000000 0x01
-
- mww $ESDCTL0 0x82226080
- mww 0x80000000 0
-
- # Re-enable fast writing
- memwrite burst enable
-}
diff --git a/openocd-0.10.0/scripts/board/da850evm.cfg b/openocd-0.10.0/scripts/board/da850evm.cfg
deleted file mode 100644
index fbec60921ddd3557928d34b59e6d0483e94bede0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/da850evm.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#DA850 EVM board
-# http://focus.ti.com/dsp/docs/thirdparty/catalog/devtoolsproductfolder.tsp?actionPerformed=productFolder&productId=5939
-# http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit
-
-source [find target/omapl138.cfg]
-
-reset_config trst_and_srst separate
-
-#currently any pinmux/timing must be setup by UBL before openocd can do debug
-#TODO: implement pinmux/timing on reset like in board/dm365evm.cfg
diff --git a/openocd-0.10.0/scripts/board/digi_connectcore_wi-9c.cfg b/openocd-0.10.0/scripts/board/digi_connectcore_wi-9c.cfg
deleted file mode 100644
index 8a8d4c3bfb69108b4ea4fcb3dfbd1178b348e78e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/digi_connectcore_wi-9c.cfg
+++ /dev/null
@@ -1,130 +0,0 @@
-######################################
-# Target: DIGI ConnectCore Wi-9C
-######################################
-
-reset_config trst_and_srst
-
-# FIXME use some standard target config, maybe create one from this
-#
-# source [find target/...cfg]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME ns9360
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # This config file was defaulting to big endian..
- set _ENDIAN big
-}
-
-
-# What's a good fallback frequency for this board if RCLK is
-# not available??
-jtag_rclk 1000
-
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07926031
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-adapter_nsrst_delay 200
-jtag_ntrst_delay 0
-
-
-######################
-# Target configuration
-######################
-
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -event reset-init {
- mww 0x90600104 0x33313333
- mww 0xA0700000 0x00000001 ;# Enable the memory controller.
- mww 0xA0700024 0x00000006 ;# Set the refresh counter 6
- mww 0xA0700028 0x00000001 ;#
- mww 0xA0700030 0x00000001 ;# Set the precharge period
- mww 0xA0700034 0x00000004 ;# Active to precharge command period is 16 clock cycles
- mww 0xA070003C 0x00000001 ;# tAPR
- mww 0xA0700040 0x00000005 ;# tDAL
- mww 0xA0700044 0x00000001 ;# tWR
- mww 0xA0700048 0x00000006 ;# tRC 32 clock cycles
- mww 0xA070004C 0x00000006 ;# tRFC 32 clock cycles
- mww 0xA0700054 0x00000001 ;# tRRD
- mww 0xA0700058 0x00000001 ;# tMRD
- mww 0xA0700100 0x00004280 ;# Dynamic Config 0 (cs4)
- mww 0xA0700120 0x00004280 ;# Dynamic Config 1 (cs5)
- mww 0xA0700140 0x00004280 ;# Dynamic Config 2 (cs6)
- mww 0xA0700160 0x00004280 ;# Dynamic Config 3 (cs7)
- #
- mww 0xA0700104 0x00000203 ;# CAS latency is 2 at 100 MHz
- mww 0xA0700124 0x00000203 ;# CAS latency is 2 at 100 MHz
- mww 0xA0700144 0x00000203 ;# CAS latency is 2 at 100 MHz
- mww 0xA0700164 0x00000203 ;# CAS latency is 2 at 100 MHz
- #
- mww 0xA0700020 0x00000103 ;# issue SDRAM PALL command
- #
- mww 0xA0700024 0x00000001 ;# Set the refresh counter to be as small as possible
- #
- # Add some dummy writes to give the SDRAM time to settle, it needs two
- # AHB clock cycles, here we poke in the debugger flag, this lets
- # the software know that we are in the debugger
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- #
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- #
- mww 0xA0700024 0x00000030 ;# Set the refresh counter to 30
- mww 0xA0700020 0x00000083 ;# Issue SDRAM MODE command
- #
- # Next we perform a read of RAM.
- # mw = move word.
- mdw 0x00022000
- # mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
- #
- mww 0xA0700020 0x00000003 ;# issue SDRAM NORMAL command
- mww 0xA0700100 0x00084280 ;# Enable buffer access
- mww 0xA0700120 0x00084280 ;# Enable buffer access
- mww 0xA0700140 0x00084280 ;# Enable buffer access
- mww 0xA0700160 0x00084280 ;# Enable buffer access
-
- #Set byte lane state (static mem 1)"
- mww 0xA0700220 0x00000082
- #Flash Start
- mww 0xA09001F8 0x50000000
- #Flash Mask Reg
- mww 0xA09001FC 0xFF000001
- mww 0xA0700028 0x00000001
-
- # RAMAddr = 0x00020000
- # RAMSize = 0x00004000
-
- # Set the processor mode
- reg cpsr 0xd3
-}
-
-$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
-
-#####################
-# Flash configuration
-#####################
-
-#M29DW323DB - not working
-#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x50000000 0x0400000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/digilent_analog_discovery.cfg b/openocd-0.10.0/scripts/board/digilent_analog_discovery.cfg
deleted file mode 100644
index d356fc0f49a5c71e2221313939460241b31bb30e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/digilent_analog_discovery.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Digilent Analog Discovery
-#
-# http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,842,1018&Prod=ANALOG-DISCOVERY
-#
-# Config is based on data from
-# https://github.com/bvanheu/urjtag-ad/commit/8bd883ee01d134f94b79cbbd00df42cd03bafd71
-#
-
-interface ftdi
-ftdi_device_desc "Digilent USB Device"
-ftdi_vid_pid 0x0403 0x6014
-
-ftdi_layout_init 0x8008 0x800b
-
-adapter_khz 25000
-
-source [find cpld/xilinx-xc6s.cfg]
diff --git a/openocd-0.10.0/scripts/board/digilent_atlys.cfg b/openocd-0.10.0/scripts/board/digilent_atlys.cfg
deleted file mode 100644
index f298e3d73d56c67888d2bbd7e0fbfd9b52d4282c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/digilent_atlys.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-# http://digilentinc.com/atlys/
-#
-# The Digilent Atlys normally requires proprietary tools to program and will
-# enumerate as:
-# ID 1443:0007 Digilent Development board JTAG
-#
-# However, the ixo-usb-jtag project provides an alternative open firmware for
-# the on board programmer. When using thie firmware the board will then
-# enumerate as:
-# ID 16c0:06ad Van Ooijen Technische Informatica
-# (With SerialNumber == hw_nexys)
-#
-# See the interface/usb-jtag.cfg for more information.
-
-source [find interface/usb-jtag.cfg]
-source [find cpld/xilinx-xc6s.cfg]
-source [find cpld/jtagspi.cfg]
diff --git a/openocd-0.10.0/scripts/board/digilent_zedboard.cfg b/openocd-0.10.0/scripts/board/digilent_zedboard.cfg
deleted file mode 100644
index 08d1a612fc957e882ff136b59208bf7d87ef5f08..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/digilent_zedboard.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Digilent Zedboard Rev.C, Rev.D with Xilinx Zynq chip
-#
-# http://zedboard.com/product/zedboard
-#
-
-source [find interface/ftdi/digilent_jtag_smt2.cfg]
-
-reset_config srst_only srst_push_pull
-
-source [find target/zynq_7000.cfg]
diff --git a/openocd-0.10.0/scripts/board/diolan_lpc4350-db1.cfg b/openocd-0.10.0/scripts/board/diolan_lpc4350-db1.cfg
deleted file mode 100644
index bd48d9ba06aa5c92e7f13a5fb44381da6a1b0a57..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/diolan_lpc4350-db1.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Diolan LPC-4350-DB1 development board
-#
-
-set CHIPNAME lpc4350
-
-source [find target/lpc4350.cfg]
-
-flash bank $_CHIPNAME.nor cfi 0x1C000000 0x00200000 2 2 $_CHIPNAME.m4
diff --git a/openocd-0.10.0/scripts/board/diolan_lpc4357-db1.cfg b/openocd-0.10.0/scripts/board/diolan_lpc4357-db1.cfg
deleted file mode 100644
index d24cfd02c6e4b11801c33338ba4ff3d4dd7def56..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/diolan_lpc4357-db1.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Diolan LPC-4357-DB1 development board
-#
-
-set CHIPNAME lpc4357
-
-source [find target/lpc4357.cfg]
-
-flash bank $_CHIPNAME.nor cfi 0x1C000000 0x00200000 2 2 $_CHIPNAME.m4
diff --git a/openocd-0.10.0/scripts/board/dk-tm4c129.cfg b/openocd-0.10.0/scripts/board/dk-tm4c129.cfg
deleted file mode 100644
index f1171af1247755d7e76b470ef5e9b060864308f5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/dk-tm4c129.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# TI Tiva C DK-TM4C129X Connected Development Kit
-#
-# http://www.ti.com/tool/dk-tm4c129x
-#
-
-source [find interface/ti-icdi.cfg]
-
-transport select hla_jtag
-
-set WORKAREASIZE 0x8000
-set CHIPNAME tm4c129xnczad
-
-source [find target/stellaris.cfg]
diff --git a/openocd-0.10.0/scripts/board/dm355evm.cfg b/openocd-0.10.0/scripts/board/dm355evm.cfg
deleted file mode 100644
index 0c971e9a0b06bc248614b718a9300270857fd58c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/dm355evm.cfg
+++ /dev/null
@@ -1,201 +0,0 @@
-# DM355 EVM board
-# http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
-# http://c6000.spectrumdigital.com/evmdm355/
-
-source [find target/ti_dm355.cfg]
-
-reset_config trst_and_srst separate
-
-# NOTE: disable or replace this call to dm355evm_init if you're
-# debugging new UBL code from SRAM.
-$_TARGETNAME configure -event reset-init { dm355evm_init }
-
-#
-# This post-reset init is called when the MMU isn't active, all IRQs
-# are disabled, etc. It should do most of what a UBL does, except for
-# loading code (like U-Boot) into DRAM and running it.
-#
-proc dm355evm_init {} {
- global dm355
-
- echo "Initialize DM355 EVM board"
-
- # CLKIN = 24 MHz ... can't talk quickly to ARM yet
- jtag_rclk 1500
-
- ########################
- # PLL1 = 432 MHz (/8, x144)
- # ...SYSCLK1 = 216 MHz (/2) ... ARM, MJCP
- # ...SYSCLK2 = 108 MHz (/4) ... Peripherals
- # ...SYSCLK3 = 27 MHz (/16) ... VPBE, DAC
- # ...SYSCLK4 = 108 MHz (/4) ... VPSS
- # pll1.{prediv,div1,div2} are fixed
- # pll1.postdiv set in MISC (for *this* speed grade)
-
- set addr [dict get $dm355 pllc1]
- set pll_divs [dict create]
- dict set pll_divs div3 16
- dict set pll_divs div4 4
- pll_v02_setup $addr 144 $pll_divs
-
- # ARM is now running at 216 MHz, so JTAG can go faster
- jtag_rclk 20000
-
- ########################
- # PLL2 = 342 MHz (/8, x114)
- # ....SYSCLK1 = 342 MHz (/1) ... DDR PHY at 171 MHz, 2x clock
- # pll2.{postdiv,div1} are fixed
-
- set addr [dict get $dm355 pllc2]
- set pll_divs [dict create]
- dict set pll_divs div1 1
- dict set pll_divs prediv 8
- pll_v02_setup $addr 114 $pll_divs
-
- ########################
- # PINMUX
-
- # All Video Inputs
- davinci_pinmux $dm355 0 0x00007f55
- # All Video Outputs
- davinci_pinmux $dm355 1 0x00145555
- # EMIFA (NOTE: more could be set up for use as GPIOs)
- davinci_pinmux $dm355 2 0x00000c08
- # SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
- davinci_pinmux $dm355 3 0x1bff55ff
- # MMC/SD0 instead of MS; SPI0
- davinci_pinmux $dm355 4 0x00000000
-
- ########################
- # PSC setup (minimal)
-
- # DDR EMIF/13, AEMIF/14, UART0/19
- psc_enable 13
- psc_enable 14
- psc_enable 19
- psc_go
-
- ########################
- # DDR2 EMIF
-
- # VTPIOCR impedance calibration
- set addr [dict get $dm355 sysbase]
- set addr [expr $addr + 0x70]
-
- # clear CLR, LOCK, PWRDN; wait a clock; set CLR
- mmw $addr 0 0x20c0
- mmw $addr 0x2000 0
-
- # wait for READY
- while { [expr [mrw $addr] & 0x8000] == 0 } { sleep 1 }
-
- # set IO_READY; then LOCK and PWRSAVE; then PWRDN
- mmw $addr 0x4000 0
- mmw $addr 0x0180 0
- mmw $addr 0x0040 0
-
- # NOTE: this DDR2 initialization sequence borrows from
- # both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec.
-
- # reset (then re-enable) DDR controller
- psc_reset 13
- psc_go
- psc_enable 13
- psc_go
-
- # now set it up for Micron MT47H64M16HR-37E @ 171 MHz
-
- set addr [dict get $dm355 ddr_emif]
-
- # DDRPHYCR1
- mww [expr $addr + 0xe4] 0x50006404
-
- # PBBPR -- burst priority
- mww [expr $addr + 0x20] 0xfe
-
- # SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
- mmw [expr $addr + 0x08] 0x00800000 0
- mmw [expr $addr + 0x08] 0x0013c632 0x03870fff
-
- # SDTIMR0, SDTIMR1
- mww [expr $addr + 0x10] 0x2a923249
- mww [expr $addr + 0x14] 0x4c17c763
-
- # SDCR -- relock SDTIM*
- mmw [expr $addr + 0x08] 0 0x00008000
-
- # SDRCR -- refresh rate (171 MHz * 7.8usec)
- mww [expr $addr + 0x0c] 1336
-
- ########################
- # ASYNC EMIF
-
- set addr [dict get $dm355 a_emif]
-
- # slow/pessimistic timings
- set nand_timings 0x40400204
- # fast (25% faster page reads)
- #set nand_timings 0x0400008c
-
- # AWCCR
- mww [expr $addr + 0x04] 0xff
- # CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
- mww [expr $addr + 0x10] $nand_timings
- # CS1 == dm9000 Ethernet
- mww [expr $addr + 0x14] 0x00a00505
- # NANDFCR -- only CS0 has NAND
- mww [expr $addr + 0x60] 0x01
-
- # default: both chipselects to the NAND socket are used
- nand probe 0
- nand probe 1
-
- ########################
- # UART0
-
- set addr [dict get $dm355 uart0]
-
- # PWREMU_MGNT -- rx + tx in reset
- mww [expr $addr + 0x30] 0
-
- # DLL, DLH -- 115200 baud
- mwb [expr $addr + 0x20] 0x0d
- mwb [expr $addr + 0x24] 0x00
-
- # FCR - clear and disable FIFOs
- mwb [expr $addr + 0x08] 0x07
- mwb [expr $addr + 0x08] 0x00
-
- # IER - disable IRQs
- mwb [expr $addr + 0x04] 0x00
-
- # LCR - 8-N-1
- mwb [expr $addr + 0x0c] 0x03
-
- # MCR - no flow control or loopback
- mwb [expr $addr + 0x10] 0x00
-
- # PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
- mww [expr $addr + 0x30] 0xe001
-
-
- ########################
-
- # turn on icache - set I bit in cp15 register c1
- arm mcr 15 0 0 1 0 0x00051078
-}
-
-# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
-#
-# NOTE: "hwecc4" here presumes that if you're using the standard 2GB NAND
-# you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
-# use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
-# needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
-set _FLASHNAME $_CHIPNAME.boot
-nand device $_FLASHNAME davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000
-set _FLASHNAME $_CHIPNAME.flash
-nand device $_FLASHNAME davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000
-
-# FIXME
-# - support writing UBL with its header (new layout only with new ROMs)
-# - support writing ABL/U-Boot with its header (new layout)
diff --git a/openocd-0.10.0/scripts/board/dm365evm.cfg b/openocd-0.10.0/scripts/board/dm365evm.cfg
deleted file mode 100644
index 8f268c4551c22140178bebb7e9b61bf8738e2faa..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/dm365evm.cfg
+++ /dev/null
@@ -1,147 +0,0 @@
-# DM365 EVM board -- Beta
-# http://focus.ti.com/docs/toolsw/folders/print/tmdxevm365.html
-# http://support.spectrumdigital.com/boards/evmdm365
-
-source [find target/ti_dm365.cfg]
-
-# NOTE: in Rev C boards, the CPLD ignores SRST from the ARM-20 JTAG
-# connector, so it doesn't affect generation of the reset signal.
-# Accordingly, resets require something else. ICEpick could do it;
-# but its docs aren't generally available.
-#
-# At this writing, newer boards aren't available ... so assume no SRST.
-# Also ICEpick docs aren't available ... so we must use watchdog reset,
-# and hope the CPU isn't wedged or in a WFI loop (either of which can
-# block access to CPU and thus watchdog registers).
-
-reset_config trst_only
-$_TARGETNAME configure -event reset-assert "davinci_wdog_reset"
-
-# SW5.1 routes CS0: NAND vs OneNAND.
-# SW4.6:4 controls AEMIF width (8 for NAND, 16 for OneNand)
-# for boot-from-flash, those must agree with SW4.3:1 settings.
-
-if { [info exists CS0MODE] } {
- # NAND or OneNAND
- set CS0 $CS0MODE
-} else {
- set CS0 ""
- echo "WARNING: CS0 configuration not known"
- proc cs0_setup {a_emif} {}
- proc flashprobe {} {}
-}
-
-set a_emif [dict get $dm365 a_emif]
-
-# As shipped: boot from NAND.
-if { $CS0 == "NAND" } {
- echo "CS0 NAND"
-
- # NAND socket has two chipselects. Default MT29F16G08FAA chip
- # has 1GByte on each one.
- # NOTE: "hwecc4" here presumes that you're not updating anything
- # that needs infix layout (e.g. UBL, old U-Boot, etc)
- nand device low davinci $_TARGETNAME 0x02000000 hwecc4 $a_emif
- nand device high davinci $_TARGETNAME 0x02004000 hwecc4 $a_emif
-
- proc cs0_setup {a_emif} {
- global dm365
-
- # 8 bit EMIF
- davinci_pinmux $dm365 2 0x00000016
-
- # slow/pessimistic timings
- set nand_timings 0x40400204
- # fast (25% faster page reads)
- #set nand_timings 0x0400008c
-
- # CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes)
- mww [expr $a_emif + 0x10] $nand_timings
-
- # NANDFCR -- CS0 has NAND
- mww [expr $a_emif + 0x60] 0x01
- }
- proc flashprobe {} {
- nand probe 0
- nand probe 1
- }
-
-} elseif { $CS0 == "OneNAND" } {
- echo "CS0 OneNAND"
-
- # No support for this OneNAND in OpenOCD (yet) or Linux ...
- # REVISIT OneNAND timings not verified to work!
- echo "WARNING -- OneNAND not yet tested!"
-
- proc cs0_setup {a_emif} {
- global dm365
-
- # 16 bit EMIF
- davinci_pinmux $dm365 2 0x00000055
-
- # CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes)
- mww [expr $a_emif + 0x10] 0x00000001
-
- # ONENANDCTRL -- CS0 has OneNAND, enable sync reads
- mww [expr $a_emif + 0x5c] 0x0441
- }
- proc flashprobe {} { }
-}
-
-# NOTE: disable or replace this call to dm365evm_init if you're
-# debugging new UBL/NANDboot code from SRAM.
-$_TARGETNAME configure -event reset-init { dm365evm_init }
-
-#
-# This post-reset init is called when the MMU isn't active, all IRQs
-# are disabled, etc. It should do most of what a UBL does, except for
-# loading code (like U-Boot) into DRAM and running it.
-#
-proc dm365evm_init {} {
- global dm365
-
- echo "Initialize DM365 EVM board"
-
- # CLKIN = 24 MHz ... can't talk quickly to ARM yet
- adapter_khz 1500
-
- # FIXME -- PLL init
-
- ########################
- # PINMUX setup
-
- davinci_pinmux $dm365 0 0x00fd0000
- davinci_pinmux $dm365 1 0x00145555
- # mux2 controls AEMIF ... 8 bit for NAND, 16 for OneNand
- davinci_pinmux $dm365 3 0x375affff
- davinci_pinmux $dm365 4 0x55556555
-
- ########################
- # PSC setup (minimal)
-
- # DDR EMIF/13, AEMIF/14, UART0/19
- psc_enable 13
- psc_enable 14
- psc_enable 19
- psc_go
-
- # FIXME setup DDR2 (needs PLL)
-
- ########################
- # ASYNC EMIF
-
- set a_emif [dict get $dm365 a_emif]
-
- # AWCCR
- mww [expr $a_emif + 0x04] 0xff
- # CS0 == NAND or OneNAND
- cs0_setup $a_emif
- # CS1 == CPLD
- mww [expr $a_emif + 0x14] 0x00a00505
-
- # FIXME setup UART0
-
- flashprobe
-}
-
-
diff --git a/openocd-0.10.0/scripts/board/dm6446evm.cfg b/openocd-0.10.0/scripts/board/dm6446evm.cfg
deleted file mode 100644
index 0d2f6a4d26f3963dffbee485bd6cbaee48a04fd0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/dm6446evm.cfg
+++ /dev/null
@@ -1,75 +0,0 @@
-# DM6446 EVM board
-# http://focus.ti.com/docs/toolsw/folders/print/tmdsevm6446.html
-# http://c6000.spectrumdigital.com/davincievm/
-# EVM is just the board; buy that at Spectrum.
-# The "kit" from TI also has: video camera, LCD video monitor, more.
-
-source [find target/ti_dm6446.cfg]
-
-# J4 controls what CS2 hooks up to, usually NOR or NAND flash.
-# S3.1/S3.2 controls boot mode, which may force J4 and S3.3 settings.
-# S3.3 controls AEMIF bus width.
-
-if { [info exists J4_OPTION] } {
- # NOR, NAND, SRAM, ...
- set CS2_MODE $J4_OPTION
-} else {
- set CS2_MODE ""
-}
-
-# ARM boot:
-# S3.1 = 0, S3.2 = 0 ==> ROM/UBL boot via NAND (J4 == NAND)
-# S3.1 = 1, S3.2 = 0 ==> AEMIF boot (J4 == NOR or SRAM)
-# S3.1 = 0, S3.2 = 1 ==> ROM/UBL boot via HPI
-# S3.1 = 1, S3.2 = 1 ==> ROM/UBL boot via UART (J4 == don't care)
-# AEMIF bus width:
-# S3.3 = 0 ==> 8 bit bus width
-# S3.3 = 1 ==> 16 bit bus width
-# DSP boot:
-# S3.4 = 0 ==> controlled by ARM
-
-if { $CS2_MODE == "NOR" } {
- # 16 Mbytes address space; 16 bit bus width
- # (older boards used 32MB parts, with upper 16 MB unusable)
- set _FLASHNAME $_CHIPNAME.flash
- flash bank $_FLASHNAME cfi 0x02000000 0x01000000 2 2 $_TARGETNAME
- proc flashprobe {} { flash probe 0 }
-} elseif { $CS2_MODE == "NAND" } {
- # 64 Mbyte small page; 8 bit bus width
- nand device davinci $_TARGETNAME 0x02000000 hwecc1 0x01e00000
- proc flashprobe {} { nand probe 0 }
-} elseif { $CS2_MODE == "SRAM" } {
- # 4 Mbyte address space; 16 bit bus width
- # loaded via JTAG or HPI
- proc flashprobe {} {}
-} else {
- # maybe it's HPI boot? can't tell...
- echo "WARNING: CS2/flash configuration not recognized"
- proc flashprobe {} {}
-}
-
-# NOTE: disable or replace this call to dm6446evm_init if you're
-# debugging new UBL code from SRAM (for NAND boot).
-$_TARGETNAME configure -event reset-init { dm6446evm_init }
-
-#
-# This post-reset init is called when the MMU isn't active, all IRQs
-# are disabled, etc. It should do most of what a UBL does, except for
-# loading code (like U-Boot) into DRAM and running it.
-#
-proc dm6446evm_init {} {
-
- echo "Initialize DM6446 EVM board"
-
- # FIXME initialize everything:
- # - PLL1
- # - PLL2
- # - PINMUX
- # - PSC
- # - DDR
- # - AEMIF
- # - UART0
- # - icache
-
- flashprobe
-}
diff --git a/openocd-0.10.0/scripts/board/dp_busblaster_v3.cfg b/openocd-0.10.0/scripts/board/dp_busblaster_v3.cfg
deleted file mode 100644
index f21197b73b1b23bc9be7701b3e74280bffe9f514..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/dp_busblaster_v3.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Dangerous Prototypes - Bus Blaster
-#
-# http://dangerousprototypes.com/docs/Bus_Blaster
-#
-# To reprogram the on-board CPLD do:
-# openocd -f board/dp_busblaster_v3.cfg -c "adapter_khz 1000; init; svf <path_to_svf>; shutdown"
-#
-
-source [find interface/ftdi/dp_busblaster.cfg]
-ftdi_channel 1
-
-jtag newtap xc2c32a tap -expected-id 0x06e1c093 -irlen 8
diff --git a/openocd-0.10.0/scripts/board/efikamx.cfg b/openocd-0.10.0/scripts/board/efikamx.cfg
deleted file mode 100644
index 007b312beb6318149af130ab36054ff80e19cca7..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/efikamx.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# Genesi USA EfikaMX
-# http://www.genesi-usa.com/products/efika
-
-# Fall back to 6MHz if RTCK is not supported
-jtag_rclk 6000
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 6000 }
-
-source [find target/imx51.cfg]
-
-reset_config trst_only
diff --git a/openocd-0.10.0/scripts/board/efm32.cfg b/openocd-0.10.0/scripts/board/efm32.cfg
deleted file mode 100644
index d2bc9a6112f829ec5901380b458f217e6583535f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/efm32.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# Configuration for EFM32 boards with on-board SEGGER J-Link
-#
-# Tested with Tiny, Giant and Zero Gecko Starter Kit.
-#
-
-source [find interface/jlink.cfg]
-transport select swd
-adapter_khz 1000
-
-set CHIPNAME efm32
-source [find target/efm32.cfg]
diff --git a/openocd-0.10.0/scripts/board/eir.cfg b/openocd-0.10.0/scripts/board/eir.cfg
deleted file mode 100644
index a014e116bfc4c825ac4d036e269869d30ec4ede8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/eir.cfg
+++ /dev/null
@@ -1,94 +0,0 @@
-# Elector Internet Radio board
-# http://www.ethernut.de/en/hardware/eir/index.html
-
-source [find target/sam7se512.cfg]
-
-$_TARGETNAME configure -event reset-init {
- # WDT_MR, disable watchdog
- mww 0xFFFFFD44 0x00008000
-
- # RSTC_MR, enable user reset
- mww 0xfffffd08 0xa5000001
-
- # CKGR_MOR
- mww 0xFFFFFC20 0x00000601
- sleep 10
-
- # CKGR_PLLR
- mww 0xFFFFFC2C 0x00481c0e
- sleep 10
-
- # PMC_MCKR
- mww 0xFFFFFC30 0x00000007
- sleep 10
-
- # PMC_IER
- mww 0xFFFFFF60 0x00480100
-
- #
- # Enable SDRAM interface.
- #
-
- # Enable SDRAM control at PIO A.
- mww 0xfffff474 0x3f800000 ;# PIO_BSR_OFF
- mww 0xfffff404 0x3f800000 ;# PIO_PDR_OFF
-
- # Enable address bus (A0, A2-A11, A13-A17) at PIO B
- mww 0xfffff674 0x0003effd ;# PIO_BSR_OFF
- mww 0xfffff604 0x0003effd ;# PIO_PDR_OFF
-
- # Enable 16 bit data bus at PIO C
- mww 0xfffff870 0x0000ffff ;# PIO_ASR_OFF
- mww 0xfffff804 0x0000ffff ;# PIO_PDR_OFF
-
- # Enable SDRAM chip select
- mww 0xffffff80 0x00000002 ;# EBI_CSA_OFF
-
- # Set SDRAM characteristics in configuration register.
- # Hard coded values for MT48LC32M16A2 with 48MHz CPU.
- mww 0xffffffb8 0x2192215a ;# SDRAMC_CR_OFF
- sleep 10
-
- # Issue 16 bit SDRAM command: NOP
- mww 0xffffffb0 0x00000011 ;# SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
-
- # Issue 16 bit SDRAM command: Precharge all
- mww 0xffffffb0 0x00000012 ;# SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
-
- # Issue 8 auto-refresh cycles
- mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
- mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
- mww 0x20000000 0x00000000
-
- # Issue 16 bit SDRAM command: Set mode register
- mww 0xffffffb0 0x00000013 ;# SDRAMC_MR_OFF
- mww 0x20000014 0xcafedede
-
- # Set refresh rate count ???
- mww 0xffffffb4 0x00000013 ;# SDRAMC_TR_OFF
-
- # Issue 16 bit SDRAM command: Normal mode
- mww 0xffffffb0 0x00000010 ;# SDRAMC_MR_OFF
- mww 0x20000000 0x00000180
-
- #
- # Enable external reset key.
- #
- mww 0xfffffd08 0xa5000001
-}
-
diff --git a/openocd-0.10.0/scripts/board/ek-lm3s1968.cfg b/openocd-0.10.0/scripts/board/ek-lm3s1968.cfg
deleted file mode 100644
index 8d990b1983d88046e3870d7ba1c76e8ab772fc5b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ek-lm3s1968.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# TI/Luminary Stellaris LM3S1968 Evaluation Kits
-#
-# http://www.ti.com/tool/ek-lm3s1968
-#
-
-# NOTE: to use J-Link instead of the on-board interface,
-# you may also need to reduce adapter_khz to be about 1200.
-# source [find interface/jlink.cfg]
-
-# include the FT2232 interface config for on-board JTAG interface
-# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional!
-# so is using in JTAG mode, as done here.
-source [find interface/ftdi/luminary.cfg]
-
-# include the target config
-set WORKAREASIZE 0x2000
-set CHIPNAME lm3s1968
-source [find target/stellaris.cfg]
diff --git a/openocd-0.10.0/scripts/board/ek-lm3s3748.cfg b/openocd-0.10.0/scripts/board/ek-lm3s3748.cfg
deleted file mode 100644
index 36ecfcd321b802edea0388ab22e0f7ba6af25e68..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ek-lm3s3748.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# TI/Luminary Stellaris lm3s3748 Evaluation Kits
-#
-# http://www.ti.com/tool/ek-lm3s3748
-#
-
-# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional!
-# so is using it in JTAG mode, as done here.
-source [find interface/ftdi/luminary.cfg]
-
-# 20k working area
-set WORKAREASIZE 0x4000
-set CHIPNAME lm3s3748
-source [find target/stellaris.cfg]
diff --git a/openocd-0.10.0/scripts/board/ek-lm3s6965.cfg b/openocd-0.10.0/scripts/board/ek-lm3s6965.cfg
deleted file mode 100644
index c7696690dcc380d4e29760b231a8c40c13dc9efd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ek-lm3s6965.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# TI/Luminary Stellaris LM3S6965 Evaluation Kits
-#
-# http://www.ti.com/tool/ek-lm3s6965
-#
-
-# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional!
-# so is using it in JTAG mode, as done here.
-source [find interface/ftdi/luminary.cfg]
-
-# 20k working area
-set WORKAREASIZE 0x5000
-set CHIPNAME lm3s6965
-# include the target config
-source [find target/stellaris.cfg]
diff --git a/openocd-0.10.0/scripts/board/ek-lm3s811-revb.cfg b/openocd-0.10.0/scripts/board/ek-lm3s811-revb.cfg
deleted file mode 100644
index 8729f1596bc0916783044bd1805d59b0a04526ca..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ek-lm3s811-revb.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# TI/Luminary Stellaris LM3S811 Evaluation Kits (rev B and earlier)
-#
-# http://www.ti.com/tool/ek-lm3s811
-#
-
-# NOTE: newer 811-EK boards (rev C and above) shouldn't use this.
-# use board/ek-lm3s811.cfg
-source [find interface/ftdi/luminary-lm3s811.cfg]
-
-# include the target config
-set WORKAREASIZE 0x2000
-set CHIPNAME lm3s811
-source [find target/stellaris.cfg]
diff --git a/openocd-0.10.0/scripts/board/ek-lm3s811.cfg b/openocd-0.10.0/scripts/board/ek-lm3s811.cfg
deleted file mode 100644
index d7fe243e64ab9a14233ebc4931b2e453751023e6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ek-lm3s811.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# TI/Luminary Stellaris LM3S811 Evaluation Kits
-#
-# http://www.ti.com/tool/ek-lm3s811
-#
-
-# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional!
-# so is using it in JTAG mode, as done here.
-# NOTE: older '811-EK boards (before rev C) shouldn't use this.
-source [find interface/ftdi/luminary.cfg]
-
-# include the target config
-set WORKAREASIZE 0x2000
-set CHIPNAME lm3s811
-source [find target/stellaris.cfg]
diff --git a/openocd-0.10.0/scripts/board/ek-lm3s8962.cfg b/openocd-0.10.0/scripts/board/ek-lm3s8962.cfg
deleted file mode 100644
index d02ce449ac487a69a74143dfecb906612c83ea83..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ek-lm3s8962.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# TI/Luminary Stellaris LM3S8962 Evaluation Kits
-#
-# http://www.ti.com/tool/ek-lm3s8962
-#
-
-# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional!
-# so is using it in JTAG mode, as done here.
-source [find interface/ftdi/luminary.cfg]
-
-# 64k working area
-set WORKAREASIZE 0x10000
-set CHIPNAME lm3s8962
-# include the target config
-source [find target/stellaris.cfg]
diff --git a/openocd-0.10.0/scripts/board/ek-lm3s9b9x.cfg b/openocd-0.10.0/scripts/board/ek-lm3s9b9x.cfg
deleted file mode 100644
index 6dd7b31a89539fb40c6fb2e3149a6adaa72683c3..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ek-lm3s9b9x.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# TI/Luminary Stellaris LM3S9B9x Evaluation Kits
-#
-# http://www.ti.com/tool/ek-lm3s9b90
-# http://www.ti.com/tool/ek-lm3s9b92
-#
-
-# NOTE: using the bundled FT2232 JTAG/SWD/SWO interface is optional!
-# so is using in JTAG mode, as done here.
-source [find interface/ftdi/luminary-icdi.cfg]
-
-set WORKAREASIZE 0x4000
-set CHIPNAME lm3s9b9x
-source [find target/stellaris.cfg]
diff --git a/openocd-0.10.0/scripts/board/ek-lm3s9d92.cfg b/openocd-0.10.0/scripts/board/ek-lm3s9d92.cfg
deleted file mode 100644
index a0253d6462e688fb96e6db2813d99dac4c57f0c6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ek-lm3s9d92.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# TI/Luminary Stellaris LM3S9D92 Evaluation Kits
-#
-# http://www.ti.com/tool/ek-lm3s9d92
-#
-
-# NOTE: using the bundled FT2232 JTAG/SWD/SWO interface is optional!
-# so is using in JTAG mode, as done here.
-source [find interface/ftdi/luminary-icdi.cfg]
-
-# 64k working area
-set WORKAREASIZE 0x10000
-set CHIPNAME lm3s9d92
-source [find target/stellaris.cfg]
diff --git a/openocd-0.10.0/scripts/board/ek-lm4f120xl.cfg b/openocd-0.10.0/scripts/board/ek-lm4f120xl.cfg
deleted file mode 100644
index b2ebfa8cf111f24dc37ae2205793afeed4261e1f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ek-lm4f120xl.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# TI Stellaris Launchpad ek-lm4f120xl Evaluation Kits
-#
-# http://www.ti.com/tool/ek-lm4f120xl
-#
-
-#
-# NOTE: using the bundled ICDI interface is optional!
-# This interface is not ftdi based as previous boards were
-#
-source [find interface/ti-icdi.cfg]
-
-transport select hla_jtag
-
-set WORKAREASIZE 0x8000
-set CHIPNAME lm4f120h5qr
-source [find target/stellaris.cfg]
diff --git a/openocd-0.10.0/scripts/board/ek-lm4f232.cfg b/openocd-0.10.0/scripts/board/ek-lm4f232.cfg
deleted file mode 100644
index 2e3fc7ca1018cc79009eb0f34d61ef6c9a6bb973..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ek-lm4f232.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# TI Stellaris LM4F232 Evaluation Kits
-#
-# http://www.ti.com/tool/ek-lm4f232
-#
-
-#
-# NOTE: using the bundled ICDI interface is optional!
-# This interface is not ftdi based as previous boards were
-#
-source [find interface/ti-icdi.cfg]
-
-transport select hla_jtag
-
-set WORKAREASIZE 0x8000
-set CHIPNAME lm4f23x
-source [find target/stellaris.cfg]
diff --git a/openocd-0.10.0/scripts/board/ek-tm4c123gxl.cfg b/openocd-0.10.0/scripts/board/ek-tm4c123gxl.cfg
deleted file mode 100644
index 4fc1050c737f4bdce9b5894220ecd6303be90f44..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ek-tm4c123gxl.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# TI Tiva C Series ek-tm4c123gxl Launchpad Evaluation Kit
-#
-# http://www.ti.com/tool/ek-tm4c123gxl
-#
-
-source [find interface/ti-icdi.cfg]
-
-transport select hla_jtag
-
-set WORKAREASIZE 0x8000
-set CHIPNAME tm4c123gh6pm
-source [find target/stellaris.cfg]
diff --git a/openocd-0.10.0/scripts/board/ek-tm4c1294xl.cfg b/openocd-0.10.0/scripts/board/ek-tm4c1294xl.cfg
deleted file mode 100644
index b3f384c0e16484648b52abf01de22fe7f9293485..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ek-tm4c1294xl.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# TI Tiva C Series ek-tm4c1294xl Launchpad Evaluation Kit
-#
-# http://www.ti.com/tool/ek-tm4c1294xl
-#
-
-source [find interface/ti-icdi.cfg]
-
-transport select hla_jtag
-
-set WORKAREASIZE 0x8000
-set CHIPNAME tm4c1294ncpdt
-
-source [find target/stellaris.cfg]
diff --git a/openocd-0.10.0/scripts/board/embedded-artists_lpc2478-32.cfg b/openocd-0.10.0/scripts/board/embedded-artists_lpc2478-32.cfg
deleted file mode 100644
index b036cd69cd709f1b5fe7985e9fd6484a318cf78f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/embedded-artists_lpc2478-32.cfg
+++ /dev/null
@@ -1,154 +0,0 @@
-# Embedded Artists eval board for LPC2478
-# http://www.embeddedartists.com/
-
-# Target device: LPC2478
-set CCLK 72000
-source [find target/lpc2478.cfg]
-
-# Helper
-#
-proc read_register {register} {
- set result ""
- mem2array result 32 $register 1
- return $result(0)
-}
-
-proc init_board {} {
- # Delays on reset lines
- adapter_nsrst_delay 500
- jtag_ntrst_delay 1
-
- # Adaptive JTAG clocking through RTCK.
- #
- jtag_rclk 20
-
- global _TARGETNAME
- global _CHIPNAME
-
- # A working area will help speeding the flash programming
- $_TARGETNAME configure -work-area-phys 0x40000200 -work-area-size [expr 0x10000-0x200-0x20] -work-area-backup 0
-
- # External 16-bit flash at chip select CS0 (SST39VF3201-70, 4 MiB)
- flash bank $_CHIPNAME.extflash cfi 0x80000000 0x400000 2 2 $_TARGETNAME jedec_probe
-
- # Event handlers
- #
- $_TARGETNAME configure -event reset-start {
- # Back to the slow JTAG clock
- jtag_rclk 20
- }
-
- $_TARGETNAME configure -event reset-init {
- arm core_state arm
- arm7_9 dcc_downloads enable ;# Speed up downloads by using DCC transfer
- arm7_9 fast_memory_access enable
-
- # Peripheral clocks
- mww 0xE01FC0C4 0x04280FFE ;# PCONP: (reset value)
-
- # Map the user flash to the vector table area (0x00...0x3F)
- mww 0xE01FC040 0x00000001 ;# MEMMAP: User flash
-
- # Memory accelerator module
- mww 0xE01FC004 0x00000003 ;# MAMTIM: 3 clock cycles
- mww 0xE01FC000 0x00000002 ;# MAMCR: fully enabled
-
- # Enable external memory bus (32-bit SDRAM at DYCS0, 16-bit flash at CS0)
- mww 0xE002C014 0x55010115 ;# PINSEL5: P2.16=CAS, P2.17=RAS, P2.18=CLKOUT0,
- # P2.20=DYCS0, P2.24=CKEOUT0, P2.28=DQMOUT0,
- # P2.29=DQMOUT1, P2.30=DQMOUT2, P2.31=DQMOUT3
- mww 0xE002C018 0x55555555 ;# PINSEL6: P3.0...P3.15=D0...D15
- mww 0xE002C01C 0x55555555 ;# PINSEL7: P3.16...P3.31=D16...D31
- mww 0xE002C020 0x55555555 ;# PINSEL8: P4.0...P4.15=A0...A15
- mww 0xE002C024 0x50051555 ;# PINSEL9: P4.16...P4.22=A16...A22, P4.24=OE,
- # P4.25=WE, P4.30=CS0, P4.31=CS1
- mww 0xFFE08000 0x00000001 ;# EMCControl: Enable EMC
-
- # Start PLL, then use faster JTAG clock
- enable_pll
- jtag_rclk 3000
-
- # 16-bit flash @ CS0 (SST39VF3201-70)
- mww 0xFFE08200 0x00080081 ;# EMCStaticConfig0: 16 bit, PB=1, buffers on
- mww 0xFFE08204 0x00000000 ;# EMCStaticWaitWen0
- mww 0xFFE08208 0x00000000 ;# EMCStaticWaitOen0
- mww 0xFFE0820C 0x00000005 ;# EMCStaticWaitRd0
- mww 0xFFE08210 0x00000005 ;# EMCStaticWaitPage0
- mww 0xFFE08214 0x00000003 ;# EMCStaticWaitWr0
- mww 0xFFE08218 0x00000001 ;# EMCStaticWaitTurn0
-
- # 8-bit NAND @ CS1
- # TODO
-
- # 32-bit SDRAM @ DYCS0 (K4M563233G-HN75)
- mww 0xFFE08028 0x00000001 ;# EMCDynamicReadConfig
- mww 0xFFE08030 0x00000001 ;# EMCDynamicRP
- mww 0xFFE08034 0x00000003 ;# EMCDynamicRAS
- mww 0xFFE08038 0x00000005 ;# EMCDynamicSREX
- mww 0xFFE0803C 0x00000001 ;# EMCDynamicAPR
- mww 0xFFE08040 0x00000005 ;# EMCDynamicDAL
- mww 0xFFE08044 0x00000001 ;# EMCDynamicWR
- mww 0xFFE08048 0x00000005 ;# EMCDynamicRC
- mww 0xFFE0804C 0x00000005 ;# EMCDynamicRFC
- mww 0xFFE08050 0x00000005 ;# EMCDynamicXSR
- mww 0xFFE08054 0x00000001 ;# EMCDynamicRRD
- mww 0xFFE08058 0x00000001 ;# EMCDynamicMRD
- #
- mww 0xFFE08104 0x00000202 ;# EMCDynamicRasCas0
- mww 0xFFE08100 0x00005488 ;# EMCDynamicConfig0
- sleep 100
- mww 0xFFE08020 0x00000183 ;# EMCDynamicControl: Clock on continuously, NOP
- sleep 10
- mww 0xFFE08020 0x00000103 ;# EMCDynamicControl: PRECHARGE-ALL
- mww 0xFFE08024 0x00000046 ;# EMCDynamicRefresh
- sleep 100
- mww 0xFFE08020 0x00000083 ;# EMCDynamicControl: MODE
- mdw 0xA0011000 1 ;# Set SDRAM mode register
- mww 0xFFE08020 0x00000000 ;# EMCDynamicControl: NORMAL
- mww 0xFFE08100 0x00085488 ;# EMCDynamicConfig0: Enable buffers
- }
-
- $_TARGETNAME configure -event gdb-attach {
- # Without this gdb-attach will first time as probe will fail
- reset init
- }
-}
-
-# Enable the PLL.
-# Generate maximum CPU clock (72 MHz) Run from internal RC oscillator.
-# Note: The PLL output runs at a frequency N times the desired CPU clock.
-# It in unavoidable that the CPU clock drops down to (4 MHz/N) during
-# the initialization!
-# Here: N=4
-# Note that if the PLL is already active at the time this script is
-# called, the effective value of N is the value of CCLKCFG at that time!
-#
-proc enable_pll {} {
- # Disconnect PLL in case it is already connected
- if {[expr [read_register 0xE01FC080] & 0x03] == 3} {
- # Disconnect it, but leave it enabled
- # (This MUST be done in two steps)
- mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL
- mww 0xE01FC08C 0x000000AA ;# PLLFEED
- mww 0xE01FC08C 0x00000055 ;# PLLFEED
- }
- # Disable PLL (as it might already be enabled at this time!)
- mww 0xE01FC080 0x00000000 ;# PLLCON: disable PLL
- mww 0xE01FC08C 0x000000AA ;# PLLFEED
- mww 0xE01FC08C 0x00000055 ;# PLLFEED
-
- # Setup PLL to generate 288 MHz from internal RC oscillator
- mww 0xE01FC10C 0x00000000 ;# CLKSRCSEL: IRC
- mww 0xE01FC084 0x00000023 ;# PLLCFG: N=1, M=36
- mww 0xE01FC08C 0x000000AA ;# PLLFEED
- mww 0xE01FC08C 0x00000055 ;# PLLFEED
- mww 0xE01FC080 0x00000001 ;# PLLCON: enable PLL
- mww 0xE01FC08C 0x000000AA ;# PLLFEED
- mww 0xE01FC08C 0x00000055 ;# PLLFEED
- sleep 100
- mww 0xE01FC104 0x00000003 ;# CCLKCFG: divide by 4 (72 MHz)
- mww 0xE01FC080 0x00000003 ;# PLLCON: connect PLL
- mww 0xE01FC08C 0x000000AA ;# PLLFEED
- mww 0xE01FC08C 0x00000055 ;# PLLFEED
-}
-
diff --git a/openocd-0.10.0/scripts/board/emcraft_twr-vf6-som-bsb.cfg b/openocd-0.10.0/scripts/board/emcraft_twr-vf6-som-bsb.cfg
deleted file mode 100644
index 3818b6793d524e81ff986b2c036c4319012d5748..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/emcraft_twr-vf6-som-bsb.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# EmCraft Systems TWR-VF6-SOM-BSB
-#
-# http://www.emcraft.com/products/259#twr-kit
-#
-
-source [find board/emcraft_vf6-som.cfg]
-
-reset_config srst_only srst_nogate
diff --git a/openocd-0.10.0/scripts/board/emcraft_vf6-som.cfg b/openocd-0.10.0/scripts/board/emcraft_vf6-som.cfg
deleted file mode 100644
index 558651683d8d1523c309f341bbad25d3c1587ea9..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/emcraft_vf6-som.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# EmCraft Systems Vybrid VF6 SOM
-#
-# http://www.emcraft.com/products/259#som
-#
-
-set CHIPNAME vf610
-source [find target/vybrid_vf6xx.cfg]
diff --git a/openocd-0.10.0/scripts/board/ethernut3.cfg b/openocd-0.10.0/scripts/board/ethernut3.cfg
deleted file mode 100644
index ad455273378346b1abc1ef3c3eb7a12837de0057..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ethernut3.cfg
+++ /dev/null
@@ -1,86 +0,0 @@
-#
-# Ethernut 3 board configuration file
-#
-# http://www.ethernut.de/en/hardware/enut3/
-
-
-# AT91R40008-66AU ARM7TDMI Microcontroller
-# 256kB internal RAM
-source [find target/at91r40008.cfg]
-
-
-# AT49BV322A-70TU NOR Flash
-# 2M x 16 mode at address 0x10000000
-# Common flash interface supported
-#
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x10000000 0x400000 2 2 $_TARGETNAME
-
-
-# Micrel MIC2775-29YM5 Supervisor
-# Reset output will remain active for 280ms (maximum)
-#
-adapter_nsrst_delay 300
-jtag_ntrst_delay 300
-
-
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-adapter_khz 16000
-
-
-# Target events
-#
-$_TARGETNAME configure -event reset-init { board_init }
-
-# Initialize board hardware
-#
-proc board_init { } {
- board_remap
- flash probe 0
-}
-
-# Memory remap
-#
-proc board_remap {{VERBOSE 0}} {
- # CS0: NOR flash
- # 16MB @ 0x10000000
- # 16-bit data bus
- # 4 wait states
- #
- mww 0xffe00000 0x1000212d
-
- # CS1: Ethernet controller
- # 1MB @ 0x20000000
- # 16-bit data bus
- # 2 wait states
- # Byte select access
- #
- mww 0xffe00004 0x20003025
-
- # CS2: CPLD registers
- # 1MB @ 0x21000000
- # 8-bit data bus
- # 2 wait states
- #
- mww 0xffe00008 0x21002026
-
- # CS3: Expansion bus
- # 1MB @ 0x22000000
- # 8-bit data bus
- # 8 wait states
- #
- mww 0xffe00010 0x22002e3e
-
- # Remap command
- #
- mww 0xffe00020 0x00000001
-
- if {$VERBOSE != 0} {
- echo "0x00000000 RAM"
- echo "0x10000000 Flash"
- echo "0x20000000 Ethernet"
- echo "0x21000000 CPLD"
- echo "0x22000000 Expansion"
- }
-}
diff --git a/openocd-0.10.0/scripts/board/frdm-kl25z.cfg b/openocd-0.10.0/scripts/board/frdm-kl25z.cfg
deleted file mode 100644
index 89ee32deea4c421904b101f38387dcec4732c23e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/frdm-kl25z.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-# This is an Freescale Freedom eval board with a single MKL25Z128VLK4 chip.
-# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=FRDM-KL25Z
-#
-
-source [find interface/cmsis-dap.cfg]
-
-# increase working area to 16KB
-set WORKAREASIZE 0x4000
-
-# chip name
-set CHIPNAME MKL25Z128VLK4
-
-reset_config srst_only
-
-source [find target/kl25.cfg]
diff --git a/openocd-0.10.0/scripts/board/frdm-kl46z.cfg b/openocd-0.10.0/scripts/board/frdm-kl46z.cfg
deleted file mode 100644
index eee4d8ead7db01bf40ff65899ddadbbfc5d896f6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/frdm-kl46z.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-# This is an Freescale Freedom eval board with a single MKL46Z256VLL4 chip.
-# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=FRDM-KL46Z
-#
-
-source [find interface/cmsis-dap.cfg]
-
-# increase working area to 16KB
-set WORKAREASIZE 0x4000
-
-# chip name
-set CHIPNAME MKL46Z256VLL4
-
-reset_config srst_only
-
-source [find target/kl46.cfg]
diff --git a/openocd-0.10.0/scripts/board/fsl_imx6q_sabresd.cfg b/openocd-0.10.0/scripts/board/fsl_imx6q_sabresd.cfg
deleted file mode 100644
index 797e2de5f5a0583f6e968d766ea1516545d88fcb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/fsl_imx6q_sabresd.cfg
+++ /dev/null
@@ -1,149 +0,0 @@
-#
-# Board configuration file for the Freescale IMX6Q Sabre SD EVM
-#
-# This board does not have an embedded JTAG adapter, you must source
-# a suitable adapter configuration before sourcing this file.
-
-# Sabre SD has a standard ARM-20 JTAG connector with
-# nTRST and nSRST available.
-reset_config trst_and_srst
-
-# the only possible transport is JTAG
-transport select jtag
-
-# iMX6Q POR gates JTAG and the chip is completely incommunicado
-# over JTAG for at least 10ms after nSRST is deasserted
-adapter_nsrst_delay 11
-
-# Source generic iMX6Q target configuration
-set CHIPNAME imx6q
-source [find target/imx6.cfg]
-
-# function to apply initial configuration after a reset. It
-# provides a basic pad configuration and also DDR memory and clocks
-# sufficient to load and execute a boot loader (e.g. barebox) from
-# DDR memory. This list is extracted from the barebox flash image
-# header.
-proc apply_dcd { } {
- mww 0x020e05a8 0x00000030
- mww 0x020e05b0 0x00000030
- mww 0x020e0524 0x00000030
- mww 0x020e051c 0x00000030
- mww 0x020e0518 0x00000030
- mww 0x020e050c 0x00000030
- mww 0x020e05b8 0x00000030
- mww 0x020e05c0 0x00000030
- mww 0x020e05ac 0x00020030
- mww 0x020e05b4 0x00020030
- mww 0x020e0528 0x00020030
- mww 0x020e0520 0x00020030
- mww 0x020e0514 0x00020030
- mww 0x020e0510 0x00020030
- mww 0x020e05bc 0x00020030
- mww 0x020e05c4 0x00020030
- mww 0x020e056c 0x00020030
- mww 0x020e0578 0x00020030
- mww 0x020e0588 0x00020030
- mww 0x020e0594 0x00020030
- mww 0x020e057c 0x00020030
- mww 0x020e0590 0x00003000
- mww 0x020e0598 0x00003000
- mww 0x020e058c 0x00000000
- mww 0x020e059c 0x00003030
- mww 0x020e05a0 0x00003030
- mww 0x020e0784 0x00000030
- mww 0x020e0788 0x00000030
- mww 0x020e0794 0x00000030
- mww 0x020e079c 0x00000030
- mww 0x020e07a0 0x00000030
- mww 0x020e07a4 0x00000030
- mww 0x020e07a8 0x00000030
- mww 0x020e0748 0x00000030
- mww 0x020e074c 0x00000030
- mww 0x020e0750 0x00020000
- mww 0x020e0758 0x00000000
- mww 0x020e0774 0x00020000
- mww 0x020e078c 0x00000030
- mww 0x020e0798 0x000c0000
- mww 0x021b081c 0x33333333
- mww 0x021b0820 0x33333333
- mww 0x021b0824 0x33333333
- mww 0x021b0828 0x33333333
- mww 0x021b481c 0x33333333
- mww 0x021b4820 0x33333333
- mww 0x021b4824 0x33333333
- mww 0x021b4828 0x33333333
- mww 0x021b0018 0x00081740
- mww 0x021b001c 0x00008000
- mww 0x021b000c 0x555a7975
- mww 0x021b0010 0xff538e64
- mww 0x021b0014 0x01ff00db
- mww 0x021b002c 0x000026d2
- mww 0x021b0030 0x005b0e21
- mww 0x021b0008 0x09444040
- mww 0x021b0004 0x00025576
- mww 0x021b0040 0x00000027
- mww 0x021b0000 0x831a0000
- mww 0x021b001c 0x04088032
- mww 0x021b001c 0x0408803a
- mww 0x021b001c 0x00008033
- mww 0x021b001c 0x0000803b
- mww 0x021b001c 0x00428031
- mww 0x021b001c 0x00428039
- mww 0x021b001c 0x09408030
- mww 0x021b001c 0x09408038
- mww 0x021b001c 0x04008040
- mww 0x021b001c 0x04008048
- mww 0x021b0800 0xa1380003
- mww 0x021b4800 0xa1380003
- mww 0x021b0020 0x00005800
- mww 0x021b0818 0x00022227
- mww 0x021b4818 0x00022227
- mww 0x021b083c 0x434b0350
- mww 0x021b0840 0x034c0359
- mww 0x021b483c 0x434b0350
- mww 0x021b4840 0x03650348
- mww 0x021b0848 0x4436383b
- mww 0x021b4848 0x39393341
- mww 0x021b0850 0x35373933
- mww 0x021b4850 0x48254A36
- mww 0x021b080c 0x001f001f
- mww 0x021b0810 0x001f001f
- mww 0x021b480c 0x00440044
- mww 0x021b4810 0x00440044
- mww 0x021b08b8 0x00000800
- mww 0x021b48b8 0x00000800
- mww 0x021b001c 0x00000000
- mww 0x021b0404 0x00011006
- mww 0x020c4068 0x00c03f3f
- mww 0x020c406c 0x0030fc03
- mww 0x020c4070 0x0fffc000
- mww 0x020c4074 0x3ff00000
- mww 0x020c4078 0x00fff300
- mww 0x020c407c 0x0f0000c3
- mww 0x020c4080 0x000003ff
- mww 0x020e0010 0xf00000cf
- mww 0x020e0018 0x007f007f
- mww 0x020e001c 0x007f007f
-}
-
-# disable watchdog
-proc disable_wdog { } {
- mwh 0x020bc000 0x30
-}
-
-# This function applies the initial configuration after a "reset init"
-# command
-proc imx6q_sabresd_init { } {
- disable_wdog
- apply_dcd
-}
-
-# prevent cortex-a code from asserting SRST again
-$_TARGETNAME.0 configure -event reset-assert { }
-# hook the init function into the reset-init event
-$_TARGETNAME.0 configure -event reset-init { imx6q_sabresd_init }
-# make sure target is halted when gdb attaches
-$_TARGETNAME.0 configure -event gdb-attach { halt }
-# set a slow default JTAG clock, can be overridden later
-adapter_khz 1000
diff --git a/openocd-0.10.0/scripts/board/glyn_tonga2.cfg b/openocd-0.10.0/scripts/board/glyn_tonga2.cfg
deleted file mode 100644
index 17ed3cf20b1f8e6451b3b81cccfc6b410411a226..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/glyn_tonga2.cfg
+++ /dev/null
@@ -1,200 +0,0 @@
-#
-# Glyn Tonga2 SO-DIMM CPU module (Toshiba TMPA900CMXBG, ARM9)
-#
-# http://toshiba-mikrocontroller.de/sites/TMPA900CPUBOARDStarter.htm
-#
-# Hardware on the S0-DIMM module:
-# - Toshiba TMPA900CMXBG (ARM9, ARM926EJ-S, max. 200MHz)
-# - DDR SDRAM: Hynix H5MS5162DFR-J3M (64Mbyte, x16, 1.8V, 166/83MHz at CL3/2)
-# - NAND flash: Samsung K9F2G08U0B-PIB0 (256M x 8 Bit, 3.3V)
-# - Ethernet: SMSC LAN9221I-ABZJ (10/100Mbit, Non-PCI, 16 bit interface)
-#
-
-source [find target/tmpa900.cfg]
-
-########################
-# Target configuration #
-########################
-
-# Initial JTAG speed should not exceed 1/6 of the initial CPU clock
-# frequency (24MHz). Be conservative and use 1/8 of the frequency.
-# (24MHz / 8 = 3MHz)
-adapter_khz 3000
-
-$_TARGETNAME configure -event reset-start {
- # Upon reset, set the JTAG frequency to 3MHz again, see above.
- echo "Setting JTAG speed to 3MHz until clocks are initialized."
- adapter_khz 3000
-
- # Halt the CPU.
- halt
-
- # Disable faster memory access for now.
- arm7_9 fast_memory_access disable
-}
-
-$_TARGETNAME configure -event reset-init {
- # Setup clocks, and initialize SRAM and DDR SDRAM.
- tonga2_init
-
- # At this point the CPU is running at 192MHz, increase JTAG speed.
- # Tests showed that 15MHz works OK, higher speeds can cause problems,
- # though. Not sure if this is a CPU issue or JTAG adapter issue.
- echo "Increasing JTAG speed to 15MHz."
- adapter_khz 15000
-
- # Enable faster memory access.
- arm7_9 fast_memory_access enable
-}
-
-proc tonga2_init { } {
- ######################
- # PLL initialization #
- ######################
-
- # Clock overview (see datasheet chapter 3.5.2, page 57):
- # - fs: Low-frequency oscillator
- # - fOSCH: High-frequency oscillator (24MHz on this board)
- # - fPLL = fOSCH * multiplier (where multiplier can be 6 or 8)
- # - fFCLK = fPLL / gear (where gear can be 1/2/4/8)
- # - fHCLK is always fFCLK/2. fPCLK is also fFCLK/2.
- #
- # We select multiplier = 8 and gear = 1, so
- # fFCLK = fOSCH * 8 / 1 = 192MHz.
-
- # SYSCR3 (System Control Register 3): Disable and configure PLL.
- # - PLL operation control: off
- # - PLL constant value setting 1: always 0, as per datasheet
- # - PLL constant value setting 2: x8 (multiplier = 8)
- mww 0xf005000c 0x00000007
-
- # SYSCR4 (System Control Register 4): Configure PLL.
- # - PLL constant value setting 3: 140MHz or more
- # - PLL constant value setting 4: always 1, as per datasheet
- # - PLL constant value setting 5: 140MHz or more
- mww 0xf0050010 0x00000065
-
- # SYSCR3 (System Control Register 3): Enable PLL.
- # - PLL operation control: on
- # - All other bits remain set as above.
- mww 0xf005000c 0x00000087
-
- # Wait for PLL to stabilize.
- sleep 10
-
- # SYSCR2 (System Control Register 2): Switch from fOSCH to fPLL.
- # - Selection of the PLL output clock: fPLL
- mww 0xf0050008 0x00000002
-
- # SYSCR1 (System Control Register 1):
- # - Clock gear programming: fc/1 (i.e., gear = 1, don't divide).
- mww 0xf0050004 0x00000000
-
- # CLKCR5 (Clock Control Register 5): Set bits 3 and 6. The datasheet
- # says the bits are reserved, but also recommends "Write as one".
- mww 0xf0050054 0x00000048
-
-
- ##############################################################
- # Dynamic Memory Controller (DMC) / DDR SDRAM initialization #
- ##############################################################
-
- # PMC (Power Management Controller):
- # PMCDRV (External Port "Driverbility" control register):
- # Bits DRV_MEM0/DRV_MEM1 (memory relation port drive power):
- mww 0xf0020260 0x00000003 ;# Select 1.8V +/- 0.1V
-
- # Setup DDR SDRAM timing parameters for our specific chip.
- mww 0xf4310014 0x00000004 ;# cas_latency = 2
- mww 0xf4310018 0x00000001 ;# t_dqss = 1
- mww 0xf431001c 0x00000002 ;# t_mrd = 2
- mww 0xf4310020 0x0000000a ;# t_ras = 10
- mww 0xf4310024 0x0000000a ;# t_rc = 10
- mww 0xf4310028 0x00000013 ;# t_rcd = 3, schedule_rcd = 2
- mww 0xf431002c 0x0000010a ;# t_rfc = 10, schedule_rfc = 8
- mww 0xf4310030 0x00000013 ;# t_rp = 3, schedule_rp = 2
- mww 0xf4310034 0x00000002 ;# t_rrd = 2
- mww 0xf4310038 0x00000002 ;# t_wr = 2
- mww 0xf431003c 0x00000001 ;# t_wtr = 1
- mww 0xf4310040 0x0000000a ;# t_xp = 10
- mww 0xf4310044 0x0000000c ;# t_xsr = 12
- mww 0xf4310048 0x00000014 ;# t_esr = 20
-
- # dmc_memory_cfg_5 (DMC Memory Configuration register):
- # Set memory configuration:
- # column_bits = 10, row_bits = 13, ap-bit = 10, power_down_prd = 0,
- # auto_power_down = disable, stop_mem_clock = disable, memory_burst = 4
- mww 0xf431000c 0x00010012
-
- # dmc_user_config_5 (DMC user_config register):
- # Data bus width of DDR SDRAM: 16 bit
- mww 0xf4310304 0x00000058
-
- # dmc_refresh_prd_5 (DMC Refresh Period register):
- # Auto refresh: every 2656 (0xa60) DMCSCLK periods.
- mww 0xf4310010 0x00000a60
-
- # dmc_chip_0_cfg_5 (DMC chip_0_cfg registers):
- # - SDRAM address structure: bank, row, column
- # - address_match = 01000000 (start address [31:24])
- # - address_mask = 11111100 (start address [31:24] mask value)
- mww 0xf4310200 0x000140fc
-
- # Initialize the DDR SDRAM chip.
- # dmc_direct_cmd_5 (DMC Direct Command register).
- # See datasheet chapter 3.10.5.1, page 268.
- mww 0xf4310008 0x000c0000 ;# RAM init: NOP
- mww 0xf4310008 0x00000000 ;# RAM init: Precharge all
- mww 0xf4310008 0x00040000 ;# RAM init: Autorefresh
- mww 0xf4310008 0x00040000 ;# RAM init: Autorefresh
- mww 0xf4310008 0x00080032 ;# RAM init: addr_13_to_0 = 0x32
- mww 0xf4310008 0x000c0000 ;# RAM init: NOP
- mww 0xf4310008 0x000a0000 ;# RAM init: bank_addr = bank 2
-
- # dmc_id_<0-5>_cfg_5 (DMC id_<0-5>_cfg registers):
- # Set min./max. QoS values.
- # - 0x5: Enable QoS, max. QoS = 1
- # - 0xb: Enable QoS, min. QoS = 2
- mww 0xf4310100 0x00000005 ;# AHB0: CPU Data
- mww 0xf4310104 0x00000005 ;# AHB1: CPU Inst
- mww 0xf4310108 0x0000000b ;# AHB2: LCDC
- mww 0xf431010c 0x00000005 ;# AHB3: LCDDA, USB
- mww 0xf4310110 0x00000005 ;# AHB4: DMA1
- mww 0xf4310114 0x00000005 ;# AHB5: DMA2
-
- # dmc_memc_cmd_5 (DMC Memory Controller Command register):
- # Change DMC state to ready.
- mww 0xf4310004 0x00000000 ;# memc_cmd = "Go"
-
- # EBI: SMC Timeout register
- mww 0xf00a0050 0x00000001 ;# smc_timeout = 1
-
-
- ########################################################
- # Static Memory Controller (SMC) / SRAM initialization #
- ########################################################
-
- # smc_set_cycles_5 (SMC Set Cycles register):
- # tRC = 10, tWC = 10, tCEOE = 7, tWP = 5, tPC=2, tTR=2
- mww 0xf4311014 0x0004afaa
-
- # smc_set_opmode_5 (SMC Set Opmode register):
- # Memory data bus width = 16 bits, async read mode, read burst
- # length = 1 beat, async write mode, write burst length = 1 beat,
- # byte enable (SMCBE0-1) timing = SMCCSn timing, memory burst boundary
- # split setting = burst can cross any address boundary
- mww 0xf4311018 0x00000001
-
- # smc_direct_cmd_5 (SMC Direct Command register):
- # cmd_type = UpdateRegs, chip_select = CS1
- mww 0xf4311010 0x00c00000
-
- echo "Clocks, SRAM, and DDR SDRAM are now initialized."
-}
-
-#######################
-# Flash configuration #
-#######################
-
-# TODO: Implement NAND support.
-
diff --git a/openocd-0.10.0/scripts/board/gumstix-aerocore.cfg b/openocd-0.10.0/scripts/board/gumstix-aerocore.cfg
deleted file mode 100644
index ba217c0431eabe8036780d82058c0a85069abdfb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/gumstix-aerocore.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# JTAG for the STM32F4x chip used on the Gumstix AeroCore is available on
-# the first interface of a Quad FTDI chip. nTRST is bit 4.
-interface ftdi
-ftdi_vid_pid 0x0403 0x6011
-
-ftdi_layout_init 0x0000 0x001b
-ftdi_layout_signal nTRST -data 0x0010
-
-source [find target/stm32f4x.cfg]
-reset_config trst_only
diff --git a/openocd-0.10.0/scripts/board/hammer.cfg b/openocd-0.10.0/scripts/board/hammer.cfg
deleted file mode 100644
index ea3da81230c887ebe7aa57e3d966e93e5632fbed..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/hammer.cfg
+++ /dev/null
@@ -1,37 +0,0 @@
-# Target Configuration for the TinCanTools S3C2410 Based Hammer Module
-# http://www.tincantools.com
-
-source [find target/samsung_s3c2410.cfg]
-
-$_TARGETNAME configure -event reset-init {
- # Reset Script for the TinCanTools S3C2410 Based Hammer Module
- # http://www.tincantools.com
- #
- # Setup primary clocks and initialize the SDRAM
- mww 0x53000000 0x00000000
- mww 0x4a000008 0xffffffff
- mww 0x4a00000c 0x000007ff
- mww 0x4c000000 0x00ffffff
- mww 0x4c000014 0x00000003
- mww 0x4c000004 0x000a1031
- mww 0x48000000 0x11111122
- mww 0x48000004 0x00000700
- mww 0x48000008 0x00000700
- mww 0x4800000c 0x00000700
- mww 0x48000010 0x00000700
- mww 0x48000014 0x00000700
- mww 0x48000018 0x00000700
- mww 0x4800001c 0x00018005
- mww 0x48000020 0x00018005
- mww 0x48000024 0x009c0459
- mww 0x48000028 0x000000b2
- mww 0x4800002c 0x00000030
- mww 0x48000030 0x00000030
- flash probe 0
-}
-
-
-#flash configuration
-#flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target> [driver_options ...]
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x00000000 0x1000000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/hilscher_nxdb500sys.cfg b/openocd-0.10.0/scripts/board/hilscher_nxdb500sys.cfg
deleted file mode 100644
index 77073e729ed43b728bac5ab5174872bbed292952..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/hilscher_nxdb500sys.cfg
+++ /dev/null
@@ -1,40 +0,0 @@
-################################################################################
-# Author: Michael Trensch (MTrensch@googlemail.com)
-################################################################################
-
-source [find target/hilscher_netx500.cfg]
-
-reset_config trst_and_srst
-adapter_nsrst_delay 500
-jtag_ntrst_delay 500
-
-$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
-
-$_TARGETNAME configure -event reset-init {
- halt
-
- arm7_9 fast_memory_access enable
- arm7_9 dcc_downloads enable
-
- sdram_fix
-
- puts "Configuring SDRAM controller for paired K4S561632C (64MB) "
- mww 0x00100140 0
- mww 0x00100144 0x03C13261
- mww 0x00100140 0x030D0121
-
- puts "Configuring SRAM nCS0 for 150ns paired Par. Flash (x32)"
- mww 0x00100100 0x0201000E
-
- flash probe 0
-}
-
-#####################
-# Flash configuration
-#####################
-
-#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
-flash bank parflash cfi 0xC0000000 0x02000000 4 4 $_TARGETNAME
-
-init
-reset init
diff --git a/openocd-0.10.0/scripts/board/hilscher_nxeb500hmi.cfg b/openocd-0.10.0/scripts/board/hilscher_nxeb500hmi.cfg
deleted file mode 100644
index 64391561e68246e4de31da4eeab9f7a5f4380649..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/hilscher_nxeb500hmi.cfg
+++ /dev/null
@@ -1,40 +0,0 @@
-################################################################################
-# Author: Michael Trensch (MTrensch@googlemail.com)
-################################################################################
-
-source [find target/hilscher_netx500.cfg]
-
-reset_config trst_and_srst
-adapter_nsrst_delay 500
-jtag_ntrst_delay 500
-
-$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
-
-$_TARGETNAME configure -event reset-init {
- halt
-
- arm7_9 fast_memory_access enable
- arm7_9 dcc_downloads disable
-
- sdram_fix
-
- puts "Configuring SDRAM controller for MT48LC8M32 (32MB) "
- mww 0x00100140 0
- mww 0x00100144 0x03C23251
- mww 0x00100140 0x030D0111
-
- puts "Configuring SRAM nCS0 for 150ns Par. Flash (x16)"
- mww 0x00100100 0x0101000E
-
- flash probe 0
-}
-
-#####################
-# Flash configuration
-#####################
-
-#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
-flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
-
-init
-reset init
diff --git a/openocd-0.10.0/scripts/board/hilscher_nxhx10.cfg b/openocd-0.10.0/scripts/board/hilscher_nxhx10.cfg
deleted file mode 100644
index 4ef2f3b967a20afdb8bf52885ff883eb8eee9997..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/hilscher_nxhx10.cfg
+++ /dev/null
@@ -1,82 +0,0 @@
-################################################################################
-# Author: Michael Trensch (MTrensch@googlemail.com)
-################################################################################
-
-source [find target/hilscher_netx10.cfg]
-
-# Usually it is not needed to set srst_pulls_trst
-# but sometimes it does not work without it. If you encounter
-# problems try to line below
-# reset_config trst_and_srst srst_pulls_trst
-reset_config trst_and_srst
-adapter_nsrst_delay 500
-jtag_ntrst_delay 500
-
-$_TARGETNAME configure -work-area-virt 0x08000000 -work-area-phys 0x08000000 -work-area-size 0x4000 -work-area-backup 1
-
-# Par. Flash can only be accessed if DIP switch on the board is set in proper
-# position and init_sdrambus was called. Don't call these functions if the DIP
-# switch is in invalid position, as some outputs may collide. This is why this
-# function is not called automatically
-proc flash_init { } {
- puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
- mww 0x101C0100 0x01010008
-
- flash probe 0
-}
-
-proc mread32 {addr} {
- set value(0) 0
- mem2array value 32 $addr 1
- return $value(0)
-}
-
-proc init_clocks { } {
- puts "Enabling all clocks "
- set accesskey [mread32 0x101c0070]
- mww 0x101c0070 [expr $accesskey]
-
- mww 0x101c0028 0x00007511
-}
-
-proc init_sdrambus { } {
- puts "Initializing external SDRAM Bus 16 Bit "
- set accesskey [mread32 0x101c0070]
- mww 0x101c0070 [expr $accesskey]
- mww 0x101c0C40 0x00000050
-
- puts "Configuring SDRAM controller for K4S561632E (32MB) "
- mww 0x101C0140 0
- sleep 100
- #mww 0x101C0144 0x00a13262
- mww 0x101C0144 0x00a13251
- mww 0x101C0148 0x00000033
- mww 0x101C0140 0x030d0121
-}
-
-$_TARGETNAME configure -event reset-init {
- halt
- wait_halt 1000
-
- arm7_9 fast_memory_access enable
- arm7_9 dcc_downloads enable
-
- init_clocks
-# init_sdrambus
-
- puts ""
- puts "-------------------------------------------------"
- puts "Call 'init_clocks' to enable all clocks"
- puts "Call 'init_sdrambus' to enable external SDRAM bus"
- puts "-------------------------------------------------"
-}
-
-#####################
-# Flash configuration
-#####################
-
-#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
-#flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
-
-init
-reset init
\ No newline at end of file
diff --git a/openocd-0.10.0/scripts/board/hilscher_nxhx50.cfg b/openocd-0.10.0/scripts/board/hilscher_nxhx50.cfg
deleted file mode 100644
index eebb165243dc7baa2aae7bd909c73b8d66128919..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/hilscher_nxhx50.cfg
+++ /dev/null
@@ -1,40 +0,0 @@
-################################################################################
-# Author: Michael Trensch (MTrensch@googlemail.com)
-################################################################################
-
-source [find target/hilscher_netx50.cfg]
-
-reset_config trst_and_srst
-adapter_nsrst_delay 500
-jtag_ntrst_delay 500
-
-$_TARGETNAME configure -work-area-virt 0x10000000 -work-area-phys 0x10000000 -work-area-size 0x4000 -work-area-backup 1
-
-$_TARGETNAME configure -event reset-init {
- halt
-
- arm7_9 fast_memory_access enable
- arm7_9 dcc_downloads enable
-
- sdram_fix
-
- puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
- mww 0x1C000140 0
- mww 0x1C000144 0x00A12151
- mww 0x1C000140 0x030D0001
-
- puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
- mww 0x1C000100 0x01010008
-
- flash probe 0
-}
-
-#####################
-# Flash configuration
-#####################
-
-#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
-flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
-
-init
-reset init
diff --git a/openocd-0.10.0/scripts/board/hilscher_nxhx500.cfg b/openocd-0.10.0/scripts/board/hilscher_nxhx500.cfg
deleted file mode 100644
index dd3a9514db01f855419446f313a7290b190d4cfe..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/hilscher_nxhx500.cfg
+++ /dev/null
@@ -1,42 +0,0 @@
-################################################################################
-# Author: Michael Trensch (MTrensch@googlemail.com)
-################################################################################
-
-source [find target/hilscher_netx500.cfg]
-
-reset_config trst_and_srst
-adapter_nsrst_delay 500
-jtag_ntrst_delay 500
-
-$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
-
-$_TARGETNAME configure -event reset-init {
- halt
-
- arm7_9 fast_memory_access enable
- arm7_9 dcc_downloads enable
-
- sleep 100
-
- sdram_fix
-
- puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
- mww 0x00100140 0
- mww 0x00100144 0x03C23251
- mww 0x00100140 0x030D0001
-
- puts "Configuring SRAM nCS0 for 90ns Par. Flash (x16)"
- mww 0x00100100 0x01010008
-
- flash probe 0
-}
-
-#####################
-# Flash configuration
-#####################
-
-#flash bank <name> <driver> <base> <size> <chip width> <bus width> <target#>
-flash bank parflash cfi 0xC0000000 0x01000000 2 2 $_TARGETNAME
-
-init
-reset init
diff --git a/openocd-0.10.0/scripts/board/hilscher_nxsb100.cfg b/openocd-0.10.0/scripts/board/hilscher_nxsb100.cfg
deleted file mode 100644
index efb091b101df046b531fad966d6a6bb368a7331a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/hilscher_nxsb100.cfg
+++ /dev/null
@@ -1,29 +0,0 @@
-################################################################################
-# Author: Michael Trensch (MTrensch@googlemail.com)
-################################################################################
-
-source [find target/hilscher_netx500.cfg]
-
-reset_config trst_and_srst
-adapter_nsrst_delay 500
-jtag_ntrst_delay 500
-
-$_TARGETNAME configure -work-area-virt 0x1000 -work-area-phys 0x1000 -work-area-size 0x4000 -work-area-backup 1
-
-$_TARGETNAME configure -event reset-init {
- halt
-
- arm7_9 fast_memory_access enable
- arm7_9 dcc_downloads enable
-
- sdram_fix
-
- puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
- mww 0x00100140 0
- mww 0x00100144 0x03C23251
- mww 0x00100140 0x030D0001
-
-}
-
-init
-reset init
diff --git a/openocd-0.10.0/scripts/board/hitex_lpc1768stick.cfg b/openocd-0.10.0/scripts/board/hitex_lpc1768stick.cfg
deleted file mode 100644
index 161e9654a4cc8f01f8ba3039d9ae2572a7eee70d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/hitex_lpc1768stick.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-# Hitex LPC1768 Stick
-#
-# http://www.hitex.com/?id=1602
-#
-
-reset_config trst_and_srst
-
-source [find interface/ftdi/hitex_lpc1768stick.cfg]
-
-source [find target/lpc17xx.cfg]
-
-
-# startup @ 500kHz
-adapter_khz 500
-
diff --git a/openocd-0.10.0/scripts/board/hitex_lpc2929.cfg b/openocd-0.10.0/scripts/board/hitex_lpc2929.cfg
deleted file mode 100644
index d2515371df806f4c6cfc6f550aa8dc11eb0820eb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/hitex_lpc2929.cfg
+++ /dev/null
@@ -1,106 +0,0 @@
-# Hitex eval board for LPC2929/LPC2939
-# http://www.hitex.com/
-
-# Delays on reset lines
-adapter_nsrst_delay 50
-jtag_ntrst_delay 1
-
-# Maximum of 1/8 of clock frequency (XTAL = 16 MHz).
-# Adaptive clocking through RTCK is not supported.
-adapter_khz 2000
-
-# Target device: LPC29xx with ETB
-# The following variables are used by the LPC2900 script:
-# HAS_ETB Must be set to 1. The CPU on this board has ETB.
-# FLASH_CLOCK CPU frequency at the time of flash programming (in kHz)
-set HAS_ETB 1
-set FLASH_CLOCK 112000
-source [find target/lpc2900.cfg]
-
-# A working area will help speeding the flash programming
-#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000 -work-area-backup 0
-$_TARGETNAME configure -work-area-phys 0x58000000 -work-area-size 0x10000 -work-area-backup 0
-
-# Event handlers
-$_TARGETNAME configure -event reset-start {
- # Back to the slow JTAG clock
- adapter_khz 2000
-}
-
-# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
-set _FLASHNAME $_CHIPNAME.extflash
-flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
-
-
-$_TARGETNAME configure -event reset-init {
- # Flash
- mww 0x20200010 0x00000007 ;# FBWST: 7 wait states, not chached
-
- # Use PLL
- mww 0xFFFF8020 0x00000001 ;# XTAL_OSC_CONTROL: enable, 1-20 MHz
- mww 0xFFFF8070 0x01000000 ;# SYS_CLK_CONF: Crystal
- mww 0xFFFF8028 0x00000005 ;# PLL: (power down)
- mww 0xFFFF8028 0x01060004 ;# PLL: M=7, 2P=2 (power up)
- # --> f=112 MHz, fcco=224 MHz
- sleep 100
- mww 0xFFFF8070 0x02000000 ;# SYS_CLK_CONF: PLL
-
- # Increase JTAG speed
- adapter_khz 6000
-
- # Enable external memory bus (16-bit SRAM at CS6, 16-bit flash at CS7)
- mww 0xE0001138 0x0000001F ;# P1.14 = D0
- mww 0xE000113C 0x0000001F ;# P1.15 = D1
- mww 0xE0001140 0x0000001F ;# P1.16 = D2
- mww 0xE0001144 0x0000001F ;# P1.17 = D3
- mww 0xE0001148 0x0000001F ;# P1.18 = D4
- mww 0xE000114C 0x0000001F ;# P1.19 = D5
- mww 0xE0001150 0x0000001F ;# P1.20 = D6
- mww 0xE0001154 0x0000001F ;# P1.21 = D7
- mww 0xE0001200 0x0000001F ;# P2.0 = D8
- mww 0xE0001204 0x0000001F ;# P2.1 = D9
- mww 0xE0001208 0x0000001F ;# P2.2 = D10
- mww 0xE000120C 0x0000001F ;# P2.3 = D11
- mww 0xE0001210 0x0000001F ;# P2.4 = D12
- mww 0xE0001214 0x0000001F ;# P2.5 = D13
- mww 0xE0001218 0x0000001F ;# P2.6 = D14
- mww 0xE000121C 0x0000001F ;# P2.7 = D15
- mww 0xE0001104 0x00000007 ;# P1.1 = A1
- mww 0xE0001108 0x00000007 ;# P1.2 = A2
- mww 0xE000110C 0x00000007 ;# P1.3 = A3
- mww 0xE0001110 0x00000007 ;# P1.4 = A4
- mww 0xE0001114 0x00000007 ;# P1.5 = A5
- mww 0xE0001118 0x00000007 ;# P1.6 = A6
- mww 0xE000111C 0x00000007 ;# P1.7 = A7
- mww 0xE0001028 0x00000007 ;# P0.10 = A8
- mww 0xE000102C 0x00000007 ;# P0.11 = A9
- mww 0xE0001030 0x00000007 ;# P0.12 = A10
- mww 0xE0001034 0x00000007 ;# P0.13 = A11
- mww 0xE0001038 0x00000007 ;# P0.14 = A12
- mww 0xE000103C 0x00000007 ;# P0.15 = A13
- mww 0xE0001048 0x00000007 ;# P0.18 = A14
- mww 0xE000104C 0x00000007 ;# P0.19 = A15
- mww 0xE0001050 0x00000007 ;# P0.20 = A16
- mww 0xE0001054 0x00000007 ;# P0.21 = A17
- mww 0xE0001058 0x00000007 ;# P0.22 = A18
- mww 0xE000105C 0x00000007 ;# P0.23 = A19
- mww 0xE0001238 0x00000007 ;# P2.14 = BLS0
- mww 0xE000123C 0x00000007 ;# P2.15 = BLS1
- mww 0xE0001300 0x00000007 ;# P3.0 = CS6
- mww 0xE0001304 0x00000007 ;# P3.1 = CS7
- mww 0xE0001130 0x00000007 ;# P1.12 = OE_N
- mww 0xE0001134 0x00000007 ;# P1.13 = WE_N
- mww 0x600000BC 0x00000041 ;# Bank6 16-bit mode, RBLE=1
- mww 0x600000B4 0x00000000 ;# Bank6 WSTOEN=0
- mww 0x600000AC 0x00000005 ;# Bank6 WST1=5
- mww 0x600000B8 0x00000001 ;# Bank6 WSTWEN=1
- mww 0x600000B0 0x00000006 ;# Bank6 WST2=6
- mww 0x600000A8 0x00000002 ;# Bank6 IDCY=2
- mww 0x600000D8 0x00000041 ;# Bank7 16-bit mode, RBLE=1
- mww 0x600000D0 0x00000000 ;# Bank7 WSTOEN=0
- mww 0x600000C8 0x0000000A ;# Bank7 WST1=10
- mww 0x600000D4 0x00000001 ;# Bank7 WSTWEN=1
- mww 0x600000CC 0x0000000C ;# Bank7 WST2=8
- mww 0x600000C4 0x00000002 ;# Bank7 IDCY=2
-}
-
diff --git a/openocd-0.10.0/scripts/board/hitex_stm32-performancestick.cfg b/openocd-0.10.0/scripts/board/hitex_stm32-performancestick.cfg
deleted file mode 100644
index 82fb169619ed33a0b7771efccde76a948987f2fd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/hitex_stm32-performancestick.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-# Hitex stm32 performance stick
-
-reset_config trst_and_srst
-
-source [find interface/ftdi/stm32-stick.cfg]
-
-set CHIPNAME stm32_hitex
-source [find target/stm32f1x.cfg]
-
-# configure str750 connected to jtag chain
-# FIXME -- source [find target/str750.cfg] after cleaning that up
-jtag newtap str750 cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id 0x4f1f0041
-
-# for some reason this board like to startup @ 500kHz
-adapter_khz 500
-
diff --git a/openocd-0.10.0/scripts/board/hitex_str9-comstick.cfg b/openocd-0.10.0/scripts/board/hitex_str9-comstick.cfg
deleted file mode 100644
index be153314fa59438d0c2205ce6fd9c75a21be1d7a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/hitex_str9-comstick.cfg
+++ /dev/null
@@ -1,79 +0,0 @@
-# Hitex STR9-comStick
-# http://www.hitex.com/index.php?id=383
-# This works for the STR9-comStick revisions STR912CS-A1 and STR912CS-A2.
-
-source [find interface/ftdi/hitex_str9-comstick.cfg]
-
-# set jtag speed
-adapter_khz 3000
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-
-#
-# FIXME use the standard str912 target config; that script might need
-# updating to "-ignore-version" for the boundary scan TAP
-#
-# source [find target/str912.cfg]
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str912
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists FLASHTAPID] } {
- set _FLASHTAPID $FLASHTAPID
-} else {
- set _FLASHTAPID 0x04570041
-}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x25966041
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID] } {
- set _BSTAPID $BSTAPID
-} else {
- # Found on STR9-comStick, revision STR912CS-A1
- set _BSTAPID1 0x1457f041
- # Found on STR9-comStick, revision STR912CS-A2
- set _BSTAPID2 0x2457f041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -event reset-init {
- # We can increase speed now that we know the target is halted.
- #jtag_rclk 3000
-
- # -- Enable 96K RAM
- # PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
-
- str9x flash_config 0 4 2 0 0x80000
- flash protect 0 0 7 off
-}
-
-$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-set _FLASHNAME $_CHIPNAME.flash0
-flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
diff --git a/openocd-0.10.0/scripts/board/iar_lpc1768.cfg b/openocd-0.10.0/scripts/board/iar_lpc1768.cfg
deleted file mode 100644
index d8c8c2d7158a18e51f00cd793a80111399fc6b77..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/iar_lpc1768.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-# Board from IAR KickStart Kit for LPC1768
-# See www.iar.com and also
-# http://www.olimex.com/dev/lpc-1766stk.html
-#
-
-source [find target/lpc17xx.cfg]
-
-# The chip has just been reset.
-#
-$_TARGETNAME configure -event reset-init {
- # FIXME update the core clock to run at 100 MHz;
- # and update JTAG clocking similarly; then
- # make CCLK match,
-
- flash probe 0
-}
-
diff --git a/openocd-0.10.0/scripts/board/iar_str912_sk.cfg b/openocd-0.10.0/scripts/board/iar_str912_sk.cfg
deleted file mode 100644
index ba060a046bcedf26307a5d597d932afe1ca18569..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/iar_str912_sk.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-# The IAR str912-sk evaluation kick start board has an str912
-
-source [find target/str912.cfg]
\ No newline at end of file
diff --git a/openocd-0.10.0/scripts/board/icnova_imx53_sodimm.cfg b/openocd-0.10.0/scripts/board/icnova_imx53_sodimm.cfg
deleted file mode 100644
index aa6a148a0a9cd059f9716b17f4cab8cc9798d1bd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/icnova_imx53_sodimm.cfg
+++ /dev/null
@@ -1,448 +0,0 @@
-#################################################################################################
-# Author: Benjamin Tietz <benjamin.tietz@in-circuit.de> ;#
-# based on work from: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> ;#
-# Kiwigrid GmbH ;#
-# Generated for In-Circuit i.MX53 SO-Dimm ;#
-#################################################################################################
-
-# The In-Circuit ICnova IMX53SODIMM board has a single IMX53 chip
-source [find target/imx53.cfg]
-# Helper for common memory read/modify/write procedures
-source [find mem_helper.tcl]
-
-echo "i.MX53 SO-Dimm board lodaded."
-
-# Set reset type
-#reset_config srst_only
-
-adapter_khz 3000
-
-# Slow speed to be sure it will work
-jtag_rclk 1000
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
-
-$_TARGETNAME configure -event "reset-assert" {
- echo "Reseting ...."
- #cortex_a dbginit
-}
-
-$_TARGETNAME configure -event reset-init { sodimm_init }
-
-global AIPS1_BASE_ADDR
-set AIPS1_BASE_ADDR 0x53F00000
-global AIPS2_BASE_ADDR
-set AIPS2_BASE_ADDR 0x63F00000
-
-proc sodimm_init { } {
- echo "Reset-init..."
- ; # halt the CPU
- halt
-
- echo "HW version [format %x [mrw 0x48]]"
-
- dap apsel 1
- DCD
-
- ; # ARM errata ID #468414
- set tR [arm mrc 15 0 1 0 1]
- arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit
-
- init_l2cc
- init_aips
- init_clock
-
- dap apsel 0
-
- ; # Force ARM state
- ; #reg cpsr 0x000001D3
- arm core_state arm
-
- jtag_rclk 3000
-# adapter_khz 3000
-}
-
-
-# L2CC Cache setup/invalidation/disable
-proc init_l2cc { } {
- ; #/* explicitly disable L2 cache */
- ; #mrc 15, 0, r0, c1, c0, 1
- set tR [arm mrc 15 0 1 0 1]
- ; #bic r0, r0, #0x2
- ; #mcr 15, 0, r0, c1, c0, 1
- arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
-
- ; #/* reconfigure L2 cache aux control reg */
- ; #mov r0, #0xC0 /* tag RAM */
- ; #add r0, r0, #0x4 /* data RAM */
- ; #orr r0, r0, #(1 << 24) /* disable write allocate delay */
- ; #orr r0, r0, #(1 << 23) /* disable write allocate combine */
- ; #orr r0, r0, #(1 << 22) /* disable write allocate */
-
- ; #mcr 15, 1, r0, c9, c0, 2
- arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<22)]
-}
-
-
-# AIPS setup - Only setup MPROTx registers.
-# The PACR default values are good.
-proc init_aips { } {
- ; # Set all MPROTx to be non-bufferable, trusted for R/W,
- ; # not forced to user-mode.
- global AIPS1_BASE_ADDR
- global AIPS2_BASE_ADDR
- set VAL 0x77777777
-
-# dap apsel 1
- mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
- mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
- mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
- mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
-# dap apsel 0
-}
-
-
-proc init_clock { } {
- global AIPS1_BASE_ADDR
- global AIPS2_BASE_ADDR
- set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000]
- set CLKCTL_CCSR 0x0C
- set CLKCTL_CBCDR 0x14
- set CLKCTL_CBCMR 0x18
- set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000]
- set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000]
- set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000]
- set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000]
- set CLKCTL_CSCMR1 0x1C
- set CLKCTL_CDHIPR 0x48
- set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000]
- set CLKCTL_CSCDR1 0x24
- set CLKCTL_CCDR 0x04
-
- ; # Switch ARM to step clock
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
-
- return
- echo "not returned"
- setup_pll $PLL1_BASE_ADDR 800
- setup_pll $PLL3_BASE_ADDR 400
-
- ; # Switch peripheral to PLL3
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
- while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
-
- setup_pll $PLL2_BASE_ADDR 400
-
- ; # Switch peripheral to PLL2
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
-
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
-
- ; # change uart clk parent to pll2
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
-
- ; # make sure change is effective
- while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
-
- setup_pll $PLL3_BASE_ADDR 216
-
- setup_pll $PLL4_BASE_ADDR 455
-
- ; # Set the platform clock dividers
- mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
-
- mww [expr $CCM_BASE_ADDR + 0x10] 0
-
- ; # Switch ARM back to PLL 1.
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
-
- ; # make uart div=6
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
-
- ; # Restore the default values in the Gate registers
- mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
-
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
-
- ; # for cko - for ARM div by 8
- mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
-}
-
-
-proc setup_pll { PLL_ADDR CLK } {
- set PLL_DP_CTL 0x00
- set PLL_DP_CONFIG 0x04
- set PLL_DP_OP 0x08
- set PLL_DP_HFS_OP 0x1C
- set PLL_DP_MFD 0x0C
- set PLL_DP_HFS_MFD 0x20
- set PLL_DP_MFN 0x10
- set PLL_DP_HFS_MFN 0x24
-
- if {$CLK == 1000} {
- set DP_OP [expr (10 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (12 - 1)]
- set DP_MFN 5
- } elseif {$CLK == 850} {
- set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (48 - 1)]
- set DP_MFN 41
- } elseif {$CLK == 800} {
- set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (3 - 1)]
- set DP_MFN 1
- } elseif {$CLK == 700} {
- set DP_OP [expr (7 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (24 - 1)]
- set DP_MFN 7
- } elseif {$CLK == 600} {
- set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (4 - 1)]
- set DP_MFN 1
- } elseif {$CLK == 665} {
- set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (96 - 1)]
- set DP_MFN 89
- } elseif {$CLK == 532} {
- set DP_OP [expr (5 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (24 - 1)]
- set DP_MFN 13
- } elseif {$CLK == 455} {
- set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
- set DP_MFD [expr (48 - 1)]
- set DP_MFN 71
- } elseif {$CLK == 400} {
- set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
- set DP_MFD [expr (3 - 1)]
- set DP_MFN 1
- } elseif {$CLK == 216} {
- set DP_OP [expr (6 << 4) + ((3 - 1) << 0)]
- set DP_MFD [expr (4 - 1)]
- set DP_MFN 3
- } else {
- error "Error (setup_dll): clock not found!"
- }
-
- mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
- mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
-
- mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
-
- mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
-
- mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
-
- mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
- while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
-}
-
-
-proc CPU_2_BE_32 { L } {
- return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)]
-}
-
-
-# Device Configuration Data
-proc DCD { } {
-# dap apsel 1
-#*========================================================================================== ======
-# Initialization script for 32 bit DDR3 (CS0+CS1)
-#*========================================================================================== ======
-# Remux D24/D25 to perform Flash-access
- mww 0x53fa818C 0x00000000 ; #EIM_RW
- mww 0x53fa8180 0x00000000 ; #EIM_CS0
- mww 0x53fa8188 0x00000000 ; #EIM_OE
- mww 0x53fa817C 0x00000000 ; #A16
- mww 0x53fa8178 0x00000000 ; #A17
- mww 0x53fa8174 0x00000000 ; #A18
- mww 0x53fa8170 0x00000000 ; #A19
- mww 0x53fa816C 0x00000000 ; #A20
- mww 0x53fa8168 0x00000000 ; #A21
- mww 0x53fa819C 0x00000000 ; #DA0
- mww 0x53fa81A0 0x00000000 ; #DA1
- mww 0x53fa81A4 0x00000000 ; #DA2
- mww 0x53fa81A8 0x00000000 ; #DA3
- mww 0x53fa81AC 0x00000000 ; #DA4
- mww 0x53fa81B0 0x00000000 ; #DA5
- mww 0x53fa81B4 0x00000000 ; #DA6
- mww 0x53fa81B8 0x00000000 ; #DA7
- mww 0x53fa81BC 0x00000000 ; #DA8
- mww 0x53fa81C0 0x00000000 ; #DA9
- mww 0x53fa81C4 0x00000000 ; #DA10
- mww 0x53fa81C8 0x00000000 ; #DA11
- mww 0x53fa81CC 0x00000000 ; #DA12
- mww 0x53fa81D0 0x00000000 ; #DA13
- mww 0x53fa81D4 0x00000000 ; #DA14
- mww 0x53fa81D8 0x00000000 ; #DA15
- mww 0x53fa8118 0x00000000 ; #D16
- mww 0x53fa811C 0x00000000 ; #D17
- mww 0x53fa8120 0x00000000 ; #D18
- mww 0x53fa8124 0x00000000 ; #D19
- mww 0x53fa8128 0x00000000 ; #D20
- mww 0x53fa812C 0x00000000 ; #D21
- mww 0x53fa8130 0x00000000 ; #D22
- mww 0x53fa8134 0x00000000 ; #D23
- mww 0x53fa813c 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D24
- mww 0x53fa8140 0x00000000 ; #IOMUXC_SW_PAD_CTL_PAD_EIM_D25
- mww 0x53fa8144 0x00000000 ; #D26
- mww 0x53fa8148 0x00000000 ; #D27
- mww 0x53fa814C 0x00000000 ; #D28
- mww 0x53fa8150 0x00000000 ; #D29
- mww 0x53fa8154 0x00000000 ; #D30
- mww 0x53fa8158 0x00000000 ; #D31
-
-# DDR3 IOMUX configuration
-#* Global pad control options */
- mww 0x53fa8554 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
- mww 0x53fa8558 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
- mww 0x53fa8560 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
- mww 0x53fa8564 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
- mww 0x53fa8568 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
- mww 0x53fa8570 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - boazp: weaker sdclk EVK DDR max frequency
- mww 0x53fa8574 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
- mww 0x53fa8578 0x00200000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - boazp: weaker sdclk EVK DDR max frequency
- mww 0x53fa857c 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
- mww 0x53fa8580 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
- mww 0x53fa8584 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
- mww 0x53fa8588 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
- mww 0x53fa8590 0x00380040 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
- mww 0x53fa8594 0x00380000 ; #IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
- mww 0x53fa86f0 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_ADDDS
- mww 0x53fa86f4 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
- mww 0x53fa86fc 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRPKE
-# mww 0x53fa8714 0x00000200 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
- mww 0x53fa8714 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode XXX
- mww 0x53fa8718 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B0DS
- mww 0x53fa871c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B1DS
- mww 0x53fa8720 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_CTLDS
- mww 0x53fa8724 0x00000000 ; #IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=0 XXX
- mww 0x53fa8728 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B2DS
- mww 0x53fa872c 0x00380000 ; #IOMUXC_SW_PAD_CTL_GRP_B3DS
-# mww 0x53fa86f4 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL for sDQS[3:0], 1=DDR2, 0=CMOS mode
-# mww 0x53fa8714 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE for D[31:0], 1=DDR2, 0=CMOS mode
-# mww 0x53fa86fc 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRPKE
-# mww 0x53fa8724 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL=00
-
-#* Data bus byte lane pad drive strength control options */
-# mww 0x53fa872c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B3DS
-# mww 0x53fa8554 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
-# mww 0x53fa8558 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
-# mww 0x53fa8728 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B2DS
-# mww 0x53fa8560 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
-# mww 0x53fa8568 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
-# mww 0x53fa871c 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B1DS
-# mww 0x53fa8594 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
-# mww 0x53fa8590 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
-# mww 0x53fa8718 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_B0DS
-# mww 0x53fa8584 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
-# mww 0x53fa857c 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
-
-#* SDCLK pad drive strength control options */
-# mww 0x53fa8578 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
-# mww 0x53fa8570 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
-
-#* Control and addr bus pad drive strength control options */
-# mww 0x53fa8574 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
-# mww 0x53fa8588 0x00300000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
-# mww 0x53fa86f0 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_ADDDS for DDR addr bus
-# mww 0x53fa8720 0x00300000 ;IOMUXC_SW_PAD_CTL_GRP_CTLDS for CSD0, CSD1, SDCKE0, SDCKE1, SDWE
-
-# mww 0x53fa8564 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
-# mww 0x53fa8580 0x00300040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
-
-# Initialize DDR3 memory - Micron MT41J128M16-187Er
-#** Keep for now, same setting as CPU3 board **#
- mww 0x63fd901c 0x00008000
-# mww 0x63fd904c 0x01680172 ; #write leveling reg 0
-# mww 0x63fd9050 0x0021017f ; #write leveling reg 1
- mww 0x63fd9088 0x32383535 ; #read delay lines
- mww 0x63fd9090 0x40383538 ; #write delay lines
-# mww 0x63fd90F8 0x00000800 ; #Measure unit
- mww 0x63fd907c 0x0136014d ; #DQS gating 0
- mww 0x63fd9080 0x01510141 ; #DQS gating 1
-#* CPU3 Board settingr
-# Enable bank interleaving, Address mirror on, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
-# mww 0x63fd9018 0x00091740 ; #Misc register:
-#* Quick Silver board setting
-# Enable bank interleaving, Address mirror off, WALAT 0x1, RALAT = 0x5, DDR2_EN = 0
- mww 0x63fd9018 0x00011740 ; #Misc register
-
-# Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
-# mww 0x63fd9000 0xc3190000 ; #Main control register
-# Enable CSD0 and CSD1, row width = 14, column width = 10, burst length = 8, data width = 32bit
- mww 0x63fd9000 0x83190000 ; #Main control register
-# tRFC=64ck;tXS=68;tXP=3;tXPDLL=10;tFAW=15;CAS=6ck
- mww 0x63fd900C 0x555952E3 ; #timing configuration Reg 0
-# tRCD=6;tRP=6;tRC=21;tRAS=15;tRPA=1;tWR=6;tMRD=4;tCWL=5ck
- mww 0x63fd9010 0xb68e8b63 ; #timing configuration Reg 1
-# tDLLK(tXSRD)=512 cycles; tRTP=4;tWTR=4;tRRD=4
- mww 0x63fd9014 0x01ff00db ; #timing configuration Reg 2
- mww 0x63fd902c 0x000026d2 ; #command delay (default)
- mww 0x63fd9030 0x009f0e21 ; #out of reset delays
-# Keep tAOFPD, tAONPD, tANPD, and tAXPD as default since they are bigger than calc values
- mww 0x63fd9008 0x12273030 ; #ODT timings
-# tCKE=3; tCKSRX=5; tCKSRE=5
- mww 0x63fd9004 0x0002002d
-#Power down control
-#**********************************
-#DDR device configuration:
-#**********************************
-#**********************************
-# CS0:
-#**********************************
- mww 0x63fd901c 0x00008032 ; #write mode reg MR2 with cs0 (see below for settings)
-# Full array self refresh
-# Rtt_WR disabled (no ODT at IO CMOS operation)
-# Manual self refresh
-# CWS=5
- mww 0x63fd901c 0x00008033 ; #write mode reg MR3 with cs0.
- mww 0x63fd901c 0x00028031 ; #write mode reg MR1 with cs0. ODS=01: out buff= RZQ/7 (see below for settings)
-# out impedance = RZQ/7
-# Rtt_nom disabled (no ODT at IO CMOS operation)
-# Aditive latency off
-# write leveling disabled
-# tdqs (differential?) disabled
-
- mww 0x63fd901c 0x09208030 ; #write mode reg MR0 with cs0 , with dll_rst0
- mww 0x63fd901c 0x04008040 ; #ZQ calibration with cs0 (A10 high indicates ZQ cal long ZQCL)
-#**********************************
-# CS1:
-#**********************************
-# mww 0x63fd901c 0x0000803a ; #write mode reg MR2 with cs1.
-# mww 0x63fd901c 0x0000803b ; #write mode reg MR3 with cs1.
-# mww 0x63fd901c 0x00028039 ; #write mode reg MR1 with cs1. ODS=01: out buff= RZQ/7
-# mww 0x63fd901c 0x09208138 ; #write mode reg MR0 with cs1.
-# mww 0x63fd901c 0x04008048 ; #ZQ calibration with cs1(A10 high indicates ZQ cal long ZQCL)
-#**********************************
-
-
- mww 0x63fd9020 0x00001800 ; # Refresh control register
- mww 0x63fd9040 0x04b80003 ; # ZQ HW control
- mww 0x63fd9058 0x00022227 ; # ODT control register
-
- mww 0x63fd901c 0x00000000
-
-# CLKO muxing (comment out for now till needed to avoid conflicts with intended usage of signals)
-# mww 0x53FA8314 = 0
-# mww 0x53FA8320 0x4
-# mww 0x53FD4060 0x01e900f0
-
-# dap apsel 0
-}
-
-# IRAM
-$_TARGETNAME configure -work-area-phys 0xF8000000 -work-area-size 0x20000 -work-area-backup 1
-
-flash bank mx535_nor cfi 0xf0000000 0x800000 2 2 $_TARGETNAME
-
-# vim:filetype=tcl
diff --git a/openocd-0.10.0/scripts/board/icnova_sam9g45_sodimm.cfg b/openocd-0.10.0/scripts/board/icnova_sam9g45_sodimm.cfg
deleted file mode 100644
index 84dab3899fd1ac503712bded29bc5ffae0bf34eb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/icnova_sam9g45_sodimm.cfg
+++ /dev/null
@@ -1,278 +0,0 @@
-#################################################################################################
-# #
-# Author: Lars Poeschel (larsi@wh2.tu-dresden.de) #
-# Generated for In-Circuit ICnova SAM9G45 SODIMM #
-# http://www.ic-board.de/product_info.php?info=p214_ICnova-SAM9G45-SODIMM.html|ICnova #
-# #
-#################################################################################################
-
-# FIXME use some standard target config, maybe create one from this
-#
-# source [find target/...cfg]
-
-source [find target/at91sam9g45.cfg]
-
-# Set reset type.
-# reset_config trst_and_srst
-
-# adapter_nsrst_delay 200
-# jtag_ntrst_delay 200
-
-
-# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
-# AT91SAM9 family, the microcontroller is a lump on a log without initialization. Because this family has
-# some powerful features, we want to have a special function that handles "reset init". To do this we declare
-# an event handler where these special activities can take place.
-
-scan_chain
-$_TARGETNAME configure -event reset-init {at91sam9g45_init}
-
-# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
-# Slow-speed oscillator enabled at reset, so run jtag speed slow.
-$_TARGETNAME configure -event reset-start {at91sam9g45_start}
-
-
-# NandFlash configuration and definition
-# Future TBD
-# Flash configuration
-# flash bank cfi <base> <size> <chip width> <bus width> <target#>
-set _FLASHNAME $_CHIPNAME.flash
-# set _NANDNAME $_CHIPNAME.nand
-flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
-# nand device $_NANDNAME at91sam9 $_TARGETNAME 0x40000000 0xFFFFE800
-
-
-proc read_register {register} {
- set result ""
- mem2array result 32 $register 1
- return $result(0)
-}
-
-proc at91sam9g45_start { } {
-
- # Make sure that the the jtag is running slow, since there are a number of different ways the board
- # can be configured coming into this state that can cause communication problems with the jtag
- # adapter. Also since this call can be made following a "reset init" where fast memory accesses
- # are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
- # jtag speed without causing GDB keep alive problem.
-
- arm7_9 fast_memory_access disable
- # Slow-speed oscillator enabled at reset, so run jtag speed slow.
- adapter_khz 4
- # Make sure processor is halted, or error will result in following steps.
- halt
- wait_halt 10000
- # RSTC_MR : enable user reset.
- mww 0xfffffd08 0xa5000501
-}
-
-
-proc at91sam9g45_init { } {
-
- # At reset AT91SAM9G45 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires
- # a number of steps that must be carefully performed. The process outline below follows the
- # recommended procedure outlined in the AT91SAM9G45 technical manual.
- #
- # Several key and very important things to keep in mind:
- # The SDRAM parts used currently on the board are -75 grade parts. This
- # means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur. The processor
- # core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
-
- # Make sure processor is halted, or error will result in following steps.
- halt
- # RSTC_MR : enable user reset.
- mww 0xfffffd08 0xa5000501
- # WDT_MR : disable watchdog.
- mww 0xfffffd44 0x00008000
-
- # Enable the main 15.000 MHz oscillator in CKGR_MOR register.
- # Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
-
- mww 0xfffffc20 0x00004001
- while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
-
- # Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
- # Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
-
- #mww 0xfffffc28 0x202a3f01
- mww 0xfffffc28 0x20c73f03
- while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
-
- # Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
- # Wait for MCKRDY signal from PMC_SR to assert.
-
- #mww 0xfffffc30 0x00000101
- mww 0xfffffc30 0x00001301
- while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
-
- # Now change PMC_MCKR register to select PLLA.
- # Wait for MCKRDY signal from PMC_SR to assert.
-
- mww 0xfffffc30 0x00001302
- while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
-
- # Processor and master clocks are now operating and stable at maximum frequency possible:
- # -> MCLK = 132.096 MHz
- # -> PCLK = 396.288 MHz
-
- # Switch over to adaptive clocking.
-
- adapter_khz 6000
-
- # Enable faster DCC downloads.
-
- arm7_9 dcc_downloads enable
-
- # To be able to use external SDRAM, several peripheral configuration registers must
- # be modified. The first change is made to PIO_ASR to select peripheral functions
- # for D15 through D31. The second change is made to the PIO_PDR register to disable
- # this for D15 through D31.
-
-# mww 0xfffff870 0xffff0000
-# mww 0xfffff804 0xffff0000
-
- # The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
- # using CS1. Additionally we want CS3 assigned to NandFlash. Also VDDIO is connected physically on
- # the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
-
- # mww 0xffffef1c 0x000100a
-
- # The ICnova SAM9G45 SODIMM has built-in NandFlash. The exact physical timing characteristics
- # for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
- # four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
-
- # mww 0xffffec30 0x00020002
- # mww 0xffffec34 0x04040404
- # mww 0xffffec38 0x00070007
- # mww 0xffffec3c 0x00030003
-
- # Identify NandFlash bank 0. Disabled at the moment because a memory driver is not yet complete.
-
-# nand probe 0
-
- # SMC_SETUP0 : Setup SMC for NOR Flash
- mww 0xffffe800 0x0012000a
- # SMC_PULSE0
- mww 0xffffe804 0x3b38343b
- # SMC_CYCLE0
- mww 0xffffe808 0x003f003f
- # SMC_MODE0
- mww 0xffffe80c 0x00001000
- # Identify flash bank 0
- flash probe 0
-
- # Now setup SDRAM. This is tricky and configuration is very important for reliability! The current calculations
- # are based on 2 x Samsung K4T51083QG memory.
-
- # 0. Enable DDR2 Clock
- mww 0xfffffc00 0x4
- # 1. Program memory device type
- # 1.1 configure the DDR controller
- mww 0xffffe620 0x16
- # 1.2 program the DDR controller
- mww 0xffffe608 0x3d
-
- # 2. program memory device features
- # 2.1 assume timings for 7.5ns min clock period
- mww 0xffffe60c 0x21128226
- # 2.2 pSDDRC->HDDRSDRC2_T1PR
- mww 0xffffe610 0x02c8100e
- # 2.3 pSDDRC->HDDRSDRC2_T2PR
- mww 0xffffe614 0x01000702
- # 3. NOP
- mww 0xffffe600 0x1
- mww 0x70000000 0x1
- # 3.1 delay 200us
- sleep 1
- # jim tcl alternative: after ms
- # after 0.2
-
- # 4. NOP
- mww 0xffffe600 0x1
- mww 0x70000000 0x1
- # 4.1 delay 400ns
-
- # 5. set all bank precharge
- mww 0xffffe600 0x2
- mww 0x70000000 0x1
- # 5.1 delay 400ns
-
- # 6. set EMR operation (EMRS2)
- mww 0xffffe600 0x5
- mww 0x74000000 0x1
- # 6.1 delay 2 cycles
-
- # 7. set EMR operation (EMRS3)
- mww 0xffffe600 0x5
- mww 0x76000000 0x1
- # 7.1 delay 2 cycles
-
- # 8. set EMR operation (EMRS1)
- mww 0xffffe600 0x5
- mww 0x72000000 0x1
- # 8.1 delay 200 cycles (400Mhz -> 5 * 10^-7s)
- sleep 1
-
- # 9. Enable DLL Reset (set DLL bit)
- set CR [expr [read_register 0xffffe608] | 0x80]
- mww 0xffffe608 $CR
-
- # 10. mode register cycle to reset the DLL
- mww 0xffffe600 0x5
- mww 0x70000000 0x1
- # 10.1 delay 2 cycles
-
- # 11. set all bank precharge
- mww 0xffffe600 0x2
- mww 0x70000000 0x1
- # 11.1 delay 400 ns
-
- # 12. two auto-refresh (CBR) cycles are provided.
- mww 0xffffe600 0x4
- mww 0x70000000 0x1
- # 12.1 delay 10 cycles
- # 12.2 2nd cycle (schreiben des Mode Register sparen wir uns)
- mww 0x70000000 0x1
- # 12.3 delay 10 cycles
-
- # 13. disable DLL reset (clear DLL bit)
- set CR [expr [read_register 0xffffe608] & 0xffffff7f]
- mww 0xffffe608 $CR
-
- # 14. mode register set cycle
- mww 0xffffe600 0x3
- mww 0x70000000 0x1
-
- # 15. program OCD field (set OCD bits)
- set CR [expr [read_register 0xffffe608] | 0x7000]
- mww 0xffffe608 $CR
-
- # 16. (EMRS1)
- mww 0xffffe600 0x5
- mww 0x72000000 0x1
- # 16.1 delay 2 cycles
-
- # 17. disable OCD field (clear OCD bits)
- set CR [expr [read_register 0xffffe608] & 0xffff8fff]
- mww 0xffffe608 $CR
-
- # 18. (EMRS1)
- mww 0xffffe600 0x5
- mww 0x76000000 0x1
- # 18.1 delay 2 cycles
-
- # 19. normal mode command
- mww 0xffffe600 0x0
- mww 0x70000000 0x1
-
- # 20. perform write to any address
- #mww 0x70000000 0x1
-
- # 21. write refresh rate into the count field of the refresh rate register
- mww 0xffffe604 0x24b
- # 21.1 delay (500 * 6 cycles)
-
- arm7_9 fast_memory_access enable
-}
-
-
diff --git a/openocd-0.10.0/scripts/board/imx27ads.cfg b/openocd-0.10.0/scripts/board/imx27ads.cfg
deleted file mode 100644
index e705b1e1666d4990c1f75c86d6193cebb4e65483..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/imx27ads.cfg
+++ /dev/null
@@ -1,76 +0,0 @@
-# The IMX27 ADS eval board has a single IMX27 chip
-# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
-source [find target/imx27.cfg]
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { imx27ads_init }
-
-# The IMX27 ADS board has a NOR flash on CS0
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME
-
-proc imx27ads_init { } {
- # This setup puts RAM at 0xA0000000
-
- # reset the board correctly
- reset run
- reset halt
-
- mww 0x10000000 0x20040304
- mww 0x10020000 0x00000000
- mww 0x10000004 0xDFFBFCFB
- mww 0x10020004 0xFFFFFFFF
-
- sleep 100
-
- # ========================================
- # Configure DDR on CSD0 -- initial reset
- # ========================================
- mww 0xD8001010 0x00000008
-
- # ========================================
- # Configure PSRAM on CS5
- # ========================================
- mww 0xd8002050 0x0000dcf6
- mww 0xd8002054 0x444a4541
- mww 0xd8002058 0x44443302
-
- # ========================================
- # Configure16 bit NorFlash on CS0
- # ========================================
- mww 0xd8002000 0x0000CC03
- mww 0xd8002004 0xa0330D01
- mww 0xd8002008 0x00220800
-
- # ========================================
- # Configure CPLD on CS4
- # ========================================
- mww 0xd8002040 0x0000DCF6
- mww 0xd8002044 0x444A4541
- mww 0xd8002048 0x44443302
-
- # ========================================
- # Configure DDR on CSD0 -- wait 5000 cycle
- # ========================================
- mww 0x10027828 0x55555555
- mww 0x10027830 0x55555555
- mww 0x10027834 0x55555555
- mww 0x10027838 0x00005005
- mww 0x1002783C 0x15555555
-
- mww 0xD8001010 0x00000004
-
- mww 0xD8001004 0x00795729
-
- mww 0xD8001000 0x92200000
- mww 0xA0000F00 0x0
-
- mww 0xD8001000 0xA2200000
- mww 0xA0000F00 0x0
- mww 0xA0000F00 0x0
-
- mww 0xD8001000 0xB2200000
- mwb 0xA0000033 0xFF
- mwb 0xA1000000 0xAA
-
- mww 0xD8001000 0x82228085
-}
diff --git a/openocd-0.10.0/scripts/board/imx27lnst.cfg b/openocd-0.10.0/scripts/board/imx27lnst.cfg
deleted file mode 100644
index e0ed05794c4a5bd4203d9d92114355cf625e7a3f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/imx27lnst.cfg
+++ /dev/null
@@ -1,59 +0,0 @@
-# The Linuxstamp-mx27 is board has a single IMX27 chip
-# For further info see http://opencircuits.com/Linuxstamp_mx27#OpenOCD
-source [find target/imx27.cfg]
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { imx27lnst_init }
-
-proc imx27lnst_init { } {
- # This setup puts RAM at 0xA0000000
-
- # reset the board correctly
- adapter_khz 500
- reset run
- reset halt
-
- mww 0x10000000 0x20040304
- mww 0x10020000 0x00000000
- mww 0x10000004 0xDFFBFCFB
- mww 0x10020004 0xFFFFFFFF
-
- sleep 100
-
- # ========================================
- # Configure DDR on CSD0 -- initial reset
- # ========================================
- mww 0xD8001010 0x00000008
-
- sleep 100
-
- # ========================================
- # Configure DDR on CSD0 -- wait 5000 cycle
- # ========================================
- mww 0x10027828 0x55555555
- mww 0x10027830 0x55555555
- mww 0x10027834 0x55555555
- mww 0x10027838 0x00005005
- mww 0x1002783C 0x15555555
-
- mww 0xD8001010 0x00000004
-
- mww 0xD8001004 0x00795729
-
- #mww 0xD8001000 0x92200000
- mww 0xD8001000 0x91120000
- mww 0xA0000F00 0x0
-
- #mww 0xD8001000 0xA2200000
- mww 0xD8001000 0xA1120000
- mww 0xA0000F00 0x0
- mww 0xA0000F00 0x0
-
- #mww 0xD8001000 0xB2200000
- mww 0xD8001000 0xB1120000
- mwb 0xA0000033 0xFF
- mwb 0xA1000000 0xAA
-
- #mww 0xD8001000 0x82228085
- mww 0xD8001000 0x81128080
-
-}
diff --git a/openocd-0.10.0/scripts/board/imx28evk.cfg b/openocd-0.10.0/scripts/board/imx28evk.cfg
deleted file mode 100644
index a85c2ca6786980b9c67292110710ffeae286f6e5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/imx28evk.cfg
+++ /dev/null
@@ -1,168 +0,0 @@
-# The IMX28EVK eval board has a IMX28 chip
-# Tested on SCH-26241 Rev D board with Olimex ARM-USB-OCD
-# Date: 201-02-01
-# Authors: James Robinson & Fabio Estevam
-
-source [find target/imx28.cfg]
-$_TARGETNAME configure -event gdb-attach { imx28evk_init }
-$_TARGETNAME configure -event reset-init { imx28evk_init }
-
-proc imx28evk_init { } {
-
- halt
-
- #****************************
- # VDDD setting
- #****************************
- # set VDDD =1.55V =(0.8v + TRIG x 0.025v), TRIG=0x1e
- mww 0x80044010 0x0003F503
- mww 0x80044040 0x0002041E
-
- #****************************
- # CLOCK set up
- #****************************
- # Power up PLL0 HW_CLKCTRL_PLL0CTRL0
- mww 0x80040000 0x00020000
- # Set up fractional dividers for CPU and EMI - HW_CLKCTRL_FRAC0
- # EMI - first set DIV_EMI to div-by-2 before programming frac divider
- mww 0x800400F0 0x80000002
-
-
- # CPU: CPUFRAC=19 480*18/29=454.7MHz, EMI: EMIFRAC=22, (480/2)*18/22=196.4MHz
- mww 0x800401B0 0x92921613
- # Clear the bypass bits for CPU and EMI clocks in HW_CLKCTRL_CLKSEQ_CLR
- mww 0x800401D8 0x00040080
- # HCLK = 227MHz,HW_CLKCTRL_HBUS DIV =0x2
- mww 0x80040060 0x00000002
-
- #****************************
- # POWER up DCDD_VDDA (DDR2)
- #****************************
- # Now set the voltage level to 1.8V HW_POWER_VDDACTRL bits TRC=0xC
- mww 0x80044050 0x0000270C
-
- #****************************
- # DDR2 DCDD_VDDA
- #****************************
- # First set up pin muxing and drive strength
- # Ungate module clock and bring out of reset HW_PINCTRL_CTRL_CLR
- mww 0x80018008 0xC0000000
-
- #****************************
- # EMI PAD setting
- #****************************
- # Set up drive strength for EMI pins
- mww 0x80019B80 0x00030000
- #IOMUXC_SW_PAD_CTL_GRP_CTLDS
-
- # Set up pin muxing for EMI, HW_PINCTRL_MUXSEL10, 11, 12, 13
- mww 0x800181A8 0xFFFFFFFF
- mww 0x800181B8 0xFFFFFFFF
- mww 0x800181C8 0xFFFFFFFF
- mww 0x800181D8 0xFFFFFFFF
-
- #** Ungate EMI clock in CCM
- mww 0x800400F0 0x00000002
-
- #============================================================================
- # DDR Controller Registers
- #============================================================================
- # Manufacturer: Elpida
- # Device Part Number: EDE1116AEBG
- # Clock Freq.: 200MHz
- # Density: 1Gb
- # Chip Selects: 1
- # Number of Banks: 8
- # Row address: 13
- # Column address: 10
- #============================================================================
- mww 0x800E0000 0x00000000
- mww 0x800E0040 0x00000000
- mww 0x800E0054 0x00000000
- mww 0x800E0058 0x00000000
- mww 0x800E005C 0x00000000
- mww 0x800E0060 0x00000000
- mww 0x800E0064 0x00000000
- mww 0x800E0068 0x00010101
- mww 0x800E006C 0x01010101
- mww 0x800E0070 0x000f0f01
- mww 0x800E0074 0x0102020A
- mww 0x800E007C 0x00010101
- mww 0x800E0080 0x00000100
- mww 0x800E0084 0x00000100
- mww 0x800E0088 0x00000000
- mww 0x800E008C 0x00000002
- mww 0x800E0090 0x01010000
- mww 0x800E0094 0x07080403
- mww 0x800E0098 0x06005003
- mww 0x800E009C 0x0A0000C8
- mww 0x800E00A0 0x02009C40
- mww 0x800E00A4 0x0002030C
- mww 0x800E00A8 0x0036B009
- mww 0x800E00AC 0x031A0612
- mww 0x800E00B0 0x02030202
- mww 0x800E00B4 0x00C8001C
- mww 0x800E00C0 0x00011900
- mww 0x800E00C4 0xffff0303
- mww 0x800E00C8 0x00012100
- mww 0x800E00CC 0xffff0303
- mww 0x800E00D0 0x00012100
- mww 0x800E00D4 0xffff0303
- mww 0x800E00D8 0x00012100
- mww 0x800E00DC 0xffff0303
- mww 0x800E00E0 0x00000003
- mww 0x800E00E8 0x00000000
- mww 0x800E0108 0x00000612
- mww 0x800E010C 0x01000f02
- mww 0x800E0114 0x00000200
- mww 0x800E0118 0x00020007
- mww 0x800E011C 0xf4004a27
- mww 0x800E0120 0xf4004a27
- mww 0x800E012C 0x07400300
- mww 0x800E0130 0x07400300
- mww 0x800E013C 0x00000005
- mww 0x800E0140 0x00000000
- mww 0x800E0144 0x00000000
- mww 0x800E0148 0x01000000
- mww 0x800E014C 0x01020408
- mww 0x800E0150 0x08040201
- mww 0x800E0154 0x000f1133
- mww 0x800E015C 0x00001f04
- mww 0x800E0160 0x00001f04
- mww 0x800E016C 0x00001f04
- mww 0x800E0170 0x00001f04
- mww 0x800E0288 0x00010000
- mww 0x800E028C 0x00030404
- mww 0x800E0290 0x00000003
- mww 0x800E02AC 0x01010000
- mww 0x800E02B0 0x01000000
- mww 0x800E02B4 0x03030000
- mww 0x800E02B8 0x00010303
- mww 0x800E02BC 0x01020202
- mww 0x800E02C0 0x00000000
- mww 0x800E02C4 0x02030303
- mww 0x800E02C8 0x21002103
- mww 0x800E02CC 0x00061200
- mww 0x800E02D0 0x06120612
- mww 0x800E02D4 0x04420442
- # Mode register 0 for CS1 and CS0, ok to program CS1 even if not used
- mww 0x800E02D8 0x00000000
- # Mode register 0 for CS2 and CS3, not supported in this processor
- mww 0x800E02DC 0x00040004
- # Mode register 1 for CS1 and CS0, ok to program CS1 even if not used
- mww 0x800E02E0 0x00000000
- # Mode register 1 for CS2 and CS3, not supported in this processor
- mww 0x800E02E4 0x00000000
- # Mode register 2 for CS1 and CS0, ok to program CS1 even if not used
- mww 0x800E02E8 0x00000000
- # Mode register 2 for CS2 and CS3, not supported in this processor
- mww 0x800E02EC 0x00000000
- # Mode register 3 for CS1 and CS0, ok to program CS1 even if not used
- mww 0x800E02F0 0x00000000
- # Mode register 3 for CS2 and CS3, not supported in this processor
- mww 0x800E02F4 0xffffffff
-
- #** start controller **#
- mww 0x800E0040 0x00000001
- # bit[0]: start
-}
diff --git a/openocd-0.10.0/scripts/board/imx31pdk.cfg b/openocd-0.10.0/scripts/board/imx31pdk.cfg
deleted file mode 100644
index 502d4077430955983a244c08f224c83fe5d0a613..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/imx31pdk.cfg
+++ /dev/null
@@ -1,99 +0,0 @@
-# The IMX31PDK eval board has a single IMX31 chip
-source [find target/imx31.cfg]
-source [find target/imx.cfg]
-$_TARGETNAME configure -event reset-init { imx31pdk_init }
-
-proc self_test {} {
- echo "Running 100 iterations of test."
- dump_image /ram/test 0x80000000 0x40000
- for {set i 0} {$i < 100} {set i [expr $i+1]} {
- echo "Iteration $i"
- reset init
- mww 0x80000000 0x12345678 0x10000
- load_image /ram/test 0x80000000 bin
- verify_image /ram/test 0x80000000 bin
- }
-}
-
-
-# Slow fallback frequency
-# measure_clk indicates ca. 3-4MHz.
-jtag_rclk 1000
-
-proc imx31pdk_init { } {
-
- imx3x_reset
-
- # This setup puts RAM at 0x80000000
-
- mww 0x53FC0000 0x040
- mww 0x53F80000 0x074B0B7D
-
- # 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
- #mww 0x53F80004 0xFF871D50
- #mww 0x53F80010 0x00271C1B
-
- # Start 16 bit NorFlash Initialization on CS0
- mww 0xb8002000 0x0000CC03
- mww 0xb8002004 0xa0330D01
- mww 0xb8002008 0x00220800
-
- # Configure CPLD on CS4
- mww 0xb8002040 0x0000DCF6
- mww 0xb8002044 0x444A4541
- mww 0xb8002048 0x44443302
-
- # SDCLK
- mww 0x43FAC26C 0
-
- # CAS
- mww 0x43FAC270 0
-
- # RAS
- mww 0x43FAC274 0
-
- # CS2 (CSD0)
- mww 0x43FAC27C 0x1000
-
- # DQM3
- mww 0x43FAC284 0
-
- # DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
- mww 0x43FAC288 0
- mww 0x43FAC28C 0
- mww 0x43FAC290 0
- mww 0x43FAC294 0
- mww 0x43FAC298 0
- mww 0x43FAC29C 0
- mww 0x43FAC2A0 0
- mww 0x43FAC2A4 0
- mww 0x43FAC2A8 0
- mww 0x43FAC2AC 0
- mww 0x43FAC2B0 0
- mww 0x43FAC2B4 0
- mww 0x43FAC2B8 0
- mww 0x43FAC2BC 0
- mww 0x43FAC2C0 0
- mww 0x43FAC2C4 0
- mww 0x43FAC2C8 0
- mww 0x43FAC2CC 0
- mww 0x43FAC2D0 0
- mww 0x43FAC2D4 0
- mww 0x43FAC2D8 0
- mww 0x43FAC2DC 0
-
- # Initialization script for 32 bit DDR on MX31 ADS
- mww 0xB8001010 0x00000004
- mww 0xB8001004 0x006ac73a
- mww 0xB8001000 0x92100000
- mww 0x80000f00 0x12344321
- mww 0xB8001000 0xa2100000
- mww 0x80000000 0x12344321
- mww 0x80000000 0x12344321
- mww 0xB8001000 0xb2100000
- mwb 0x80000033 0xda
- mwb 0x81000000 0xff
- mww 0xB8001000 0x82226080
- mww 0x80000000 0xDEADBEEF
- mww 0xB8001010 0x0000000c
-}
diff --git a/openocd-0.10.0/scripts/board/imx35pdk.cfg b/openocd-0.10.0/scripts/board/imx35pdk.cfg
deleted file mode 100644
index b5aa752fa248ec86bd30f9a56a5a785bb2d428fd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/imx35pdk.cfg
+++ /dev/null
@@ -1,252 +0,0 @@
-# The IMX35PDK eval board has a single IMX35 chip
-source [find target/imx35.cfg]
-source [find target/imx.cfg]
-$_TARGETNAME configure -event reset-init { imx35pdk_init }
-
-# Stick to *really* low clock rate or reset will fail
-# without RTCK / RCLK
-jtag_rclk 10
-
-proc imx35pdk_init { } {
-
- imx3x_reset
-
- mww 0x43f00040 0x00000000
- mww 0x43f00044 0x00000000
- mww 0x43f00048 0x00000000
- mww 0x43f0004C 0x00000000
- mww 0x43f00050 0x00000000
- mww 0x43f00000 0x77777777
- mww 0x43f00004 0x77777777
- mww 0x53f00040 0x00000000
- mww 0x53f00044 0x00000000
- mww 0x53f00048 0x00000000
- mww 0x53f0004C 0x00000000
- mww 0x53f00050 0x00000000
- mww 0x53f00000 0x77777777
- mww 0x53f00004 0x77777777
-
- # clock setup
- mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP
- mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.
-
- #=================================================
- # WEIM config
- #=================================================
- # CS0U
- mww 0xB8002000 0x0000CC03
- # CS0L
- mww 0xB8002004 0xA0330D01
- # CS0A
- mww 0xB8002008 0x00220800
- # CS5U
- mww 0xB8002050 0x0000dcf6
- # CS5L
- mww 0xB8002054 0x444a4541
- # CS5A
- mww 0xB8002058 0x44443302
-
- # IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
- mww 0x43FAC368 0x00000006
- mww 0x43FAC36C 0x00000006
- mww 0x43FAC370 0x00000006
- mww 0x43FAC374 0x00000006
- mww 0x43FAC378 0x00000006
- mww 0x43FAC37C 0x00000006
- mww 0x43FAC380 0x00000006
- mww 0x43FAC384 0x00000006
- mww 0x43FAC388 0x00000006
- mww 0x43FAC38C 0x00000006
- mww 0x43FAC390 0x00000006
- mww 0x43FAC394 0x00000006
- mww 0x43FAC398 0x00000006
- mww 0x43FAC39C 0x00000006
- mww 0x43FAC3A0 0x00000006
- mww 0x43FAC3A4 0x00000006
- mww 0x43FAC3A8 0x00000006
- mww 0x43FAC3AC 0x00000006
- mww 0x43FAC3B0 0x00000006
- mww 0x43FAC3B4 0x00000006
- mww 0x43FAC3B8 0x00000006
- mww 0x43FAC3BC 0x00000006
- mww 0x43FAC3C0 0x00000006
- mww 0x43FAC3C4 0x00000006
- mww 0x43FAC3C8 0x00000006
- mww 0x43FAC3CC 0x00000006
- mww 0x43FAC3D0 0x00000006
- mww 0x43FAC3D4 0x00000006
- mww 0x43FAC3D8 0x00000006
-
- # DDR data bus SD 0 through 31
- mww 0x43FAC3DC 0x00000082
- mww 0x43FAC3E0 0x00000082
- mww 0x43FAC3E4 0x00000082
- mww 0x43FAC3E8 0x00000082
- mww 0x43FAC3EC 0x00000082
- mww 0x43FAC3F0 0x00000082
- mww 0x43FAC3F4 0x00000082
- mww 0x43FAC3F8 0x00000082
- mww 0x43FAC3FC 0x00000082
- mww 0x43FAC400 0x00000082
- mww 0x43FAC404 0x00000082
- mww 0x43FAC408 0x00000082
- mww 0x43FAC40C 0x00000082
- mww 0x43FAC410 0x00000082
- mww 0x43FAC414 0x00000082
- mww 0x43FAC418 0x00000082
- mww 0x43FAC41c 0x00000082
- mww 0x43FAC420 0x00000082
- mww 0x43FAC424 0x00000082
- mww 0x43FAC428 0x00000082
- mww 0x43FAC42c 0x00000082
- mww 0x43FAC430 0x00000082
- mww 0x43FAC434 0x00000082
- mww 0x43FAC438 0x00000082
- mww 0x43FAC43c 0x00000082
- mww 0x43FAC440 0x00000082
- mww 0x43FAC444 0x00000082
- mww 0x43FAC448 0x00000082
- mww 0x43FAC44c 0x00000082
- mww 0x43FAC450 0x00000082
- mww 0x43FAC454 0x00000082
- mww 0x43FAC458 0x00000082
-
- # DQM setup
- mww 0x43FAC45c 0x00000082
- mww 0x43FAC460 0x00000082
- mww 0x43FAC464 0x00000082
- mww 0x43FAC468 0x00000082
-
- mww 0x43FAC46c 0x00000006
- mww 0x43FAC470 0x00000006
- mww 0x43FAC474 0x00000006
- mww 0x43FAC478 0x00000006
- mww 0x43FAC47c 0x00000006
- mww 0x43FAC480 0x00000006 ;# CSD0
- mww 0x43FAC484 0x00000006 ;# CSD1
- mww 0x43FAC488 0x00000006
- mww 0x43FAC48c 0x00000006
- mww 0x43FAC490 0x00000006
- mww 0x43FAC494 0x00000006
- mww 0x43FAC498 0x00000006
- mww 0x43FAC49c 0x00000006
- mww 0x43FAC4A0 0x00000006
- mww 0x43FAC4A4 0x00000006 ;# RAS
- mww 0x43FAC4A8 0x00000006 ;# CAS
- mww 0x43FAC4Ac 0x00000006 ;# SDWE
- mww 0x43FAC4B0 0x00000006 ;# SDCKE0
- mww 0x43FAC4B4 0x00000006 ;# SDCKE1
- mww 0x43FAC4B8 0x00000002 ;# SDCLK
-
- # SDQS0 through SDQS3
- mww 0x43FAC4Bc 0x00000082
- mww 0x43FAC4C0 0x00000082
- mww 0x43FAC4C4 0x00000082
- mww 0x43FAC4C8 0x00000082
-
-
- # *==================================================
- # Initialization script for 32 bit DDR2 on RINGO 3DS
- # *==================================================
-
- #--------------------------------------------
- # Init CCM
- #--------------------------------------------
- mww 0x53F80028 0x7D000028
-
- #--------------------------------------------
- # Init IOMUX for JTAG
- #--------------------------------------------
- mww 0x43FAC5EC 0x000000C3
- mww 0x43FAC5F0 0x000000C3
- mww 0x43FAC5F4 0x000000F3
- mww 0x43FAC5F8 0x000000F3
- mww 0x43FAC5FC 0x000000F3
- mww 0x43FAC600 0x000000F3
- mww 0x43FAC604 0x000000F3
-
-
- # ESD_MISC : enable DDR2
- mww 0xB8001010 0x00000304
-
- #--------------------------------------------
- # Init 32-bit DDR2 memeory on CSD0
- # COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
- #--------------------------------------------
-
- # ESD_ESDCFG0 : set timing paramters
- mww 0xB8001004 0x007ffC2f
-
- # ESD_ESDCTL0 : select Prechare-All mode
- mww 0xB8001000 0x92220000
- # DDR2 : Prechare-All
- mww 0x80000400 0x12345678
-
- # ESD_ESDCTL0 : select Load-Mode-Register mode
- mww 0xB8001000 0xB2220000
- # DDR2 : Load reg EMR2
- mwb 0x84000000 0xda
- # DDR2 : Load reg EMR3
- mwb 0x86000000 0xda
- # DDR2 : Load reg EMR1 -- enable DLL
- mwb 0x82000400 0xda
- # DDR2 : Load reg MR -- reset DLL
- mwb 0x80000333 0xda
-
- # ESD_ESDCTL0 : select Prechare-All mode
- mww 0xB8001000 0x92220000
- # DDR2 : Prechare-All
- mwb 0x80000400 0x12345678
-
- # ESD_ESDCTL0 : select Manual-Refresh mode
- mww 0xB8001000 0xA2220000
- # DDR2 : Manual-Refresh 2 times
- mww 0x80000000 0x87654321
- mww 0x80000000 0x87654321
-
- # ESD_ESDCTL0 : select Load-Mode-Register mode
- mww 0xB8001000 0xB2220000
- # DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
- mwb 0x80000233 0xda
- # DDR2 : Load reg EMR1 -- OCD default
- mwb 0x82000780 0xda
- # DDR2 : Load reg EMR1 -- OCD exit
- mwb 0x82000400 0xda ;# ODT disabled
-
- # ESD_ESDCTL0 : select normal-operation mode
- # DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
- # disable PWT & PRCT
- # disable Auto-Refresh
- mww 0xB8001000 0x82220080
-
- ## ESD_ESDCTL0 : enable Auto-Refresh
- mww 0xB8001000 0x82228080
- ## ESD_ESDCTL1 : enable Auto-Refresh
- mww 0xB8001008 0x00002000
-
-
- #***********************************************
- # Adjust the ESDCDLY5 register
- #***********************************************
- # Vary DQS_ABS_OFFSET5 for writes
- mww 0xB8001020 0x00F48000 ;# this is the default value
- mww 0xB8001024 0x00F48000 ;# this is the default value
- mww 0xB8001028 0x00F48000 ;# this is the default value
- mww 0xB800102c 0x00F48000 ;# this is the default value
-
-
- #Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
- mww 0xB8001010 0x00000384
- # wait a while
- sleep 1000
- # now clear the force measurement bit
- mww 0xB8001010 0x00000304
-
- # dummy write to DDR memory to set DQS low
- mww 0x80000000 0x00000000
-
- mww 0x30000100 0x0
- mww 0x30000104 0x31024
-
-
-}
diff --git a/openocd-0.10.0/scripts/board/imx53-m53evk.cfg b/openocd-0.10.0/scripts/board/imx53-m53evk.cfg
deleted file mode 100644
index eada27ab6baa7b62d135cce239da11154609736c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/imx53-m53evk.cfg
+++ /dev/null
@@ -1,318 +0,0 @@
-#######################################
-# DENX M53EVK #
-# http://www.denx-cs.de/?q=M53EVK #
-# Author: Marek Vasut <marex@denx.de> #
-# Based on imx53loco.cfg #
-#######################################
-
-# The DENX M53EVK has on-board JTAG adapter
-source [find interface/ftdi/m53evk.cfg]
-# The DENX M53EVK board has a single i.MX53 chip
-source [find target/imx53.cfg]
-# Helper for common memory read/modify/write procedures
-source [find mem_helper.tcl]
-
-echo "iMX53 M53EVK board lodaded."
-
-# Set reset type
-reset_config trst_and_srst separate trst_open_drain srst_open_drain
-
-# Run at 6 MHz
-adapter_khz 6000
-
-$_TARGETNAME configure -event "reset-assert" {
- echo "Reseting ...."
- #cortex_a dbginit
-}
-
-$_TARGETNAME configure -event reset-init { m53evk_init }
-
-global AIPS1_BASE_ADDR
-set AIPS1_BASE_ADDR 0x53F00000
-global AIPS2_BASE_ADDR
-set AIPS2_BASE_ADDR 0x63F00000
-
-proc m53evk_init { } {
- echo "Reset-init..."
- ; # halt the CPU
- halt
-
- echo "HW version [format %x [mrw 0x48]]"
-
- dap apsel 1
- DCD
-
- ; # ARM errata ID #468414
- set tR [arm mrc 15 0 1 0 1]
- arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit
-
- init_l2cc
- init_aips
- init_clock
-
- dap apsel 0
-
- ; # Force ARM state
- ; #reg cpsr 0x000001D3
- arm core_state arm
-}
-
-
-# L2CC Cache setup/invalidation/disable
-proc init_l2cc { } {
- ; #/* explicitly disable L2 cache */
- ; #mrc 15, 0, r0, c1, c0, 1
- set tR [arm mrc 15 0 1 0 1]
- ; #bic r0, r0, #0x2
- ; #mcr 15, 0, r0, c1, c0, 1
- arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
-
- ; #/* reconfigure L2 cache aux control reg */
- ; #mov r0, #0xC0 /* tag RAM */
- ; #add r0, r0, #0x4 /* data RAM */
- ; #orr r0, r0, #(1 << 24) /* disable write allocate delay */
- ; #orr r0, r0, #(1 << 23) /* disable write allocate combine */
- ; #orr r0, r0, #(1 << 22) /* disable write allocate */
-
- ; #mcr 15, 1, r0, c9, c0, 2
- arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<22)]
-}
-
-
-# AIPS setup - Only setup MPROTx registers.
-# The PACR default values are good.
-proc init_aips { } {
- ; # Set all MPROTx to be non-bufferable, trusted for R/W,
- ; # not forced to user-mode.
- global AIPS1_BASE_ADDR
- global AIPS2_BASE_ADDR
- set VAL 0x77777777
-
-# dap apsel 1
- mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
- mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
- mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
- mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
-# dap apsel 0
-}
-
-
-proc init_clock { } {
- global AIPS1_BASE_ADDR
- global AIPS2_BASE_ADDR
- set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000]
- set CLKCTL_CCSR 0x0C
- set CLKCTL_CBCDR 0x14
- set CLKCTL_CBCMR 0x18
- set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000]
- set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000]
- set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000]
- set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000]
- set CLKCTL_CSCMR1 0x1C
- set CLKCTL_CDHIPR 0x48
- set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000]
- set CLKCTL_CSCDR1 0x24
- set CLKCTL_CCDR 0x04
-
- ; # Switch ARM to step clock
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
-
- return
- echo "not returned"
- setup_pll $PLL1_BASE_ADDR 800
- setup_pll $PLL3_BASE_ADDR 400
-
- ; # Switch peripheral to PLL3
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
- while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
-
- setup_pll $PLL2_BASE_ADDR 400
-
- ; # Switch peripheral to PLL2
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
-
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
-
- ; # change uart clk parent to pll2
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
-
- ; # make sure change is effective
- while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
-
- setup_pll $PLL3_BASE_ADDR 216
-
- setup_pll $PLL4_BASE_ADDR 455
-
- ; # Set the platform clock dividers
- mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
-
- mww [expr $CCM_BASE_ADDR + 0x10] 0
-
- ; # Switch ARM back to PLL 1.
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
-
- ; # make uart div=6
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
-
- ; # Restore the default values in the Gate registers
- mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
-
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
-
- ; # for cko - for ARM div by 8
- mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
-}
-
-
-proc setup_pll { PLL_ADDR CLK } {
- set PLL_DP_CTL 0x00
- set PLL_DP_CONFIG 0x04
- set PLL_DP_OP 0x08
- set PLL_DP_HFS_OP 0x1C
- set PLL_DP_MFD 0x0C
- set PLL_DP_HFS_MFD 0x20
- set PLL_DP_MFN 0x10
- set PLL_DP_HFS_MFN 0x24
-
- if {$CLK == 1000} {
- set DP_OP [expr (10 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (12 - 1)]
- set DP_MFN 5
- } elseif {$CLK == 850} {
- set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (48 - 1)]
- set DP_MFN 41
- } elseif {$CLK == 800} {
- set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (3 - 1)]
- set DP_MFN 1
- } elseif {$CLK == 700} {
- set DP_OP [expr (7 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (24 - 1)]
- set DP_MFN 7
- } elseif {$CLK == 600} {
- set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (4 - 1)]
- set DP_MFN 1
- } elseif {$CLK == 665} {
- set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (96 - 1)]
- set DP_MFN 89
- } elseif {$CLK == 532} {
- set DP_OP [expr (5 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (24 - 1)]
- set DP_MFN 13
- } elseif {$CLK == 455} {
- set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
- set DP_MFD [expr (48 - 1)]
- set DP_MFN 71
- } elseif {$CLK == 400} {
- set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
- set DP_MFD [expr (3 - 1)]
- set DP_MFN 1
- } elseif {$CLK == 216} {
- set DP_OP [expr (6 << 4) + ((3 - 1) << 0)]
- set DP_MFD [expr (4 - 1)]
- set DP_MFN 3
- } else {
- error "Error (setup_dll): clock not found!"
- }
-
- mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
- mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
-
- mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
-
- mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
-
- mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
-
- mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
- while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
-}
-
-
-proc CPU_2_BE_32 { L } {
- return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)]
-}
-
-
-# Device Configuration Data
-proc DCD { } {
-# dap apsel 1
- mww 0x53fa86f4 0x00000000 ;# GRP_DDRMODE_CTL
- mww 0x53fa8714 0x00000000 ;# GRP_DDRMODE
- mww 0x53fa86fc 0x00000000 ;# GRP_DDRPKE
- mww 0x53fa8724 0x04000000 ;# GRP_DDR_TYPE
-
- mww 0x53fa872c 0x00300000 ;# GRP_B3DS
- mww 0x53fa8554 0x00300000 ;# DRAM_DQM3
- mww 0x53fa8558 0x00300040 ;# DRAM_SDQS3
-
- mww 0x53fa8728 0x00300000 ;# GRP_B2DS
- mww 0x53fa8560 0x00300000 ;# DRAM_DQM2
- mww 0x53fa8568 0x00300040 ;# DRAM_SDQS2
-
- mww 0x53fa871c 0x00300000 ;# GRP_B1DS
- mww 0x53fa8594 0x00300000 ;# DRAM_DQM1
- mww 0x53fa8590 0x00300040 ;# DRAM_SDQS1
-
- mww 0x53fa8718 0x00300000 ;# GRP_B0DS
- mww 0x53fa8584 0x00300000 ;# DRAM_DQM0
- mww 0x53fa857c 0x00300040 ;# DRAM_SDQS0
-
- mww 0x53fa8578 0x00300000 ;# DRAM_SDCLK_0
- mww 0x53fa8570 0x00300000 ;# DRAM_SDCLK_1
-
- mww 0x53fa8574 0x00300000 ;# DRAM_CAS
- mww 0x53fa8588 0x00300000 ;# DRAM_RAS
- mww 0x53fa86f0 0x00300000 ;# GRP_ADDDS
- mww 0x53fa8720 0x00300000 ;# GRP_CTLDS
-
- mww 0x53fa8564 0x00300040 ;# DRAM_SDODT1
- mww 0x53fa8580 0x00300040 ;# DRAM_SDODT0
-
- # Initialize DDR2 memory
- mww 0x63fd9088 0x32383535
- mww 0x63fd9090 0x40383538
- mww 0x63fd907c 0x0136014d
- mww 0x63fd9080 0x01510141
-
- mww 0x63fd9018 0x00011740
- mww 0x63fd9000 0xc3190000
- mww 0x63fd900c 0x555952e3
- mww 0x63fd9010 0xb68e8b63
- mww 0x63fd9014 0x01ff00db
- mww 0x63fd902c 0x000026d2
- mww 0x63fd9030 0x009f0e21
- mww 0x63fd9008 0x12273030
- mww 0x63fd9004 0x0002002d
- mww 0x63fd901c 0x00008032
- mww 0x63fd901c 0x00008033
- mww 0x63fd901c 0x00028031
- mww 0x63fd901c 0x092080b0
- mww 0x63fd901c 0x04008040
- mww 0x63fd901c 0x0000803a
- mww 0x63fd901c 0x0000803b
- mww 0x63fd901c 0x00028039
- mww 0x63fd901c 0x09208138
- mww 0x63fd901c 0x04008048
- mww 0x63fd9020 0x00001800
- mww 0x63fd9040 0x04b80003
- mww 0x63fd9058 0x00022227
- mww 0x63fd901c 0x00000000
-# dap apsel 0
-}
-
-# vim:filetype=tcl
diff --git a/openocd-0.10.0/scripts/board/imx53loco.cfg b/openocd-0.10.0/scripts/board/imx53loco.cfg
deleted file mode 100644
index 06c3993781e93d6eb1481ca1833f179022b87741..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/imx53loco.cfg
+++ /dev/null
@@ -1,315 +0,0 @@
-##################################################################################
-# Author: Wjatscheslaw Stoljarski (Slawa) <wjatscheslaw.stoljarski@kiwigrid.com> #
-# Kiwigrid GmbH #
-##################################################################################
-
-# The IMX53LOCO (QSB) board has a single IMX53 chip
-source [find target/imx53.cfg]
-# Helper for common memory read/modify/write procedures
-source [find mem_helper.tcl]
-
-echo "iMX53 Loco board lodaded."
-
-# Set reset type
-#reset_config srst_only
-
-adapter_khz 3000
-
-# Slow speed to be sure it will work
-jtag_rclk 1000
-$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
-
-#jtag_nsrst_delay 200
-#jtag_ntrst_delay 200
-
-$_TARGETNAME configure -event "reset-assert" {
- echo "Reseting ...."
- #cortex_a dbginit
-}
-
-$_TARGETNAME configure -event reset-init { loco_init }
-
-global AIPS1_BASE_ADDR
-set AIPS1_BASE_ADDR 0x53F00000
-global AIPS2_BASE_ADDR
-set AIPS2_BASE_ADDR 0x63F00000
-
-proc loco_init { } {
- echo "Reset-init..."
- ; # halt the CPU
- halt
-
- echo "HW version [format %x [mrw 0x48]]"
-
- dap apsel 1
- DCD
-
- ; # ARM errata ID #468414
- set tR [arm mrc 15 0 1 0 1]
- arm mcr 15 0 1 0 1 [expr $tR | (1<<5)] ; # enable L1NEON bit
-
- init_l2cc
- init_aips
- init_clock
-
- dap apsel 0
-
- ; # Force ARM state
- ; #reg cpsr 0x000001D3
- arm core_state arm
-
- jtag_rclk 3000
-# adapter_khz 3000
-}
-
-
-# L2CC Cache setup/invalidation/disable
-proc init_l2cc { } {
- ; #/* explicitly disable L2 cache */
- ; #mrc 15, 0, r0, c1, c0, 1
- set tR [arm mrc 15 0 1 0 1]
- ; #bic r0, r0, #0x2
- ; #mcr 15, 0, r0, c1, c0, 1
- arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
-
- ; #/* reconfigure L2 cache aux control reg */
- ; #mov r0, #0xC0 /* tag RAM */
- ; #add r0, r0, #0x4 /* data RAM */
- ; #orr r0, r0, #(1 << 24) /* disable write allocate delay */
- ; #orr r0, r0, #(1 << 23) /* disable write allocate combine */
- ; #orr r0, r0, #(1 << 22) /* disable write allocate */
-
- ; #mcr 15, 1, r0, c9, c0, 2
- arm mcr 15 1 9 0 2 [expr 0xC4 | (1<<24) | (1<<23) | (1<22)]
-}
-
-
-# AIPS setup - Only setup MPROTx registers.
-# The PACR default values are good.
-proc init_aips { } {
- ; # Set all MPROTx to be non-bufferable, trusted for R/W,
- ; # not forced to user-mode.
- global AIPS1_BASE_ADDR
- global AIPS2_BASE_ADDR
- set VAL 0x77777777
-
-# dap apsel 1
- mww [expr $AIPS1_BASE_ADDR + 0x0] $VAL
- mww [expr $AIPS1_BASE_ADDR + 0x4] $VAL
- mww [expr $AIPS2_BASE_ADDR + 0x0] $VAL
- mww [expr $AIPS2_BASE_ADDR + 0x4] $VAL
-# dap apsel 0
-}
-
-
-proc init_clock { } {
- global AIPS1_BASE_ADDR
- global AIPS2_BASE_ADDR
- set CCM_BASE_ADDR [expr $AIPS1_BASE_ADDR + 0x000D4000]
- set CLKCTL_CCSR 0x0C
- set CLKCTL_CBCDR 0x14
- set CLKCTL_CBCMR 0x18
- set PLL1_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00080000]
- set PLL2_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00084000]
- set PLL3_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x00088000]
- set PLL4_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x0008C000]
- set CLKCTL_CSCMR1 0x1C
- set CLKCTL_CDHIPR 0x48
- set PLATFORM_BASE_ADDR [expr $AIPS2_BASE_ADDR + 0x000A0000]
- set CLKCTL_CSCDR1 0x24
- set CLKCTL_CCDR 0x04
-
- ; # Switch ARM to step clock
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x4
-
- return
- echo "not returned"
- setup_pll $PLL1_BASE_ADDR 800
- setup_pll $PLL3_BASE_ADDR 400
-
- ; # Switch peripheral to PLL3
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00015154
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x02888945 | (1<<16)]
- while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
-
- setup_pll $PLL2_BASE_ADDR 400
-
- ; # Switch peripheral to PLL2
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCDR] [expr 0x00808145 | (2<<10) | (9<<16) | (1<<19)]
-
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CBCMR] 0x00016154
-
- ; # change uart clk parent to pll2
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCMR1]] & 0xfcffffff | 0x01000000]
-
- ; # make sure change is effective
- while {[mrw [expr $CCM_BASE_ADDR + $CLKCTL_CDHIPR]] != 0} { sleep 1 }
-
- setup_pll $PLL3_BASE_ADDR 216
-
- setup_pll $PLL4_BASE_ADDR 455
-
- ; # Set the platform clock dividers
- mww [expr $PLATFORM_BASE_ADDR + 0x14] 0x00000124
-
- mww [expr $CCM_BASE_ADDR + 0x10] 0
-
- ; # Switch ARM back to PLL 1.
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCSR] 0x0
-
- ; # make uart div=6
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1] [expr [mrw [expr $CCM_BASE_ADDR + $CLKCTL_CSCDR1]] & 0xffffffc0 | 0x0a]
-
- ; # Restore the default values in the Gate registers
- mww [expr $CCM_BASE_ADDR + 0x68] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x6C] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x70] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x74] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x78] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x7C] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x80] 0xFFFFFFFF
- mww [expr $CCM_BASE_ADDR + 0x84] 0xFFFFFFFF
-
- mww [expr $CCM_BASE_ADDR + $CLKCTL_CCDR] 0x00000
-
- ; # for cko - for ARM div by 8
- mww [expr $CCM_BASE_ADDR + 0x60] [expr 0x000A0000 & 0x00000F0]
-}
-
-
-proc setup_pll { PLL_ADDR CLK } {
- set PLL_DP_CTL 0x00
- set PLL_DP_CONFIG 0x04
- set PLL_DP_OP 0x08
- set PLL_DP_HFS_OP 0x1C
- set PLL_DP_MFD 0x0C
- set PLL_DP_HFS_MFD 0x20
- set PLL_DP_MFN 0x10
- set PLL_DP_HFS_MFN 0x24
-
- if {$CLK == 1000} {
- set DP_OP [expr (10 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (12 - 1)]
- set DP_MFN 5
- } elseif {$CLK == 850} {
- set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (48 - 1)]
- set DP_MFN 41
- } elseif {$CLK == 800} {
- set DP_OP [expr (8 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (3 - 1)]
- set DP_MFN 1
- } elseif {$CLK == 700} {
- set DP_OP [expr (7 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (24 - 1)]
- set DP_MFN 7
- } elseif {$CLK == 600} {
- set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (4 - 1)]
- set DP_MFN 1
- } elseif {$CLK == 665} {
- set DP_OP [expr (6 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (96 - 1)]
- set DP_MFN 89
- } elseif {$CLK == 532} {
- set DP_OP [expr (5 << 4) + ((1 - 1) << 0)]
- set DP_MFD [expr (24 - 1)]
- set DP_MFN 13
- } elseif {$CLK == 455} {
- set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
- set DP_MFD [expr (48 - 1)]
- set DP_MFN 71
- } elseif {$CLK == 400} {
- set DP_OP [expr (8 << 4) + ((2 - 1) << 0)]
- set DP_MFD [expr (3 - 1)]
- set DP_MFN 1
- } elseif {$CLK == 216} {
- set DP_OP [expr (6 << 4) + ((3 - 1) << 0)]
- set DP_MFD [expr (4 - 1)]
- set DP_MFN 3
- } else {
- error "Error (setup_dll): clock not found!"
- }
-
- mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
- mww [expr $PLL_ADDR + $PLL_DP_CONFIG] 0x2
-
- mww [expr $PLL_ADDR + $PLL_DP_OP] $DP_OP
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_OP
-
- mww [expr $PLL_ADDR + $PLL_DP_MFD] $DP_MFD
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFD] $DP_MFD
-
- mww [expr $PLL_ADDR + $PLL_DP_MFN] $DP_MFN
- mww [expr $PLL_ADDR + $PLL_DP_HFS_MFN] $DP_MFN
-
- mww [expr $PLL_ADDR + $PLL_DP_CTL] 0x00001232
- while {[expr [mrw [expr $PLL_ADDR + $PLL_DP_CTL]] & 0x1] == 0} { sleep 1 }
-}
-
-
-proc CPU_2_BE_32 { L } {
- return [expr (($L & 0x000000FF) << 24) | (($L & 0x0000FF00) << 8) | (($L & 0x00FF0000) >> 8) | (($L & 0xFF000000) >> 24)]
-}
-
-
-# Device Configuration Data
-proc DCD { } {
-# dap apsel 1
- mww 0x53FA8554 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3
- mww 0x53FA8558 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3
- mww 0x53FA8560 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2
- mww 0x53FA8564 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT
- mww 0x53FA8568 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2
- mww 0x53FA8570 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1
- mww 0x53FA8574 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS
- mww 0x53FA8578 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0
- mww 0x53FA857c 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0
- mww 0x53FA8580 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
- mww 0x53FA8584 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
- mww 0x53FA8588 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS
- mww 0x53FA8590 0x00300040 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1
- mww 0x53FA8594 0x00300000 ;# IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
- mww 0x53FA86f0 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_ADDDS
- mww 0x53FA86f4 0x00000000 ;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL
- mww 0x53FA86fc 0x00000000 ;# IOMUXC_SW_PAD_CTL_GRP_DDRPKE
- mww 0x53FA8714 0x00000000 ;# IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode
- mww 0x53FA8718 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_B0DS
- mww 0x53FA871c 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_B1DS
- mww 0x53FA8720 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_CTLDS
- mww 0x53FA8724 0x04000000 ;# IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL0=
- mww 0x53FA8728 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_B2DS
- mww 0x53FA872c 0x00300000 ;# IOMUXC_SW_PAD_CTL_GRP_B3DS
-
- # Initialize DDR2 memory
- mww 0x63FD9088 0x35343535 ;# ESDCTL_RDDLCTL
- mww 0x63FD9090 0x4d444c44 ;# ESDCTL_WRDLCTL
- mww 0x63FD907c 0x01370138 ;# ESDCTL_DGCTRL0
- mww 0x63FD9080 0x013b013c ;# ESDCTL_DGCTRL1
- mww 0x63FD9018 0x00011740 ;# ESDCTL_ESDMISC
- mww 0x63FD9000 0xc3190000 ;# ESDCTL_ESDCTL
- mww 0x63FD900c 0x9f5152e3 ;# ESDCTL_ESDCFG0
- mww 0x63FD9010 0xb68e8a63 ;# ESDCTL_ESDCFG1
- mww 0x63FD9014 0x01ff00db ;# ESDCTL_ESDCFG2
- mww 0x63FD902c 0x000026d2 ;# ESDCTL_ESDRWD
- mww 0x63FD9030 0x009f0e21 ;# ESDCTL_ESDOR
- mww 0x63FD9008 0x12273030 ;# ESDCTL_ESDOTC
- mww 0x63FD9004 0x0002002d ;# ESDCTL_ESDPDC
- mww 0x63FD901c 0x00008032 ;# ESDCTL_ESDSCR
- mww 0x63FD901c 0x00008033 ;# ESDCTL_ESDSCR
- mww 0x63FD901c 0x00028031 ;# ESDCTL_ESDSCR
- mww 0x63FD901c 0x052080b0 ;# ESDCTL_ESDSCR
- mww 0x63FD901c 0x04008040 ;# ESDCTL_ESDSCR
- mww 0x63FD901c 0x0000803a ;# ESDCTL_ESDSCR
- mww 0x63FD901c 0x0000803b ;# ESDCTL_ESDSCR
- mww 0x63FD901c 0x00028039 ;# ESDCTL_ESDSCR
- mww 0x63FD901c 0x05208138 ;# ESDCTL_ESDSCR
- mww 0x63FD901c 0x04008048 ;# ESDCTL_ESDSCR
- mww 0x63FD9020 0x00005800 ;# ESDCTL_ESDREF
- mww 0x63FD9040 0x04b80003 ;# ESDCTL_ZQHWCTRL
- mww 0x63FD9058 0x00022227 ;# ESDCTL_ODTCTRL
- mww 0x63FD901C 0x00000000 ;# ESDCTL_ESDSCR
-# dap apsel 0
-}
-
-# vim:filetype=tcl
diff --git a/openocd-0.10.0/scripts/board/insignal_arndale.cfg b/openocd-0.10.0/scripts/board/insignal_arndale.cfg
deleted file mode 100644
index 25c123e7b84831d8682033acc36b1b71202d69fb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/insignal_arndale.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# InSignal Arndale board
-#
-
-source [find target/exynos5250.cfg]
-
-# Experimentally determined highest working speed
-adapter_khz 200
diff --git a/openocd-0.10.0/scripts/board/kc705.cfg b/openocd-0.10.0/scripts/board/kc705.cfg
deleted file mode 100644
index 39f7fa39c22db9f98af9576b29d8fafdd9416cb9..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/kc705.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-# http://www.xilinx.com/products/boards-and-kits/ek-k7-kc705-g.html
-
-source [find interface/ftdi/digilent-hs1.cfg]
-source [find cpld/xilinx-xc7.cfg]
-source [find cpld/jtagspi.cfg]
-adapter_khz 25000
-
-# example command to write bitstream, soft-cpu bios and runtime:
-# openocd -f board/kc705.cfg -c "init;\
-# jtagspi_init 0 bscan_spi_xc7k325t.bit;\
-# jtagspi_program bitstream-kc705.bin 0;\
-# jtagspi_program bios.bin 0xaf0000;\
-# jtagspi_program runtime.fbi 0xb00000;\
-# xc7_program xc7.tap;\
-# exit"
diff --git a/openocd-0.10.0/scripts/board/keil_mcb1700.cfg b/openocd-0.10.0/scripts/board/keil_mcb1700.cfg
deleted file mode 100644
index d63d3ede91c2d9654b2490093ca90bbd7fb369b6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/keil_mcb1700.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Keil MCB1700 eval board
-#
-# http://www.keil.com/mcb1700/picture.asp
-#
-
-source [find target/lpc17xx.cfg]
-
diff --git a/openocd-0.10.0/scripts/board/keil_mcb2140.cfg b/openocd-0.10.0/scripts/board/keil_mcb2140.cfg
deleted file mode 100644
index db81efad53c9592c2419fbcb2736286a7827aacd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/keil_mcb2140.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Keil MCB2140 eval board
-#
-# http://www.keil.com/mcb2140/picture.asp
-#
-
-source [find target/lpc2148.cfg]
-
diff --git a/openocd-0.10.0/scripts/board/kwikstik.cfg b/openocd-0.10.0/scripts/board/kwikstik.cfg
deleted file mode 100644
index f936d6e92ad30e48cf7c486af71f8e303f3345f2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/kwikstik.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Freescale KwikStik development board
-#
-
-#
-# JLINK interface is onboard
-#
-source [find interface/jlink.cfg]
-
-source [find target/k40.cfg]
-
-reset_config trst_and_srst
diff --git a/openocd-0.10.0/scripts/board/la_fonera-fon2200.cfg b/openocd-0.10.0/scripts/board/la_fonera-fon2200.cfg
deleted file mode 100644
index f46b04200af180cf3206cee3dad755efdc67c6bb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/la_fonera-fon2200.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-source [find target/atheros_ar2315.cfg]
-
-reset_config trst_and_srst
diff --git a/openocd-0.10.0/scripts/board/linksys-wag200g.cfg b/openocd-0.10.0/scripts/board/linksys-wag200g.cfg
deleted file mode 100644
index aa4887f9484636530b4c4a42bbd376e8499996bc..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/linksys-wag200g.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# Linksys WAG200G Router
-#
-# The stock firmware Flash layout is organized as follow:
-#
-# Start End Device
-# 0x90000000 0x90020000 /dev/mtdblock/2
-# 0x90020000 0x900d0000 /dev/mtdblock/1
-# 0x900d0000 0x903a0000 /dev/mtdblock/0
-# 0x903a0000 0x903e0000 /dev/mtdblock/5
-# 0x903e0000 0x903f0000 /dev/mtdblock/3
-# 0x903f0000 0x90400000 /dev/mtdblock/4
-
-set partition_list {
- adam2 { "Adam2 bootloader" 0x90000000 0x00020000 }
- kernel { "Kernel" 0x90020000 0x000b0000 }
- rootfs { "Root FS" 0x900d0000 0x002d0000 }
- lang { "Minix language part" 0x903a0000 0x00040000 }
- config { "Firmware config" 0x903e0000 0x00010000 }
- adam2env { "Adam2 environment" 0x903f0000 0x00010000 }
-}
-
-source [find target/ti-ar7.cfg]
-
-# External 4MB MXIC 29LV320MBTC Flash (Manufacturer/Device: 0x00c2 0x227e)
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x90000000 0x00400000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/linksys-wrt54gl.cfg b/openocd-0.10.0/scripts/board/linksys-wrt54gl.cfg
deleted file mode 100644
index ffe53ffbb36cf2e8e520e9c40810eaa9ca2f7f08..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/linksys-wrt54gl.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Linksys WRT54GL v1.1
-#
-
-source [find target/bcm5352e.cfg]
-
-set partition_list {
- CFE { Bootloader 0x1c000000 0x00040000 }
- firmware { "Kernel+rootfs" 0x1c040000 0x003b0000 }
- nvram { "Config space" 0x1c3f0000 0x00010000 }
-}
-
-# External 4MB NOR Flash (Intel TE28F320C3BD90 or similar)
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x1c000000 0x00400000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/linksys_nslu2.cfg b/openocd-0.10.0/scripts/board/linksys_nslu2.cfg
deleted file mode 100644
index e605fc19e01d5f387fb3fe61ee5137c23a9891dc..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/linksys_nslu2.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# This is for the LinkSys (CISCO) NSLU2 board
-# It is an Intel XSCALE IXP420 CPU.
-
-source [find target/ixp42x.cfg]
-# The _TARGETNAME is set by the above.
-
-$_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
-
diff --git a/openocd-0.10.0/scripts/board/lisa-l.cfg b/openocd-0.10.0/scripts/board/lisa-l.cfg
deleted file mode 100644
index 73f51a26da57e89afedd0a24878c99c37ef4e65b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/lisa-l.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-# the Lost Illusions Serendipitous Autopilot
-# http://paparazzi.enac.fr/wiki/Lisa
-
-# Work-area size (RAM size) = 20kB for STM32F103RB device
-set WORKAREASIZE 0x5000
-
-source [find target/stm32f1x.cfg]
diff --git a/openocd-0.10.0/scripts/board/logicpd_imx27.cfg b/openocd-0.10.0/scripts/board/logicpd_imx27.cfg
deleted file mode 100644
index da0b46223d52948aa08d798b7a48d334c81f57eb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/logicpd_imx27.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-# The LogicPD Eval IMX27 eval board has a single IMX27 chip
-source [find target/imx27.cfg]
-
-# The Logic PD board has a NOR flash on CS0
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0xc0000000 0x00200000 2 2 $_TARGETNAME
-
-#
-# FIX ME, Add support to
-#
-# (A) hard reset the board.
-# (B) Initialize the SDRAM on the board
-#
diff --git a/openocd-0.10.0/scripts/board/lpc1850_spifi_generic.cfg b/openocd-0.10.0/scripts/board/lpc1850_spifi_generic.cfg
deleted file mode 100644
index bff4af6050462efce7d07ba972c07cb3692b3e99..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/lpc1850_spifi_generic.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Generic LPC1850 board w/ SPIFI flash.
-# This config file is intended as an example of how to
-# use the lpcspifi flash driver, but it should be functional
-# for most LPC1850 boards utilizing SPIFI flash.
-
-set CHIPNAME lpc1850
-
-source [find target/lpc1850.cfg]
-
-#A large working area greatly reduces flash write times
-set _WORKAREASIZE 0x4000
-
-$_CHIPNAME.m3 configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
-
-#Configure the flash bank; 0x14000000 is the base address for
-#lpc43xx/lpc18xx family micros.
-flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m3
diff --git a/openocd-0.10.0/scripts/board/lpc4350_spifi_generic.cfg b/openocd-0.10.0/scripts/board/lpc4350_spifi_generic.cfg
deleted file mode 100644
index b363f1eff8d27c7d63121b8ffbe64e9d962dbe91..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/lpc4350_spifi_generic.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Generic LPC4350 board w/ SPIFI flash.
-# This config file is intended as an example of how to
-# use the lpcspifi flash driver, but it should be functional
-# for most LPC4350 boards utilizing SPIFI flash.
-
-set CHIPNAME lpc4350
-
-source [find target/lpc4350.cfg]
-
-#Configure the flash bank; 0x14000000 is the base address for
-#lpc43xx/lpc18xx family micros.
-flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m4
diff --git a/openocd-0.10.0/scripts/board/lubbock.cfg b/openocd-0.10.0/scripts/board/lubbock.cfg
deleted file mode 100644
index 298954cc0678f4a32d66f0e0fcb88c1a7c2e7689..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/lubbock.cfg
+++ /dev/null
@@ -1,112 +0,0 @@
-# Intel "Lubbock" Development Board with PXA255 (dbpxa255)
-# Obsolete; this was Intel's original PXA255 development system
-# Board also had CPU cards for SA1100, PXA210, PXA250, and more.
-
-source [find target/pxa255.cfg]
-
-adapter_nsrst_delay 250
-jtag_ntrst_delay 250
-
-# NOTE: until after pinmux and such are set up, only CS0 is
-# available ... not 2nd bank of CFI, or FPGA, SRAM, ENET, etc.
-
-# CS0, CS1 -- two banks of CFI flash, 32 MBytes each
-# each bank is 32-bits wide, two 16-bit chips in parallel
-set _FLASHNAME $_CHIPNAME.flash0
-flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
-
-# CS2 low -- FPGA registers
-# CS2 high -- 1 MByte SRAM at 0x0a00.0000 ... last 64K for scratch
-$_TARGETNAME configure -work-area-phys 0x0a0f0000
-
-$_TARGETNAME configure -event reset-assert-pre \
- "$_TARGETNAME configure -work-area-size 0"
-
-# Make the hex led display a number, assuming CS2 is set up
-# and all digits have been enabled through the FPGA.
-proc hexled {u32} {
- mww 0x08000010 $u32
-}
-
-# CS3 -- Ethernet
-# CS4 -- SA1111
-# CS5 -- PCMCIA
-
-# NOTE: system console normally uses the FF UART connector
-
-proc lubbock_init {target} {
-
- echo "Initialize PXA255 Lubbock board"
-
- # (1) pinmux
-
- # GPSR0..GPSR2
- mww 0x40e00018 0x00008000
- mww 0x40e0001c 0x00FC0382
- mww 0x40e00020 0x0001FFFF
- # GPDR0..GPDR2
- mww 0x40e0000c 0x0060A800
- mww 0x40e00010 0x00FF0382
- mww 0x40e00014 0x0001C000
- # GAFR0_[LU]..GAFR2_[LU]
- mww 0x40e00054 0x98400000
- mww 0x40e00058 0x00002950
- mww 0x40e0005c 0x000A9558
- mww 0x40e00060 0x0005AAAA
- mww 0x40e00064 0xA0000000
- mww 0x40e00068 0x00000002
-
- # write PSSR, enable GPIOs
- mww 0x40f00000 0x00000020
-
- # write LED ctrl register ... ones disable
- # high byte, 8 hex leds; low byte, 8 discretes
- mwh 0x08000040 0xf0ff
-
- hexled 0x0000
-
- # (2) Address space setup
-
- # MSC0/MSC1/MSC2
- mww 0x48000008 0x23f223f2
- mww 0x4800000c 0x3ff1a441
- mww 0x48000010 0x7ff97ff1
- # pcmcia/cf
- mww 0x48000014 0x00000000
- mww 0x48000028 0x00010504
- mww 0x4800002c 0x00010504
- mww 0x48000030 0x00010504
- mww 0x48000034 0x00010504
- mww 0x48000038 0x00004715
- mww 0x4800003c 0x00004715
-
- hexled 0x1111
-
- # (3) SDRAM setup
- # REVISIT this looks dubious ... no refresh cycles
- mww 0x48000004 0x03CA4018
- mww 0x48000004 0x004B4018
- mww 0x48000004 0x000B4018
- mww 0x48000004 0x000BC018
- mww 0x48000000 0x00001AC8
- mww 0x48000000 0x00001AC9
-
- mww 0x48000040 0x00000000
-
- # FIXME -- setup:
- # CLOCKS (and faster JTAG)
- # enable icache
-
- # FIXME SRAM isn't working
- # $target configure -work-area-size 0x10000
-
- hexled 0x2222
-
- flash probe 0
- flash probe 1
-
- hexled 0xcafe
-}
-$_TARGETNAME configure -event reset-init "lubbock_init $_TARGETNAME"
diff --git a/openocd-0.10.0/scripts/board/marsohod.cfg b/openocd-0.10.0/scripts/board/marsohod.cfg
deleted file mode 100644
index 681f575cc3abf386a18ee3df7cf9f075b012574c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/marsohod.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Marsohod CPLD Development and Education board
-#
-# http://marsohod.org/howtostart/plata
-#
-
-# Recommended MBFTDI programmer
-source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
-transport select jtag
-
-# Altera MAXII EPM240T100C CPLD
-source [find cpld/altera-epm240.cfg]
diff --git a/openocd-0.10.0/scripts/board/marsohod2.cfg b/openocd-0.10.0/scripts/board/marsohod2.cfg
deleted file mode 100644
index d4897c3c33b6fec6be2b7a8a945a35d72d422a91..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/marsohod2.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Marsohod2 FPGA Development and Education board
-#
-# http://www.marsohod.org/prodmarsohod2
-#
-
-# Built-in MBFTDI programmer
-source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
-transport select jtag
-
-# Cyclone III EP3C10E144 FPGA
-source [find fpga/altera-ep3c10.cfg]
diff --git a/openocd-0.10.0/scripts/board/marsohod3.cfg b/openocd-0.10.0/scripts/board/marsohod3.cfg
deleted file mode 100644
index bb3c74f28e0c0a2ebb3c802719ba8c7f492328d4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/marsohod3.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Marsohod3 FPGA Development and Education board
-#
-# http://www.marsohod.org/plata-marsokhod3
-#
-
-# Built-in MBFTDI programmer
-source [find interface/ftdi/mbftdi.cfg]
-adapter_khz 2000
-transport select jtag
-
-# MAX10 10M50SAE144C8GES FPGA
-source [find fpga/altera-10m50.cfg]
diff --git a/openocd-0.10.0/scripts/board/mbed-lpc11u24.cfg b/openocd-0.10.0/scripts/board/mbed-lpc11u24.cfg
deleted file mode 100644
index b1ec2a5194c639d65d6ee3940f57d65bd73b35ed..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/mbed-lpc11u24.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# This is an mbed eval board with a single NXP LPC11U24 chip.
-# http://mbed.org/handbook/mbed-NXP-LPC11U24
-#
-
-source [find interface/cmsis-dap.cfg]
-
-# NXP LPC11U24 Cortex-M0 with 32kB Flash and 8kB SRAM
-set WORKAREASIZE 0x2000
-
-source [find target/lpc11xx.cfg]
diff --git a/openocd-0.10.0/scripts/board/mbed-lpc1768.cfg b/openocd-0.10.0/scripts/board/mbed-lpc1768.cfg
deleted file mode 100644
index 67f834011d40ccc2f67d78ba7c3818eb26696b84..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/mbed-lpc1768.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-# This is an mbed eval board with a single NXP LPC1768 chip.
-# http://mbed.org/handbook/mbed-NXP-LPC1768
-#
-
-source [find interface/cmsis-dap.cfg]
-
-source [find target/lpc17xx.cfg]
diff --git a/openocd-0.10.0/scripts/board/mcb1700.cfg b/openocd-0.10.0/scripts/board/mcb1700.cfg
deleted file mode 100644
index 068a19b24d5c3c19c25c82e2958e45d5bc9fd12e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/mcb1700.cfg
+++ /dev/null
@@ -1,75 +0,0 @@
-# Keil MCB1700 PCB with 1768
-#
-# Reset init script sets it to 100MHz
-set CCLK 100000
-
-source [find target/lpc17xx.cfg]
-
-global MCB1700_CCLK
-set MCB1700_CCLK $CCLK
-
-$_TARGETNAME configure -event reset-start {
- # Start *real slow* as we do not know the
- # state the boot rom left the clock in
- adapter_khz 10
-}
-
-# Set up 100MHz clock to CPU
-$_TARGETNAME configure -event reset-init {
- # PLL0CON: Disable PLL
- mww 0x400FC080 0x00000000
- # PLLFEED
- mww 0x400FC08C 0x000000AA
- # PLLFEED
- mww 0x400FC08C 0x00000055
-
- # CCLK=PLL/4 (=100 MHz)
- mww 0x400FC104 0x00000003
- # CLKSRCSEL: Clock source = internal RC oscillator
- mww 0x400FC10C 0x00000000
-
- # PLL0CFG: M=50,N=1 -> PLL=400 MHz
- mww 0x400FC084 0x00000031
- # PLLFEED
- mww 0x400FC08C 0x000000AA
- # PLLFEED
- mww 0x400FC08C 0x00000055
-
- # PLL0CON: Enable PLL
- mww 0x400FC080 0x00000001
- # PLLFEED
- mww 0x400FC08C 0x000000AA
- # PLLFEED
- mww 0x400FC08C 0x00000055
-
- sleep 50
-
- # PLL0CON: Connect PLL
- mww 0x400FC080 0x00000003
- # PLLFEED
- mww 0x400FC08C 0x000000AA
- # PLLFEED
- mww 0x400FC08C 0x00000055
-
- # Dividing CPU clock by 8 should be pretty conservative
- #
- #
- global MCB1700_CCLK
- adapter_khz [expr $MCB1700_CCLK / 8]
-
- # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
- # "User Flash Mode" where interrupt vectors are _not_ remapped,
- # and reside in flash instead).
- #
- # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
- # Bit Symbol Value Description Reset
- # value
- # 0 MAP Memory map control. 0
- # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
- # 1 User mode. The on-chip Flash memory is mapped to address 0.
- # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
- #
- # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
-
- mww 0x400FC040 0x01
-}
diff --git a/openocd-0.10.0/scripts/board/microchip_explorer16.cfg b/openocd-0.10.0/scripts/board/microchip_explorer16.cfg
deleted file mode 100644
index 7c036c665cb02c295bfa7ee511ba76a95a6fbcf0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/microchip_explorer16.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# Microchip Explorer 16 with PIC32MX360F512L PIM module.
-# http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1406&dDocName=en024858
-
-# TAPID for PIC32MX360F512L
-set CPUTAPID 0x30938053
-
-# use 32k working area
-set WORKAREASIZE 32768
-
-source [find target/pic32mx.cfg]
diff --git a/openocd-0.10.0/scripts/board/mini2440.cfg b/openocd-0.10.0/scripts/board/mini2440.cfg
deleted file mode 100644
index 874f829ab17b1fa54679adec01f5d0831bf8b7c3..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/mini2440.cfg
+++ /dev/null
@@ -1,320 +0,0 @@
-#-------------------------------------------------------------------------
-# Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R
-# NOTE: Configured for NAND boot (switch S2 in NANDBOOT)
-# 64 MB NAND (Samsung K9D1208V0M)
-# B Findlay 08/09
-#
-# ----------- Important notes to help you on your way ----------
-# README:
-# NOR/NAND Boot Switch - I have not read the vivi source, but from
-# what I could tell from reading the registers it appears that vivi
-# loads itself into DRAM and then flips NFCONT (0x4E000004) bits
-# Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND
-# FLASH at the bottom 64MB of memory. This essentially takes the
-# NOR Flash out of the circuit so you can't trash it.
-#
-# I adapted the samsung_s3c2440.cfg file which is why I did not
-# include "source [find target/samsung_s3c2440.cfg]". I believe
-# the -work-area-phys 0x200000 is incorrect, but also had to pad
-# some additional resets. I didn't modify it as if it is working
-# for someone, the work-area-phys is not used by most.
-#
-# JTAG ADAPTER SPECIFIC
-# IMPORTANT! Any JTAG device that uses ADAPTIVE CLOCKING will likely
-# FAIL as the pin RTCK on the mini2440 10 pin JTAG Conn doesn't exist.
-# This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is
-# necessary to FORCE setting the clock. Normally this should be configured
-# in the openocd.cfg file, but was placed here as it can be a tough
-# problem to figure out. THIS MAY NOT FIX YOUR PROBLEM.. I modified
-# the openOCD driver jlink.c and posted it here. It may eventually end
-# up changed in openOCD, but its a hack in the driver and really should
-# be in the jtag layer (core.c me thinks), but haven't done it yet. My
-# hack for jlink.c may be found here.
-#
-# http://forum.sparkfun.com/viewtopic.php?t=16763&sid=946e65abdd3bab39cc7d90dee33ff135
-#
-# Note: Also if you have a USB JTAG, you will need the USB library installed
-# on your system "libusb-dev" or the make of openocd will fail. I *think*
-# it's apt-get install libusb-dev. When I made my config I only included
-# --enable-jlink and --enable-usbdevs
-#
-# I HAVE NOT Tested this throughly, so there could still be problems.
-# But it should get you way ahead of the game from where I started.
-# If you find problems (and fixes) please post them to
-# openocd-development@lists.berlios.de and join the developers and
-# check in fixes to this and anything else you find. I do not
-# provide support, but if you ask really nice and I see anything
-# obvious I will tell you.. mostly just dig, fix, and submit to openocd.
-#
-# best! brfindla@yahoo.com Nashua, NH USA
-#
-# Recommended resources:
-# - first two are the best Mini2440 resources anywhere
-# - maintained by buserror... thanks guy!
-#
-# http://bliterness.blogspot.com/
-# http://code.google.com/p/mini2440/
-#
-# others....
-#
-# http://forum.sparkfun.com/viewforum.php?f=18
-# http://labs.kernelconcepts.de/Publications/Micro24401/
-# http://www.friendlyarm.net/home
-# http://www.amontec.com/jtag_pinout.shtml
-#
-#-------------------------------------------------------------------------
-#
-#
-# Your openocd.cfg file should contain:
-# source [find interface/<yourjtag>.cfg]
-# source [find board/mini2440.cfg]
-#
-#
-#
-
-# FIXME use some standard target config, maybe create one from this
-#
-# source [find target/...cfg]
-
-#-------------------------------------------------------------------------
-# Target configuration for the Samsung 2440 system on chip
-# Tested on a S3C2440 Evaluation board by keesj
-# Processor : ARM920Tid(wb) rev 0 (v4l)
-# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d
-# (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
-#-------------------------------------------------------------------------
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME s3c2440
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a bigendian
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x0032409d
-}
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 1
-
-#reset configuration
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-reset_config trst_and_srst
-
-#-------------------------------------------------------------------------
-# JTAG ADAPTER SPECIFIC
-# IMPORTANT! See README at top of this file.
-#-------------------------------------------------------------------------
-
- adapter_khz 12000
- jtag interface
-
-#-------------------------------------------------------------------------
-# GDB Setup
-#-------------------------------------------------------------------------
-
- gdb_breakpoint_override hard
-
-#------------------------------------------------
-# ARM SPECIFIC
-#------------------------------------------------
-
- targets
- # arm7_9 dcc_downloads enable
- # arm7_9 fast_memory_access enable
-
-
- nand device s3c2440 0
-
- adapter_nsrst_delay 100
- jtag_ntrst_delay 100
- reset_config trst_and_srst
- init
-
- echo " "
- echo "-------------------------------------------"
- echo "--- login with - telnet localhost 4444 ---"
- echo "--- then type help_2440 ---"
- echo "-------------------------------------------"
- echo " "
-
-
-
-#------------------------------------------------
-# Processor Initialialization
-# Note: Processor writes can only occur when
-# the state is in SYSTEM. When you call init_2440
-# one of the first lines will tell you what state
-# you are in. If a linux image is booting
-# when you run this, it will not work
-# a vivi boot loader will run with this just
-# fine. The reg values were obtained by a combination
-# of figuring them out fromt the manual, and looking
-# at post vivi values with the debugger. Don't
-# place too much faith in them, but seem to work.
-#------------------------------------------------
-
-proc init_2440 { } {
-
- halt
- s3c2440.cpu curstate
-
- #-----------------------------------------------
- # Set Processor Clocks - mini2440 xtal=12mHz
- # we set main clock for 405mHZ
- # we set the USB Clock for 48mHz
- # OM2 OM3 pulled to ground so main clock and
- # usb clock are off 12mHz xtal
- #-----------------------------------------------
-
- mww phys 0x4C000014 0x00000005 ;# Clock Divider control Reg
- mww phys 0x4C000000 0xFFFFFFFF ;# LOCKTIME count register
- mww phys 0x4C000008 0x00038022 ;# UPPLCON USB clock config Reg
- mww phys 0x4C000004 0x0007F021 ;# MPPLCON Proc clock config Reg
-
- #-----------------------------------------------
- # Configure Memory controller
- # BWSCON configures all banks, NAND, NOR, DRAM
- # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
- #-----------------------------------------------
-
- mww phys 0x48000000 0x22111112 ;# BWSCON - Bank and Bus Width
- mww phys 0x48000010 0x00001112 ;# BANKCON4 - ?
- mww phys 0x4800001c 0x00018009 ;# BANKCON6 - DRAM
- mww phys 0x48000020 0x00018009 ;# BANKCON7 - DRAM
- mww phys 0x48000024 0x008E04EB ;# REFRESH - DRAM
- mww phys 0x48000028 0x000000B2 ;# BANKSIZE - DRAM
- mww phys 0x4800002C 0x00000030 ;# MRSRB6 - DRAM
- mww phys 0x48000030 0x00000030 ;# MRSRB7 - DRAM
-
- #-----------------------------------------------
- # Now port configuration for enables for memory
- # and other stuff.
- #-----------------------------------------------
-
- mww phys 0x56000000 0x007FFFFF ;# GPACON
-
- mww phys 0x56000010 0x00295559 ;# GPBCON
- mww phys 0x56000018 0x000003FF ;# GPBUP (PULLUP ENABLE)
- mww phys 0x56000014 0x000007C2 ;# GPBDAT
-
- mww phys 0x56000020 0xAAAAA6AA ;# GPCCON
- mww phys 0x56000028 0x0000FFFF ;# GPCUP
- mww phys 0x56000024 0x00000020 ;# GPCDAT
-
- mww phys 0x56000030 0xAAAAAAAA ;# GPDCON
- mww phys 0x56000038 0x0000FFFF ;# GPDUP
-
- mww phys 0x56000040 0xAAAAAAAA ;# GPECON
- mww phys 0x56000048 0x0000FFFF ;# GPEUP
-
- mww phys 0x56000050 0x00001555 ;# GPFCON
- mww phys 0x56000058 0x0000007F ;# GPFUP
- mww phys 0x56000054 0x00000000 ;# GPFDAT
-
- mww phys 0x56000060 0x00150114 ;# GPGCON
- mww phys 0x56000068 0x0000007F ;# GPGUP
-
- mww phys 0x56000070 0x0015AAAA ;# GPHCON
- mww phys 0x56000078 0x000003FF ;# GPGUP
-
-}
-
-
-
-proc flash_config { } {
-
- #-----------------------------------------
- # Finish Flash Configuration
- #-----------------------------------------
-
- halt
-
- #flash configuration (K9D1208V0M: 512Mbit, x8, 3.3V, Mode: Normal, 1st gen)
- nand probe 0
- nand list
-}
-
-proc flash_uboot { } {
-
- # flash the u-Boot binary and reboot into it
- init_2440
- flash_config
- nand erase 0 0x0 0x40000
- nand write 0 /tftpboot/u-boot-nand512.bin 0 oob_softecc_kw
- resume
-}
-
-
-proc load_uboot { } {
- echo " "
- echo " "
- echo "----------------------------------------------------------"
- echo "---- Load U-Boot into RAM and execute it. ---"
- echo "---- NOTE: loads, partially runs, and hangs ---"
- echo "---- U-Boot is fine, this image runs from vivi. ---"
- echo "---- I burned u-boot into NAND so I didn't finish ---"
- echo "---- debugging it. I am leaving this here as it is ---"
- echo "---- part of the way there if you want to fix it. ---"
- echo "---- ---"
- echo "---- mini2440 U-boot here: ---"
- echo "---- http://repo.or.cz/w/u-boot-openmoko/mini2440.git ---"
- echo "---- Also this: ---"
- echo "---- http://code.google.com/p/mini2440/wiki/MiniBringup --"
- echo "----------------------------------------------------------"
-
- init_2440
- echo "Loading /tftpboot/u-boot-nand512.bin"
- load_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
- echo "Verifying image...."
- verify_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
- echo "jumping to u-boot"
- #bp 0x33f80068 4 hw
- reg 0 0
- reg 1 0
- reg 2 0
- reg 3 0
- reg 4 0x33f80000
- resume 0x33f80000
-}
-
- # this may help a little bit debugging the load_uboot
-proc s {} {
- step
- reg
- arm disassemble 0x33F80068 0x10
-}
-
-proc help_2440 {} {
- echo " "
- echo " "
- echo "-----------------------------------------------------------"
- echo "---- The following mini2440 funcs are supported ----"
- echo "---- init_2440 - initialize clocks, DRAM, IO ----"
- echo "---- flash_config - configures nand flash ----"
- echo "---- load_uboot - loads uboot into ram ----"
- echo "---- flash_uboot - flashes uboot to nand (untested) ----"
- echo "---- help_2440 - this help display ----"
- echo "-----------------------------------------------------------"
- echo " "
- echo " "
-}
-
-
-#----------------------------------------------------------------------------
-#----------------------------------- END ------------------------------------
-#----------------------------------------------------------------------------
diff --git a/openocd-0.10.0/scripts/board/mini6410.cfg b/openocd-0.10.0/scripts/board/mini6410.cfg
deleted file mode 100644
index d00ce1f8c52e4a30e48bcc9e89058d7a133315e4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/mini6410.cfg
+++ /dev/null
@@ -1,112 +0,0 @@
-# Target configuration for the Samsung s3c6410 system on chip
-# Tested on a tiny6410
-# Processor : ARM1176
-# Info : JTAG tap: s3c6410.etb tap/device found: 0x2b900f0f (mfg: 0x787, part: 0xb900, ver: 0x2)
-# Info : JTAG tap: s3c6410.cpu tap/device found: 0x07b76f0f (mfg: 0x787, part: 0x7b76, ver: 0x0)
-
-source [find target/samsung_s3c6410.cfg]
-
-proc init_6410 {} {
- halt
- reg cpsr 0x1D3
- arm mcr 15 0 15 2 4 0x70000013
-
- #-----------------------------------------------
- # Clock and Timer Setting
- #-----------------------------------------------
- mww 0x7e004000 0 ;# WATCHDOG - Disable
- mww 0x7E00F120 0x0003 ;# MEM_SYS_CFG - CS0:8 bit, Mem1:32bit, CS2=NAND
- #mww 0x7E00F120 0x1000 ;# MEM_SYS_CFG - CS0:16bit, Mem1:32bit, CS2=SROMC
- #mww 0x7E00F120 0x1002 ;# MEM_SYS_CFG - CS0:16bit, Mem1:32bit, CS2=OND
- mww 0x7E00F900 0x805e ;# OTHERS - Change SYNCMUX[6] to “1”
- sleep 1000
- mww 0x7E00F900 0x80de ;# OTHERS - Assert SYNCREQ&VICSYNCEN to “1”(rb1004modify)
- sleep 1000 ;# - Others[11:8] to 0xF
- mww 0x7E00F000 0xffff ;# APLL_LOCK - APLL LockTime
- mww 0x7E00F004 0xffff ;# MPLL_LOCK - MPLL LockTime
- mww 0x7E00F020 0x1047310 ;# CLK_DIV0 - ARMCLK:HCLK:PCLK = 1:4:16
- mww 0x7E00F00c 0x81900302 ;# APLL_CON - A:400, P:3, S:2 => 400MHz
- mww 0x7E00F010 0x81900303 ;# MPLL_CON - M:400, P:3, S:3 => 200MHz
- mww 0x7E00F01c 0x3 ;# CLK_SRC - APLL,MPLL Clock Select
-
- #-----------------------------------------------
- # DRAM initialization
- #-----------------------------------------------
- mww 0x7e001004 0x4 ;# P1MEMCCMD - Enter the config state
- mww 0x7e001010 0x30C ;# P1REFRESH - Refresh Period register (7800ns), 100MHz
-# mww 0x7e001010 0x40e ;# P1REFRESH - Refresh Period register (7800ns), 133MHz
- mww 0x7e001014 0x6 ;# P1CASLAT - CAS Latency = 3
- mww 0x7e001018 0x1 ;# P1T_DQSS
- mww 0x7e00101c 0x2 ;# P1T_MRD
- mww 0x7e001020 0x7 ;# P1T_RAS - 45 ns
- mww 0x7e001024 0xA ;# P1T_RC - 67.5 ns
- mww 0x7e001028 0xC ;# P1T_RCD - 22.5 ns
- mww 0x7e00102C 0x10B ;# P1T_RFC - 80 ns
- mww 0x7e001030 0xC ;# P1T_RP - 22.5 ns
- mww 0x7e001034 0x3 ;# P1T_RRD - 15 ns
- mww 0x7e001038 0x3 ;# P1T_WR - 15 ns
- mww 0x7e00103C 0x2 ;# P1T_WTR
- mww 0x7e001040 0x2 ;# P1T_XP
- mww 0x7e001044 0x11 ;# P1T_XSR - 120 ns
- mww 0x7e001048 0x11 ;# P1T_ESR
-
- #-----------------------------------------------
- # Memory Configuration Registers
- #-----------------------------------------------
- mww 0x7e00100C 0x00010012 ;# P1MEMCFG - 1 CKE, 1Chip, 4burst, Alw, AP[10],ROW/Column bit
- mww 0x7e00104C 0x0B41 ;# P1MEMCFG2 - Read delay 1 Cycle, mDDR, 32bit, Sync.
- mww 0x7e001200 0x150F0 ;# CHIP_N_CFG - 0x150F0 for 256M, 0x150F8 for 128M
-
- #-----------------------------------------------
- # Memory Direct Commands
- #-----------------------------------------------
- mww 0x7e001008 0xc0000 ;# Chip0 Direct Command :NOP5
- mww 0x7e001008 0x0 ;# Chip0 Direct Command :PreCharge al
- mww 0x7e001008 0x40000 ;# Chip0 Direct Command :AutoRefresh
- mww 0x7e001008 0x40000 ;# Chip0 Direct Command :AutoRefresh
- mww 0x7e001008 0xA0000 ;# EMRS, DS:Full, PASR:Full
- mww 0x7e001008 0x80032 ;# MRS, CAS3, BL4
- mww 0x7e001004 0x0 ;# Enable DMC1
-}
-
-proc install_6410_uboot {} {
- # write U-boot magic number
- mww 0x50000000 0x24564236
- mww 0x50000004 0x20764316
- load_image u-boot_nand-ram256.bin 0x50008000 bin
- load_image u-boot_nand-ram256.bin 0x57E00000 bin
-
- #Kick in
- reg pc 0x57E00000
- resume
-}
-
-proc init_6410_flash {} {
- halt
- nand probe 0
- nand list
-}
-
-
-adapter_khz 1000
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-reset_config trst_and_srst
-
-gdb_breakpoint_override hard
-
-targets
-nand device $_CHIPNAME.flash s3c6400 $_CHIPNAME.cpu
-
-init
-echo " "
-echo " "
-echo "-------------------------------------------------------------------"
-echo "---- The following mini6410/tiny6410 functions are available: ----"
-echo "---- init_6410 - initialize clock, timer, DRAM ----"
-echo "---- init_6410_flash - initializes NAND flash support ----"
-echo "---- install_6410_uboot - copies u-boot image into RAM and ----"
-echo "---- runs it ----"
-echo "-------------------------------------------------------------------"
-echo " "
-echo " "
diff --git a/openocd-0.10.0/scripts/board/minispartan6.cfg b/openocd-0.10.0/scripts/board/minispartan6.cfg
deleted file mode 100644
index 3de9e99d4bc2013d7cda9904a6412b978cce2e8c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/minispartan6.cfg
+++ /dev/null
@@ -1,24 +0,0 @@
-# https://www.scarabhardware.com/minispartan6/
-
-source [find interface/ftdi/minispartan6.cfg]
-source [find cpld/xilinx-xc6s.cfg]
-source [find cpld/jtagspi.cfg]
-
-# example command to read the device dna of the FPGA on the board;
-# openocd -f board/minispartan6.cfg -c "init;xc6s_print_dna xc6s.tap;shutdown"
-
-# example command to write bitstream
-# openocd -f board/minispartan6.cfg -c "init;\
-# jtagspi_init 0 bscan_spi_xc6slx??.bit;\
-# jtagspi_program bitstream.bin 0;\
-# xc6s_program xc6s.tap;\
-# shutdown"
-#
-# jtagspi flash procies can be found in the contrib/loaders/flash/fpga/
-# directory, with prebuilt versions available at
-# https://github.com/jordens/bscan_spi_bitstreams
-#
-# For the SLX25 variant, use
-# - https://github.com/jordens/bscan_spi_bitstreams/raw/master/bscan_spi_xc6slx25.bit
-# For the SLX9 variant, use
-# - https://github.com/jordens/bscan_spi_bitstreams/raw/master/bscan_spi_xc6slx9.bit
diff --git a/openocd-0.10.0/scripts/board/nds32_xc5.cfg b/openocd-0.10.0/scripts/board/nds32_xc5.cfg
deleted file mode 100644
index 7d86996bd019f8719a2c2b8b3f661ba805fdd797..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/nds32_xc5.cfg
+++ /dev/null
@@ -1,5 +0,0 @@
-set _CPUTAPID 0x1000063d
-set _CHIPNAME nds32
-source [find target/nds32v3.cfg]
-
-jtag init
diff --git a/openocd-0.10.0/scripts/board/netgear-dg834v3.cfg b/openocd-0.10.0/scripts/board/netgear-dg834v3.cfg
deleted file mode 100644
index 48d23daf9f37575948db4023c79b7e065c5f992b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/netgear-dg834v3.cfg
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# Netgear DG834v3 Router
-# Internal 4Kb RAM (@0x80000000)
-# Flash is located at 0x90000000 (CS0) and RAM is located at 0x94000000 (CS1)
-#
-
-set partition_list {
- loader { "Bootloader (ADAM2)" 0x90000000 0x00020000 }
- firmware { "Kernel+rootfs" 0x90020000 0x003d0000 }
- config { "Bootloader config space" 0x903f0000 0x00010000 }
-}
-
-source [find target/ti-ar7.cfg]
-
-# External 16MB SDRAM - disabled as we use internal sram
-#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x00001000
-
-# External 4MB NOR Flash
-set _FLASHNAME $_CHIPNAME.norflash
-flash bank $_FLASHNAME cfi 0x90000000 0x00400000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/netgear-wg102.cfg b/openocd-0.10.0/scripts/board/netgear-wg102.cfg
deleted file mode 100644
index 232d2e4230b3c866b9af4763696dfb5e8b3112b8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/netgear-wg102.cfg
+++ /dev/null
@@ -1,35 +0,0 @@
-source [find target/atheros_ar2313.cfg]
-
-reset_config trst_and_srst
-
-$_TARGETNAME configure -event reset-init {
- mips32 cp0 12 0 0x10400000
-
- # configure sdram controller
- mww 0xb8300004 0x0e03
- sleep 100
- mww 0xb8300004 0x0e01
- mww 0xb8300008 0x10
- sleep 500
- mww 0xb8300004 0x0e02
-
- mww 0xb8300000 0x6c0088
- mww 0xb8300008 0x57e
- mww 0xb8300004 0x0e00
- mww 0xb8300004 0xb00
-
- # configure flash
- # 0x00000001 - 0x01 << FLASHCTL_IDCY_S
- # 0x000000e0 - 0x07 << FLASHCTL_WST1_S
- # FLASHCTL_RBLE 0x00000400 - Read byte lane enable
- # 0x00003800 - 0x07 << FLASHCTL_WST2_S
- # FLASHCTL_AC_8M 0x00060000 - Size of flash
- # FLASHCTL_E 0x00080000 - Flash bank enable (added)
- # FLASHCTL_WP 0x04000000 - write protect. If used, CFI mode wont work!!
- # FLASHCTL_MWx16 0x10000000 - 16bit mode. Do not use it!!
- # FLASHCTL_MWx8 0x00000000 - 8bit mode.
- mww 0xb8400000 0x000d3ce1
-}
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0xbe000000 0x00400000 1 1 $_TARGETNAME x16_as_x8
diff --git a/openocd-0.10.0/scripts/board/nordic_nrf51822_mkit.cfg b/openocd-0.10.0/scripts/board/nordic_nrf51822_mkit.cfg
deleted file mode 100644
index aa6161f5d651091f6f251307884596f9f176f4bd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/nordic_nrf51822_mkit.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Nordic Semiconductor PCA10024 board (aka nRF51822-mKIT)
-#
-
-source [find interface/cmsis-dap.cfg]
-source [find target/nrf51.cfg]
diff --git a/openocd-0.10.0/scripts/board/nordic_nrf51_dk.cfg b/openocd-0.10.0/scripts/board/nordic_nrf51_dk.cfg
deleted file mode 100644
index 96f5471a5f624c4058023c788208b7b2544aa338..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/nordic_nrf51_dk.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Nordic Semiconductor NRF51 Development Kit (nRF6824)
-#
-
-source [find interface/jlink.cfg]
-
-transport select swd
-
-source [find target/nrf51.cfg]
diff --git a/openocd-0.10.0/scripts/board/nordic_nrf52_dk.cfg b/openocd-0.10.0/scripts/board/nordic_nrf52_dk.cfg
deleted file mode 100644
index 9f528669cb3b4910541aa0c0bf4976f1c9e542c2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/nordic_nrf52_dk.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Nordic Semiconductor NRF52 Development Kit (nRF52832)
-#
-
-source [find interface/jlink.cfg]
-
-transport select swd
-
-source [find target/nrf52.cfg]
diff --git a/openocd-0.10.0/scripts/board/novena-internal-fpga.cfg b/openocd-0.10.0/scripts/board/novena-internal-fpga.cfg
deleted file mode 100644
index 87495e3729343d991eba09b0c8a1b6a966b22cf4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/novena-internal-fpga.cfg
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# Novena open hardware and F/OSS-friendly computing platform
-#
-# Design documentation:
-# http://www.kosagi.com/w/index.php?title=Novena_PVT_Design_Source
-#
-# +-------------+--------------+------+-------+---------+
-# | Pad name | Schematic | GPIO | sysfs | JTAG |
-# +-------------+--------------+------+-------+---------+
-# | DISP0_DAT13 | FPGA_RESET_N | 5-07 | 135 | RESET_N |
-# | DISP0_DAT14 | FPGA_TCK | 5-08 | 136 | TCK |
-# | DISP0_DAT15 | FPGA_TDI | 5-09 | 137 | TDI |
-# | DISP0_DAT16 | FPGA_TDO | 5-10 | 138 | TDO |
-# | DISP0_DAT17 | FPGA_TMS | 5-11 | 139 | TMS |
-# +-------------+--------------+------+-------+---------+
-
-interface sysfsgpio
-
-transport select jtag
-
-# TCK TMS TDI TDO
-sysfsgpio_jtag_nums 136 139 137 138
-
-source [find cpld/xilinx-xc6s.cfg]
-
diff --git a/openocd-0.10.0/scripts/board/numato_opsis.cfg b/openocd-0.10.0/scripts/board/numato_opsis.cfg
deleted file mode 100644
index e54a4eca8186bcdfc37de6f1da3b268b9024ed70..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/numato_opsis.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# http://opsis.hdmi2usb.tv
-#
-# The Numato Opsis is an FPGA based, open video platform.
-#
-# The board is supported via ixo-usb-jtag project. See the
-# interface/usb-jtag.cfg for more information.
-
-source [find interface/usb-jtag.cfg]
-source [find cpld/xilinx-xc6s.cfg]
-source [find cpld/jtagspi.cfg]
diff --git a/openocd-0.10.0/scripts/board/nxp_lpc-link2.cfg b/openocd-0.10.0/scripts/board/nxp_lpc-link2.cfg
deleted file mode 100644
index 593fa599a52f6788135c472f59113e91dc5d61ef..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/nxp_lpc-link2.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# NXP LPC-Link2
-#
-# http://www.nxp.com/board/OM13054.html
-# https://www.lpcware.com/lpclink2
-# http://embeddedartists.com/products/lpcxpresso/lpclink2.php
-#
-
-source [find target/lpc4370.cfg]
-
-# W25Q80BVSSIG w/ 1 MB flash
-flash bank SPIFI_FLASH lpcspifi 0x14000000 0 0 0 $_CHIPNAME.m4
diff --git a/openocd-0.10.0/scripts/board/olimex_LPC2378STK.cfg b/openocd-0.10.0/scripts/board/olimex_LPC2378STK.cfg
deleted file mode 100644
index a4b422dcc0f64f1b2f7789b197a24b2c2de325d4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/olimex_LPC2378STK.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#####################################################
-# Olimex LPC2378STK eval board
-#
-# http://olimex.com/dev/lpc-2378stk.html
-#
-# Author: Sten, debian@sansys-electronic.com
-#####################################################
-#
-
-source [find target/lpc2378.cfg]
-
diff --git a/openocd-0.10.0/scripts/board/olimex_lpc_h2148.cfg b/openocd-0.10.0/scripts/board/olimex_lpc_h2148.cfg
deleted file mode 100644
index 7833fdec69a05cb159a5eebaa452a9e718bda028..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/olimex_lpc_h2148.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Olimex LPC-H2148 eval board
-#
-# http://www.olimex.com/dev/lpc-h2148.html
-#
-
-source [find target/lpc2148.cfg]
-
diff --git a/openocd-0.10.0/scripts/board/olimex_sam7_ex256.cfg b/openocd-0.10.0/scripts/board/olimex_sam7_ex256.cfg
deleted file mode 100644
index 5f83629de35910d81706fed1cba06bdc242a2d9c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/olimex_sam7_ex256.cfg
+++ /dev/null
@@ -1,4 +0,0 @@
-# Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.
-
-source [find target/sam7x256.cfg]
-
diff --git a/openocd-0.10.0/scripts/board/olimex_sam7_la2.cfg b/openocd-0.10.0/scripts/board/olimex_sam7_la2.cfg
deleted file mode 100644
index 89d2b5a592d78a81e7f855afc7bf1a528c715b33..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/olimex_sam7_la2.cfg
+++ /dev/null
@@ -1,76 +0,0 @@
-source [find target/at91sam7a2.cfg]
-
-# delays needed to get stable reads of cpu state
-jtag_ntrst_delay 10
-adapter_nsrst_delay 200
-
-# board uses pullup and connects only srst
-reset_config srst_open_drain
-
-# srst is connected to NRESET of CPU and fully resets everything...
-reset_config srst_only srst_pulls_trst
-
-adapter_khz 1
-$_TARGETNAME configure -event reset-start {
- adapter_khz 1
-}
-
-$_TARGETNAME configure -event reset-init {
- # init script from http://www.mikrocontroller.net/topic/107462
- # AT91SAM7A2
- # AMC (advanced memory controller)
-
- echo "setting up AMC"
- # AMC_CS0 - FLASH 1MB (0x40000000-0x400FFFFF) + DM9000E (0x40100000)
- mww 0xFFE00000 0x40003EBD
-
- # AMC_CS1 - RAM low 2MB (0x40400000-0x405FFFFF)
- mww 0xFFE00004 0x404030A9
-
- # AMC_CS2 - RAM high 2MB (0x40800000-0x405FFFFF)
- #mww 0xFFE00008 0x404030A9
- # changed to 0x40_8_
- mww 0xFFE00008 0x408030A9
-
- # AMC_MCR
- mww 0xFFE00024 0x00000004
-
- # AMC_RCR force remap
- mww 0xFFE00020 0x00000001
-
- echo "set up AMC"
- sleep 100
-
- # the following base addresses from the original script did not correspond to those from datasheet
- # changed bases from 0xFF000000 to 0xFFF00000
-
- # disable watchdog, to prevent unwanted resets
- mww 0xFFFA0068 0x00000000
- echo "disabled watchdog"
-
- sleep 50
-
- # disable PLL
- mww 0xFFFEC004 0x18070004
-
- # PLL = 10 ==> Coreclock = 6Mhz*10/2 = 30 Mhz
- mww 0xFFFEC010 0x762D800A
-
- # enable PLL
- mww 0xFFFEC000 0x23050004
- echo "set up pll"
-
- sleep 100
- adapter_khz 5000
-}
-
-$_TARGETNAME arm7_9 dcc_downloads enable
-$_TARGETNAME arm7_9 fast_memory_access enable
-
-# remap: ram at 0, flash at 0x40000000, like reset-init above does
-$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1
-flash bank onboard.flash cfi 0x40000000 0x00100000 2 2 at91sam7a2.cpu
-
-# boot: ram at 0x300000, flash at 0x0, useful if board is in funny configuration
-#$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
-#flash bank onboard1.flash cfi 0x00000000 0x00100000 2 2 at91sam7a2.cpu
diff --git a/openocd-0.10.0/scripts/board/olimex_sam9_l9260.cfg b/openocd-0.10.0/scripts/board/olimex_sam9_l9260.cfg
deleted file mode 100644
index ad2f850a116dbf4d7d250dc2a1b8b673c9fdd81f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/olimex_sam9_l9260.cfg
+++ /dev/null
@@ -1,141 +0,0 @@
-################################################################################
-# Olimex SAM9-L9260 Development Board
-#
-# http://www.olimex.com/dev/sam9-L9260.html
-#
-# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
-# PMC configured for external 18.432 MHz crystal
-#
-# 32-bit SDRAM : 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks
-# 8-bit NAND Flash : 1 x Samsung K9F4G08U0M, 512M x 8Bit
-# Dataflash : 1 x Atmel AT45DB161D, 16Mbit
-#
-################################################################################
-
-source [find target/at91sam9260.cfg]
-
-# NTRST_E jumper is enabled by default, so we don't need to override the reset
-# config.
-#reset_config srst_only
-
-$_TARGETNAME configure -event reset-start {
- # At reset, CPU runs at 32.768 kHz. JTAG frequency must be 6 times slower if
- # RCLK is not supported.
- jtag_rclk 5
- halt
-
- # RSTC_MR : enable user reset, reset length is 64 slow clock cycles. MMU may
- # be enabled... use physical address.
- mww phys 0xfffffd08 0xa5000501
-}
-
-$_TARGETNAME configure -event reset-init {
- mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
-
- ##
- # Clock configuration for 99.328 MHz main clock.
- ##
- echo "Setting up clock"
- mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable main oscillator, 512 slow clock startup
- sleep 20 ;# wait 20 ms (need 15.6 ms for startup)
- mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator (18.432 MHz)
- sleep 10 ;# wait 10 ms
- mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR : 18.432 MHz / 9 * 97 = 198.656 MHz, 63 slow clock startup
- sleep 20 ;# wait 20 ms (need 1.9 ms for startup)
- mww 0xfffffc30 0x00000101 ;# PMC_MCKR : no scale on proc clock, master is proc / 2
- sleep 10 ;# wait 10 ms
- mww 0xfffffc30 0x00000102 ;# PMC_MCKR : switch to PLLA (99.328 MHz)
-
- # Increase JTAG speed to 6 MHz if RCLK is not supported.
- jtag_rclk 6000
-
- arm7_9 dcc_downloads enable ;# Enable faster DCC downloads.
-
- ##
- # SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
- ##
- echo "Configuring SDRAM"
- mww 0xfffff870 0xffff0000 ;# PIOC_ASR : select peripheral function for D15..D31
- mww 0xfffff804 0xffff0000 ;# PIOC_PDR : disable PIO function for D15..D31
-
- mww 0xffffef1c 0x00010002 ;# EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
-
- mww 0xffffea08 0x85237259 ;# SDRAMC_CR : configure SDRAM for Samsung chips
-
- mww 0xffffea00 0x1 ;# SDRAMC_MR : issue NOP command
- mww 0x20000000 0
- mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
- mww 0x20000000 0
- mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' command
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
- mww 0x20000000 0
- mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
- mww 0x20000000 0
-
- mww 0xffffea04 0x2b6 ;# SDRAMC_TR : set refresh timer count to 7 us
-
- ##
- # NAND Flash Configuration for 1 x Samsung K9F4G08U0M, 512M x 8Bit.
- ##
- echo "Configuring NAND flash"
- mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
- mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
- mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
- mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
- mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
- mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13
-
- mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before
-
- mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE
- mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals
- mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle
- mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
- # 3 TDF cycles, no optimization
-
- mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
- mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
-
- nand probe at91sam9260.flash
-
- ##
- # Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit
- ##
- echo "Setting up dataflash"
- mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI),
- # 2(SPI0_SPCK), and 11(SPI0_NPCS1)
- mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2
- mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11
- mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock
-
- mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0
- mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure
- mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected
-
- mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud,
- # 250ns delay before SPCK, 250ns b/n tx
-
- mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1
- mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0
-}
-
-nand device at91sam9260.flash at91sam9 at91sam9260.cpu 0x40000000 0xffffe800
-at91sam9 cle 0 22
-at91sam9 ale 0 21
-at91sam9 rdy_busy 0 0xfffff800 13
-at91sam9 ce 0 0xfffff800 14
diff --git a/openocd-0.10.0/scripts/board/olimex_stm32_h103.cfg b/openocd-0.10.0/scripts/board/olimex_stm32_h103.cfg
deleted file mode 100644
index ec03034c109b7204174cc990dfceedecd4eb2b3f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/olimex_stm32_h103.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-# Olimex STM32-H103 eval board
-# http://olimex.com/dev/stm32-h103.html
-
-# Work-area size (RAM size) = 20kB for STM32F103RB device
-set WORKAREASIZE 0x5000
-
-source [find target/stm32f1x.cfg]
diff --git a/openocd-0.10.0/scripts/board/olimex_stm32_h107.cfg b/openocd-0.10.0/scripts/board/olimex_stm32_h107.cfg
deleted file mode 100644
index e54fb4e707ffbd0ea943c78ff3c70ec84320ad87..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/olimex_stm32_h107.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Olimex STM32-H107
-#
-# http://olimex.com/dev/stm32-h107.html
-#
-
-# Work-area size (RAM size) = 64kB for STM32F107VC device
-set WORKAREASIZE 0x10000
-
-source [find target/stm32f1x.cfg]
diff --git a/openocd-0.10.0/scripts/board/olimex_stm32_p107.cfg b/openocd-0.10.0/scripts/board/olimex_stm32_p107.cfg
deleted file mode 100644
index 98c72a6e7ebfd065ef960afab282e9d09a67e5ef..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/olimex_stm32_p107.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Olimex STM32-P107
-#
-# http://olimex.com/dev/stm32-p107.html
-#
-
-# Work-area size (RAM size) = 64kB for STM32F107VC device
-set WORKAREASIZE 0x10000
-
-source [find target/stm32f1x.cfg]
diff --git a/openocd-0.10.0/scripts/board/omap2420_h4.cfg b/openocd-0.10.0/scripts/board/omap2420_h4.cfg
deleted file mode 100644
index d789e25313aa63a5f1493c41a0fca923caa0e0e8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/omap2420_h4.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-# OMAP2420 SDP board ("H4")
-
-source [find target/omap2420.cfg]
-
-# NOTE: this assumes you're *NOT* using a TI-14 connector.
-reset_config trst_and_srst separate
-
-# Board configs can vary a *LOT* ... parts, jumpers, etc.
-# This GP board boots from cs0 using NOR (2x32M), and also
-# has 64M NAND on cs6.
-flash bank h4.u10 cfi 0x04000000 0x02000000 2 2 $_TARGETNAME
-flash bank h4.u11 cfi 0x06000000 0x02000000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/open-bldc.cfg b/openocd-0.10.0/scripts/board/open-bldc.cfg
deleted file mode 100644
index da8654c8d56e467803e7537ea70e49681fb0d5f2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/open-bldc.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-# Open Source Brush Less DC Motor Controller
-# http://open-bldc.org
-
-# Work-area size (RAM size) = 20kB for STM32F103RB device
-set WORKAREASIZE 0x5000
-
-source [find target/stm32.cfg]
diff --git a/openocd-0.10.0/scripts/board/openrd.cfg b/openocd-0.10.0/scripts/board/openrd.cfg
deleted file mode 100644
index 1051c25d95e66f31620149f5925a2652b3ce6195..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/openrd.cfg
+++ /dev/null
@@ -1,123 +0,0 @@
-# Marvell OpenRD
-
-source [find interface/ftdi/openrd.cfg]
-source [find target/feroceon.cfg]
-
-$_TARGETNAME configure \
- -work-area-phys 0x10000000 \
- -work-area-size 65536 \
- -work-area-backup 0
-
-arm7_9 dcc_downloads enable
-
-# this assumes the hardware default peripherals location before u-Boot moves it
-set _FLASHNAME $_CHIPNAME.flash
-nand device $_FLASHNAME orion 0 0xd8000000
-
-proc openrd_init { } {
-
- # We need to assert DBGRQ while holding nSRST down.
- # However DBGACK will be set only when nSRST is released.
- # Furthermore, the JTAG interface doesn't respond at all when
- # the CPU is in the WFI (wait for interrupts) state, so it is
- # possible that initial tap examination failed. So let's
- # re-examine the target again here when nSRST is asserted which
- # should then succeed.
- jtag_reset 0 1
- feroceon.cpu arp_examine
- halt 0
- jtag_reset 0 0
- wait_halt
-
- arm mcr 15 0 0 1 0 0x00052078
-
- mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
- mww 0xD0001404 0x37543000 ;# Dunit Control Low Register
- mww 0xD0001408 0x22125451 ;# DDR SDRAM Timing (Low) Register
- mww 0xD000140C 0x00000A33 ;# DDR SDRAM Timing (High) Register
- mww 0xD0001410 0x000000CC ;# DDR SDRAM Address Control Register
- mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
- mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
- mww 0xD000141C 0x00000C52 ;# DDR SDRAM Mode Register
- mww 0xD0001420 0x00000004 ;# DDR SDRAM Extended Mode Register
- mww 0xD0001424 0x0000F17F ;# Dunit Control High Register
- mww 0xD0001428 0x00085520 ;# Dunit Control High Register
- mww 0xD000147c 0x00008552 ;# Dunit Control High Register
- mww 0xD0001504 0x0FFFFFF1 ;# CS0n Size Register
- mww 0xD0001508 0x10000000 ;# CS1n Base Register
- mww 0xD000150C 0x0FFFFFF5 ;# CS1n Size Register
- mww 0xD0001514 0x00000000 ;# CS2n Size Register
- mww 0xD000151C 0x00000000 ;# CS3n Size Register
- mww 0xD0001494 0x00120012 ;# DDR2 SDRAM ODT Control (Low) Register
- mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
- mww 0xD000149C 0x0000E40F ;# DDR2 Dunit ODT Control Register
- mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register
- mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
-
- mww 0xD0010000 0x01111111 ;# MPP 0 to 7
- mww 0xD0010004 0x11113322 ;# MPP 8 to 15
- mww 0xD0010008 0x00001111 ;# MPP 16 to 23
-
- mww 0xD0010418 0x003E07CF ;# NAND Read Parameters REgister
- mww 0xD001041C 0x000F0F0F ;# NAND Write Parameters Register
- mww 0xD0010470 0x01C7D943 ;# NAND Flash Control Register
-
-}
-
-proc openrd_reflash_uboot { } {
-
- # reflash the u-Boot binary and reboot into it
- openrd_init
- nand probe 0
- nand erase 0 0x0 0xa0000
- nand write 0 uboot.bin 0 oob_softecc_kw
- resume
-
-}
-
-proc openrd_load_uboot { } {
-
- # load u-Boot into RAM and execute it
- openrd_init
- load_image uboot.elf
- verify_image uboot.elf
- resume 0x00600000
-
-}
-
diff --git a/openocd-0.10.0/scripts/board/or1k_generic.cfg b/openocd-0.10.0/scripts/board/or1k_generic.cfg
deleted file mode 100644
index c543ebe25e02c21181139a2cf0944fc5899cdf94..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/or1k_generic.cfg
+++ /dev/null
@@ -1,51 +0,0 @@
-# If you want to use the VJTAG TAP or the XILINX BSCAN,
-# you must set your FPGA TAP ID here
-
-set FPGATAPID 0x020b30dd
-
-# Choose your TAP core (VJTAG , MOHOR or XILINX_BSCAN)
-if { [info exists TAP_TYPE] == 0} {
- set TAP_TYPE VJTAG
-}
-
-# Set your chip name
-set CHIPNAME or1200
-
-source [find target/or1k.cfg]
-
-# Set the servers polling period to 1ms (needed to JSP Server)
-poll_period 1
-
-# Set the adapter speed
-adapter_khz 3000
-
-# Enable the target description feature
-gdb_target_description enable
-
-# Add a new register in the cpu register list. This register will be
-# included in the generated target descriptor file.
-# format is addreg [name] [address] [feature] [reg_group]
-addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
-
-# Override default init_reset
-proc init_reset {mode} {
- soft_reset_halt
- resume
-}
-
-# Target initialization
-init
-echo "Halting processor"
-halt
-
-foreach name [target names] {
- set y [$name cget -endian]
- set z [$name cget -type]
- puts [format "Chip is %s, Endian: %s, type: %s" \
- $name $y $z]
-}
-
-set c_blue "\033\[01;34m"
-set c_reset "\033\[0m"
-
-puts [format "%sTarget ready...%s" $c_blue $c_reset]
diff --git a/openocd-0.10.0/scripts/board/osk5912.cfg b/openocd-0.10.0/scripts/board/osk5912.cfg
deleted file mode 100644
index f4378f8cfed5316fd26d14345dcb2f29302c7367..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/osk5912.cfg
+++ /dev/null
@@ -1,34 +0,0 @@
-# http://omap.spectrumdigital.com/osk5912/
-
-source [find target/omap5912.cfg]
-
-# NOTE: this assumes you're using the ARM 20-pin ("Multi-ICE")
-# JTAG connector, and accordingly have J1 connecting pins 1 & 2.
-# The TI-14 pin needs "trst_only", and J1 connecting 2 & 3.
-reset_config trst_and_srst separate
-
-# NOTE: boards with XOMAP parts wire nSRST to nPWRON_RESET.
-# That resets everything -- including JTAG and EmbeddedICE.
-# So they must use "reset_config srst_pulls_trst".
-
-# NOTE: an expansion board could add a trace connector ... if
-# it does, change this appropriately. And reset_config too,
-# assuming JTAG_DIS reroutes JTAG to that connector.
-etm config $_TARGETNAME 8 demultiplexed full dummy
-etm_dummy config $_TARGETNAME
-
-# standard boards populate two 16 MB chips, but manufacturing
-# options or an expansion board could change this config.
-flash bank osk.u1 cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
-flash bank osk.u2 cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
-
-proc osk5912_init {} {
- omap5912_reset
-
- # detect flash
- flash probe 0
- flash probe 1
-}
-$_TARGETNAME configure -event reset-init { osk5912_init }
-
-arm7_9 dcc_downloads enable
diff --git a/openocd-0.10.0/scripts/board/phone_se_j100i.cfg b/openocd-0.10.0/scripts/board/phone_se_j100i.cfg
deleted file mode 100644
index 6326590273b8ae8fc1a165f27cf6a2042233d622..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/phone_se_j100i.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Sony Ericsson J100I Phone
-#
-# more informations can be found on
-# http://bb.osmocom.org/trac/wiki/SonyEricssonJ100i
-#
-source [find target/ti_calypso.cfg]
-
-# external flash
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x00000000 0x400000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/phytec_lpc3250.cfg b/openocd-0.10.0/scripts/board/phytec_lpc3250.cfg
deleted file mode 100644
index 6a7e8e923b7c442daa74a14dcf0569c8d7352cb3..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/phytec_lpc3250.cfg
+++ /dev/null
@@ -1,88 +0,0 @@
-source [find target/lpc3250.cfg]
-
-adapter_nsrst_delay 200
-jtag_ntrst_delay 1
-adapter_khz 200
-reset_config trst_and_srst separate
-
-arm7_9 dcc_downloads enable
-
-$_TARGETNAME configure -event gdb-attach { reset init }
-
-$_TARGETNAME configure -event reset-start {
- arm7_9 fast_memory_access disable
- adapter_khz 200
-}
-
-$_TARGETNAME configure -event reset-end {
- adapter_khz 6000
- arm7_9 fast_memory_access enable
-}
-
-$_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
-
-# Bare-bones initialization of core clocks and SDRAM
-proc phytec_lpc3250_init { } {
- # Set clock dividers
- # ARMCLK = 266.5 MHz
- # HCLK = 133.25 MHz
- # PERIPHCLK = 13.325 MHz
- mww 0x400040BC 0
- mww 0x40004050 0x140
- mww 0x40004040 0x4D
- mww 0x40004058 0x16250
-
- # Init PLLs
- mww 0x40004044 0x006
- sleep 1 busy
- mww 0x40004044 0x106
- sleep 1 busy
- mww 0x40004044 0x006
- sleep 1 busy
- mww 0x40004048 0x2
-
- # Init SDRAM with 133 MHz timings
- mww 0x40028134 0x00FFFFFF
- mww 0x4002802C 0x00000008
-
- mww 0x31080000 1
- mww 0x31080008 0
- mww 0x40004068 0x1C000
- mww 0x31080028 0x11
-
- mww 0x31080400 0
- mww 0x31080440 0
- mww 0x31080460 0
- mww 0x31080480 0
-
- # Delays
- mww 0x31080030 1
- mww 0x31080034 6
- mww 0x31080038 10
- mww 0x31080044 1
- mww 0x31080048 9
- mww 0x3108004C 12
- mww 0x31080050 10
- mww 0x31080054 1
- mww 0x31080058 1
- mww 0x3108005C 0
-
- mww 0x31080100 0x5680
- mww 0x31080104 0x302
-
- # Init sequence
- mww 0x31080020 0x193
- sleep 1 busy
- mww 0x31080024 1
- mww 0x31080020 0x113
- sleep 1 busy
- mww 0x31080020 0x013
- sleep 1 busy
- mww 0x31080024 65
- mww 0x31080020 0x093
- mdw 0x80020000
- mww 0x31080020 0x013
-
- # SYS_CTRL remapping
- mww 0x40004014 1
-}
diff --git a/openocd-0.10.0/scripts/board/pic-p32mx.cfg b/openocd-0.10.0/scripts/board/pic-p32mx.cfg
deleted file mode 100644
index 661e3d63f420a27766b55805bd8400ae15035129..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/pic-p32mx.cfg
+++ /dev/null
@@ -1,4 +0,0 @@
-# The Olimex PIC-P32MX has a PIC32MX
-
-set CPUTAPID 0x40916053
-source [find target/pic32mx.cfg]
diff --git a/openocd-0.10.0/scripts/board/pipistrello.cfg b/openocd-0.10.0/scripts/board/pipistrello.cfg
deleted file mode 100644
index 87193b4a1ea939cb65186732511b25d85ea87182..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/pipistrello.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-# http://pipistrello.saanlima.com/
-
-source [find interface/ftdi/pipistrello.cfg]
-source [find cpld/xilinx-xc6s.cfg]
-source [find cpld/jtagspi.cfg]
-
-# example command to write bitstream, soft-cpu bios and runtime:
-# openocd -f board/pipistrello.cfg -c "init;\
-# jtagspi_init 0 bscan_spi_xc6slx45.bit;\
-# jtagspi_program bitstream-pistrello.bin 0;\
-# jtagspi_program bios.bin 0x170000;\
-# jtagspi_program runtime.fbi 0x180000;\
-# xc6s_program xc6s.tap;\
-# exit"
diff --git a/openocd-0.10.0/scripts/board/propox_mmnet1001.cfg b/openocd-0.10.0/scripts/board/propox_mmnet1001.cfg
deleted file mode 100644
index 39ae5cbc1e2ab503213e029aef638b332b8c7b86..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/propox_mmnet1001.cfg
+++ /dev/null
@@ -1,83 +0,0 @@
-
-## Chip:
-set CHIPNAME at91sam9260
-set CPUTAPID 0x0792603f
-set ENDIAN little
-source [find target/at91sam9260.cfg]
-
-$_TARGETNAME configure -event reset-init {at91sam_init}
-
-
-proc at91sam_init { } {
-
- # at reset chip runs at 32 kHz => 1/8 * 32 kHz = 4 kHz
- jtag_rclk 4
-
- # Enable user reset and disable watchdog
- mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset
- mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
-
- # Oscillator setup
- mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator (18.432 MHz)
- sleep 20 ;# wait 20 ms
- mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
- sleep 10 ;# wait 10 ms
-
- # now we are running at 18.432 MHz kHz => 1/8 * 18.432 MHz = 2.304 MHz
- jtag_rclk 2000
-
- mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
- sleep 20 ;# wait 20 ms
- mww 0xfffffc2c 0x207c3f0c ;# CKGR_PLLBR: Set PLLB Register for USB usage (USB_CLK = 48 MHz)
- sleep 10 ;# wait 10 ms
- mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler
- sleep 10 ;# wait 10 ms
- mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected
- sleep 10 ;# wait 10 ms
-
- # now we are running at 198.656 MHz kHz => full speed jtag
- jtag_rclk 30000
-
- arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
-
- # Configure PIO Controller for SDRAM data-lines D16-D31
- # PC16-PC31 = Peripheral A: D16-D32
- mww 0xfffff844 0xffff0000 ;# Interrupt Disable
- mww 0xfffff854 0xffff0000 ;# Multi-Drive Disable
- mww 0xfffff860 0xffff0000 ;# Pull-Up Disable
- mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral A function for D15..D31
- mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31 (Peripheral function enable)
- mww 0xfffffc10 0x00000010 ;# Enable PIO-C Clock in PMC (PID=4)
-
- # SD-Ram setup
- mww 0xffffef1c 0x2 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
- mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (IS42S32160A: 4M Words x 32 Bits x 4 Banks (512-Mbit))
- mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
- mww 0x20000000 0
- mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
- mww 0x20000000 0
- mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (1st)
- mww 0x20000000 0
- mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (2nd)
- mww 0x20000000 0
- mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (3th)
- mww 0x20000000 0
- mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (4th)
- mww 0x20000000 0
- mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (5th)
- mww 0x20000000 0
- mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (6th)
- mww 0x20000000 0
- mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (7th)
- mww 0x20000000 0
- mww 0xffffea00 0x4 ;# SDRAMC_MR : issue an 'Auto-Refresh' command (8th)
- mww 0x20000000 0
- mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
- mww 0x20000000 0
- mww 0xffffea00 0x0 ;# SDRAMC_MR : Normal Mode
- mww 0x20000000 0
- mww 0xFFFFEA04 0x30d ;# SDRAM Refresh Time Register
- # datasheet: 8k refresh cycles / 64 ms
- # MCLK / (8*1024 / 64e-3) = 100e6 / 128000 = 781 = 0x30d
-
-}
diff --git a/openocd-0.10.0/scripts/board/pxa255_sst.cfg b/openocd-0.10.0/scripts/board/pxa255_sst.cfg
deleted file mode 100644
index 49cad5db74d281469803928175b3744f8c5ef3f4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/pxa255_sst.cfg
+++ /dev/null
@@ -1,99 +0,0 @@
-# A PXA255 test board with SST 39LF400A flash
-#
-# At reset the memory map is as follows. Note that
-# the memory map changes later on as the application
-# starts...
-#
-# RAM at 0x4000000
-# Flash at 0x00000000
-#
-source [find target/pxa255.cfg]
-
-# Target name is set by above
-$_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
-
-# flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
-
-proc pxa255_sst_init {} {
- xscale cp15 15 0x00002001 ;#Enable CP0 and CP13 access
- #
- # setup GPIO
- #
- mww 0x40E00018 0x00008000 ;#CPSR0
- sleep 20
- mww 0x40E0001C 0x00000002 ;#GPSR1
- sleep 20
- mww 0x40E00020 0x00000008 ;#GPSR2
- sleep 20
- mww 0x40E0000C 0x00008000 ;#GPDR0
- sleep 20
- mww 0x40E00054 0x80000000 ;#GAFR0_L
- sleep 20
- mww 0x40E00058 0x00188010 ;#GAFR0_H
- sleep 20
- mww 0x40E0005C 0x60908018 ;#GAFR1_L
- sleep 20
- mww 0x40E0000C 0x0280E000 ;#GPDR0
- sleep 20
- mww 0x40E00010 0x821C88B2 ;#GPDR1
- sleep 20
- mww 0x40E00014 0x000F03DB ;#GPDR2
- sleep 20
- mww 0x40E00000 0x000F03DB ;#GPLR0
- sleep 20
-
-
- mww 0x40F00004 0x00000020 ;#PSSR
- sleep 20
-
- #
- # setup memory controller
- #
- mww 0x48000008 0x01111998 ;#MSC0
- sleep 20
- mww 0x48000010 0x00047ff0 ;#MSC2
- sleep 20
- mww 0x48000014 0x00000000 ;#MECR
- sleep 20
- mww 0x48000028 0x00010504 ;#MCMEM0
- sleep 20
- mww 0x4800002C 0x00010504 ;#MCMEM1
- sleep 20
- mww 0x48000030 0x00010504 ;#MCATT0
- sleep 20
- mww 0x48000034 0x00010504 ;#MCATT1
- sleep 20
- mww 0x48000038 0x00004715 ;#MCIO0
- sleep 20
- mww 0x4800003C 0x00004715 ;#MCIO1
- sleep 20
- #
- mww 0x48000004 0x03CA4018 ;#MDREF
- sleep 20
- mww 0x48000004 0x004B4018 ;#MDREF
- sleep 20
- mww 0x48000004 0x000B4018 ;#MDREF
- sleep 20
- mww 0x48000004 0x000BC018 ;#MDREF
- sleep 20
- mww 0x48000000 0x00001AC8 ;#MDCNFG
- sleep 20
-
- sleep 20
-
- mww 0x48000000 0x00001AC9 ;#MDCNFG
- sleep 20
- mww 0x48000040 0x00000000 ;#MDMRS
- sleep 20
-}
-
-$_TARGETNAME configure -event reset-init {pxa255_sst_init}
-
-reset_config trst_and_srst
-
-adapter_nsrst_delay 200
-jtag_ntrst_delay 200
-
-#xscale debug_handler 0 0xFFFF0800 ;# debug handler base address
diff --git a/openocd-0.10.0/scripts/board/quark_d2000_refboard.cfg b/openocd-0.10.0/scripts/board/quark_d2000_refboard.cfg
deleted file mode 100644
index d1388bbaaaa43e6a470eab9f4f6ebc8fa5c82985..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/quark_d2000_refboard.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-# Intel Quark microcontroller D2000 Reference Board (web search for doc num 333582)
-
-# the board has an onboard FTDI FT232H chip
-interface ftdi
-ftdi_vid_pid 0x0403 0x6014
-ftdi_channel 0
-
-ftdi_layout_init 0x0000 0x030b
-ftdi_layout_signal nTRST -data 0x0100 -noe 0x0100
-
-source [find target/quark_d20xx.cfg]
-
-adapter_khz 1000
-
-reset_config trst_only
diff --git a/openocd-0.10.0/scripts/board/quark_x10xx_board.cfg b/openocd-0.10.0/scripts/board/quark_x10xx_board.cfg
deleted file mode 100644
index 8dc600b804d386215990e7f42cbf3e756e6d7513..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/quark_x10xx_board.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-# There are many Quark boards that can host the quark_x10xx SoC
-# Galileo is an example board
-
-source [find target/quark_x10xx.cfg]
-
-#default frequency but this can be adjusted at runtime
-adapter_khz 4000
-
-reset_config trst_only
diff --git a/openocd-0.10.0/scripts/board/redbee.cfg b/openocd-0.10.0/scripts/board/redbee.cfg
deleted file mode 100644
index 046e7a478bb90e07ff0b15ef4acadd74f259139d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/redbee.cfg
+++ /dev/null
@@ -1 +0,0 @@
-source [find target/mc13224v.cfg]
diff --git a/openocd-0.10.0/scripts/board/renesas_dk-s7g2.cfg b/openocd-0.10.0/scripts/board/renesas_dk-s7g2.cfg
deleted file mode 100644
index 3f29ec3ae97e1ec063cace7382549af89b1f1631..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/renesas_dk-s7g2.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Renesas Synergy DK-S7G2
-#
-
-source [find interface/jlink.cfg]
-transport select swd
-
-# XXX 19-pin SWD+TRACE connector also available
-
-# Synergy R7FS7G27H2A01CBD
-source [find target/renesas_s7g2.cfg]
-
-# 32 MB QSPI flash (Micron N25Q256A13EF840E)
diff --git a/openocd-0.10.0/scripts/board/rsc-w910.cfg b/openocd-0.10.0/scripts/board/rsc-w910.cfg
deleted file mode 100644
index 636a05399d0e7ccaba93993620bfb5ca51aa07dc..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/rsc-w910.cfg
+++ /dev/null
@@ -1,66 +0,0 @@
-# Avalue RSC-W8910 sbc
-# http://www.avalue.com.tw/products/RSC-W910.cfm
-# 2MB NOR Flash
-# 64MB SDRAM
-# 128MB NAND Flash
-
-# Based on Nuvoton nuc910
-source [find target/nuc910.cfg]
-
-#
-# reset only behaves correctly if we use srst_pulls_trst
-#
-reset_config trst_and_srst srst_pulls_trst
-
-adapter_khz 1000
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
-$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x04000000 -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x20000000 0x00200000 2 2 $_TARGETNAME
-
-set _NANDNAME $_CHIPNAME.nand
-nand device $_NANDNAME nuc910 $_TARGETNAME
-
-#
-# Target events
-#
-
-$_TARGETNAME configure -event reset-start {adapter_khz 1000}
-
-$_TARGETNAME configure -event reset-init {
- # switch on PLL for 200MHz operation
- # running from 15MHz input clock
-
- mww 0xB0000200 0x00000030 ;# CLKEN
- mww 0xB0000204 0x00000f3c ;# CLKSEL
- mww 0xB0000208 0x05007000 ;# CLKDIV
- mww 0xB000020C 0x00004f24 ;# PLLCON0
- mww 0xB0000210 0x00002b63 ;# PLLCON1
- mww 0xB000000C 0x08817fa6 ;# MFSEL
- sleep 10
-
- # we are now running @ 200MHz
- # enable all openocd speed tweaks
-
- arm7_9 dcc_downloads enable
- arm7_9 fast_memory_access enable
- adapter_khz 15000
-
- # map nor flash to 0x20000000
- # map sdram to 0x00000000
-
- mww 0xb0001000 0x000530c1 ;# EBICON
- mww 0xb0001004 0x40030084 ;# ROMCON
- mww 0xb0001008 0x000010ee ;# SDCONF0
- mww 0xb000100C 0x00000000 ;# SDCONF1
- mww 0xb0001010 0x0000015b ;# SDTIME0
- mww 0xb0001014 0x0000015b ;# SDTIME1
- mww 0xb0001018 0x00000000 ;# EXT0CON
- mww 0xb000101C 0x00000000 ;# EXT1CON
- mww 0xb0001020 0x00000000 ;# EXT2CON
- mww 0xb0001024 0x00000000 ;# EXT3CON
- mww 0xb000102c 0x00ff0048 ;# CKSKEW
-}
diff --git a/openocd-0.10.0/scripts/board/sheevaplug.cfg b/openocd-0.10.0/scripts/board/sheevaplug.cfg
deleted file mode 100644
index ff333ca77f9fb30f02cf3649b5913955b915af7c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/sheevaplug.cfg
+++ /dev/null
@@ -1,136 +0,0 @@
-# Marvell SheevaPlug
-
-source [find interface/ftdi/sheevaplug.cfg]
-source [find target/feroceon.cfg]
-
-adapter_khz 2000
-
-$_TARGETNAME configure \
- -work-area-phys 0x10000000 \
- -work-area-size 65536 \
- -work-area-backup 0
-
-arm7_9 dcc_downloads enable
-
-# this assumes the hardware default peripherals location before u-Boot moves it
-set _FLASHNAME $_CHIPNAME.flash
-nand device $_FLASHNAME orion 0 0xd8000000
-
-proc sheevaplug_init { } {
-
- # We need to assert DBGRQ while holding nSRST down.
- # However DBGACK will be set only when nSRST is released.
- # Furthermore, the JTAG interface doesn't respond at all when
- # the CPU is in the WFI (wait for interrupts) state, so it is
- # possible that initial tap examination failed. So let's
- # re-examine the target again here when nSRST is asserted which
- # should then succeed.
- jtag_reset 0 1
- feroceon.cpu arp_examine
- halt 0
- jtag_reset 0 0
- wait_halt
-
- arm mcr 15 0 0 1 0 0x00052078
-
- mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
- mww 0xD0001404 0x39543000 ;# Dunit Control Low Register
- mww 0xD0001408 0x22125451 ;# DDR SDRAM Timing (Low) Register
- mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
- mww 0xD0001410 0x000000CC ;# DDR SDRAM Address Control Register
- mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
- mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
- mww 0xD000141C 0x00000C52 ;# DDR SDRAM Mode Register
- mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
- mww 0xD0001424 0x0000F17F ;# Dunit Control High Register
- mww 0xD0001428 0x00085520 ;# Dunit Control High Register
- mww 0xD000147c 0x00008552 ;# Dunit Control High Register
- mww 0xD0001504 0x0FFFFFF1 ;# CS0n Size Register
- mww 0xD0001508 0x10000000 ;# CS1n Base Register
- mww 0xD000150C 0x0FFFFFF5 ;# CS1n Size Register
- mww 0xD0001514 0x00000000 ;# CS2n Size Register
- mww 0xD000151C 0x00000000 ;# CS3n Size Register
- mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
- mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
- mww 0xD000149C 0x0000F80F ;# DDR2 Dunit ODT Control Register
- mww 0xD0001480 0x00000001 ;# DDR SDRAM Initialization Control Register
- mww 0xD0020204 0x00000000 ;# Main IRQ Interrupt Mask Register
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
- mww 0xD0020204 0x00000000 ;# "
-
- mww 0xD0010000 0x01111111 ;# MPP 0 to 7
- mww 0xD0010004 0x11113322 ;# MPP 8 to 15
- mww 0xD0010008 0x00001111 ;# MPP 16 to 23
-
- mww 0xD0010418 0x003E07CF ;# NAND Read Parameters REgister
- mww 0xD001041C 0x000F0F0F ;# NAND Write Parameters Register
- mww 0xD0010470 0x01C7D943 ;# NAND Flash Control Register
-
-}
-
-proc sheevaplug_reflash_uboot { } {
-
- # reflash the u-Boot binary and reboot into it
- sheevaplug_init
- nand probe 0
- nand erase 0 0x0 0xa0000
- nand write 0 uboot.bin 0 oob_softecc_kw
- resume
-
-}
-
-proc sheevaplug_reflash_uboot_env { } {
-
- # reflash the u-Boot environment variables area
- sheevaplug_init
- nand probe 0
- nand erase 0 0xa0000 0x40000
- nand write 0 uboot-env.bin 0xa0000 oob_softecc_kw
- resume
-
-}
-
-proc sheevaplug_load_uboot { } {
-
- # load u-Boot into RAM and execute it
- sheevaplug_init
- load_image uboot.elf
- verify_image uboot.elf
- resume 0x00600000
-
-}
-
diff --git a/openocd-0.10.0/scripts/board/smdk6410.cfg b/openocd-0.10.0/scripts/board/smdk6410.cfg
deleted file mode 100644
index dd8bf87ad71ef15abf0c945ec94e526b1e0075fa..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/smdk6410.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-# Target configuration for the Samsung s3c6410 system on chip
-# Tested on a SMDK6410
-# Processor : ARM1176
-# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
-
-source [find target/samsung_s3c6410.cfg]
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x00000000 0x00100000 2 2 $_TARGETNAME jedec_probe
diff --git a/openocd-0.10.0/scripts/board/spansion_sk-fm4-176l-s6e2cc.cfg b/openocd-0.10.0/scripts/board/spansion_sk-fm4-176l-s6e2cc.cfg
deleted file mode 100644
index 2855c5d41f73aa4b44821eedc82d5a807caf83ce..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/spansion_sk-fm4-176l-s6e2cc.cfg
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# Spansion SK-FM4-176L-S6E2CC
-#
-
-#
-# FM3 MB9AF312K
-#
-source [find interface/cmsis-dap.cfg]
-
-# There's also an unpopulated 10-pin 0.05" pinout.
-
-#
-# FM4 S6E2CCAJ0A w/ 192 KB SRAM0
-#
-set CHIPNAME s6e2cc
-set CHIPSERIES S6E2CCAJ0A
-set WORKAREASIZE 0x30000
-source [find target/fm4_s6e2cc.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/spansion_sk-fm4-u120-9b560.cfg b/openocd-0.10.0/scripts/board/spansion_sk-fm4-u120-9b560.cfg
deleted file mode 100644
index 38ad4a8831f4f3f65ca7a6adda0ae00eb829b4c0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/spansion_sk-fm4-u120-9b560.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Spansion SK-FM4-U120-9B560
-#
-
-#
-# FM3 MB9AF312K
-#
-# source [find interface/cmsis-dap.cfg]
-
-#
-# FM4 MB9BF568R w/ 64 KB SRAM0
-#
-set CHIPNAME mb9bf568
-set CHIPSERIES MB9BF568R
-set WORKAREASIZE 0x10000
-source [find target/fm4_mb9bf.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/spear300evb.cfg b/openocd-0.10.0/scripts/board/spear300evb.cfg
deleted file mode 100644
index 9f957038d3245ac5bcc446071e82815d34a626e6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/spear300evb.cfg
+++ /dev/null
@@ -1,44 +0,0 @@
-# Configuration for the ST SPEAr300 Evaluation board
-# EVALSPEAr300 Rev. 1.0
-# http://www.st.com/spear
-#
-# Date: 2010-11-27
-# Author: Antonio Borneo <borneo.antonio@gmail.com>
-
-# The standard board has JTAG SRST not connected.
-# This script targets such boards using quirky code to bypass the issue.
-
-
-source [find mem_helper.tcl]
-source [find target/spear3xx.cfg]
-source [find chip/st/spear/spear3xx_ddr.tcl]
-source [find chip/st/spear/spear3xx.tcl]
-
-arm7_9 dcc_downloads enable
-arm7_9 fast_memory_access enable
-
-
-# Serial NOR on SMI CS0. 8Mbyte.
-set _FLASHNAME1 $_CHIPNAME.snor
-flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
-
-if { [info exists BOARD_HAS_SRST] } {
- # Modified board has SRST on JTAG connector
- reset_config trst_and_srst separate srst_gates_jtag \
- trst_push_pull srst_open_drain
-} else {
- # Standard board has no SRST on JTAG connector
- reset_config trst_only separate srst_gates_jtag trst_push_pull
- source [find chip/st/spear/quirk_no_srst.tcl]
-}
-
-$_TARGETNAME configure -event reset-init { spear300evb_init }
-
-proc spear300evb_init {} {
- reg pc 0xffff0020; # loop forever
-
- sp3xx_clock_default
- sp3xx_common_init
- sp3xx_ddr_init "mt47h64m16_3_333_cl5_async"
- sp300_init
-}
diff --git a/openocd-0.10.0/scripts/board/spear300evb_mod.cfg b/openocd-0.10.0/scripts/board/spear300evb_mod.cfg
deleted file mode 100644
index 91cad5f199917210dc5793a564f9ea12d1351529..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/spear300evb_mod.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-# Configuration for the ST SPEAr300 Evaluation board
-# EVALSPEAr300 Rev. 1.0, modified to enable SRST on JTAG connector
-# http://www.st.com/spear
-#
-# List of board modifications to enable SRST, as reported in
-# ST Application Note (FIXME: add reference).
-# - Modifications on the top layer:
-# 1. replace reset chip U4 with a STM6315SDW13F;
-# - Modifications on the bottom layer:
-# 2. add 0 ohm resistor R10. It is located close to JTAG connector.
-# 3. add a 10K ohm pull-up resistor on the reset wire named as
-# POWERGOOD in the schematic.
-#
-# The easier way to do modification 3, is to use a resistor in package
-# 0603 and solder it between R10 and R54:
-# - one pad soldered with the pad of R54 connected to 3.3V (this
-# is the pad of R54 far from JTAG connector J4)
-# - the other pad soldered with the nearest pad of R10.
-#
-# Date: 2011-11-18
-# Author: Antonio Borneo <borneo.antonio@gmail.com>
-
-
-# Modified boards has SRST on JTAG connector
-set BOARD_HAS_SRST 1
-source [find board/spear300evb.cfg]
diff --git a/openocd-0.10.0/scripts/board/spear310evb20.cfg b/openocd-0.10.0/scripts/board/spear310evb20.cfg
deleted file mode 100644
index c45873ca9923ef724988a5cfe8a1ac3091d39052..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/spear310evb20.cfg
+++ /dev/null
@@ -1,51 +0,0 @@
-# Configuration for the ST SPEAr310 Evaluation board
-# EVALSPEAr310 Rev. 2.0
-# http://www.st.com/spear
-#
-# Date: 2010-08-17
-# Author: Antonio Borneo <borneo.antonio@gmail.com>
-
-# The standard board has JTAG SRST not connected.
-# This script targets such boards using quirky code to bypass the issue.
-#
-# Check ST Application Note AN3321 on how to fix SRST on
-# the board, then use the script board/spear310evb20_mod.cfg
-
-
-source [find mem_helper.tcl]
-source [find target/spear3xx.cfg]
-source [find chip/st/spear/spear3xx_ddr.tcl]
-source [find chip/st/spear/spear3xx.tcl]
-
-arm7_9 dcc_downloads enable
-arm7_9 fast_memory_access enable
-
-# CFI parallel NOR on EMI CS0. 2x 16bit 8M devices = 16Mbyte.
-set _FLASHNAME0 $_CHIPNAME.pnor
-flash bank $_FLASHNAME0 cfi 0x50000000 0x01000000 2 4 $_TARGETNAME
-
-# Serial NOR on SMI CS0. 8Mbyte.
-set _FLASHNAME1 $_CHIPNAME.snor
-flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
-
-if { [info exists BOARD_HAS_SRST] } {
- # Modified board has SRST on JTAG connector
- reset_config trst_and_srst separate srst_gates_jtag \
- trst_push_pull srst_open_drain
-} else {
- # Standard board has no SRST on JTAG connector
- reset_config trst_only separate srst_gates_jtag trst_push_pull
- source [find chip/st/spear/quirk_no_srst.tcl]
-}
-
-$_TARGETNAME configure -event reset-init { spear310evb20_init }
-
-proc spear310evb20_init {} {
- reg pc 0xffff0020 ;# loop forever
-
- sp3xx_clock_default
- sp3xx_common_init
- sp3xx_ddr_init "mt47h64m16_3_333_cl5_async"
- sp310_init
- sp310_emi_init
-}
diff --git a/openocd-0.10.0/scripts/board/spear310evb20_mod.cfg b/openocd-0.10.0/scripts/board/spear310evb20_mod.cfg
deleted file mode 100644
index a7bac55a5c9e11f7a4be60a93b4623c6d26b4ff4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/spear310evb20_mod.cfg
+++ /dev/null
@@ -1,25 +0,0 @@
-# Configuration for the ST SPEAr310 Evaluation board
-# EVALSPEAr310 Rev. 2.0, modified to enable SRST on JTAG connector
-# http://www.st.com/spear
-#
-# List of board modifications to enable SRST, as reported in
-# ST Application Note AN3321.
-# - Modifications on the top layer:
-# 1. remove R137 and C57, located near the SMII PHY U18;
-# 2. remove R172 and C75, located near the SMII PHY U19;
-# 3. remove R207 and C90, located near the SMII PHY U20;
-# 4. remove C236, located near the SMII PHY U21;
-# 5. remove U12, located near the JTAG connector;
-# 6. solder together pins 7, 8 and 9 of U12;
-# 7. solder together pins 11, 12, 13, 14, 15, 16, 17 and 18 of U12.
-# - Modifications on the bottom layer:
-# 8. replace reset chip U11 with a STM6315SDW13F;
-# 9. add 0 ohm resistor R329. It is located close to JTAG connector.
-#
-# Date: 2009-10-31
-# Author: Antonio Borneo <borneo.antonio@gmail.com>
-
-
-# Modified boards has SRST on JTAG connector
-set BOARD_HAS_SRST 1
-source [find board/spear310evb20.cfg]
diff --git a/openocd-0.10.0/scripts/board/spear320cpu.cfg b/openocd-0.10.0/scripts/board/spear320cpu.cfg
deleted file mode 100644
index e21db3412567b41b49bbe73cc955ffb5df6ddfee..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/spear320cpu.cfg
+++ /dev/null
@@ -1,51 +0,0 @@
-# Configuration for the ST SPEAr320 CPU board
-# EVAL_SPEAr320CPU Rev. 2.0
-# http://www.st.com/spear
-#
-# Date: 2011-11-18
-# Author: Antonio Borneo <borneo.antonio@gmail.com>
-
-# The standard board has JTAG SRST not connected.
-# This script targets such boards using quirky code to bypass the issue.
-
-
-source [find mem_helper.tcl]
-source [find target/spear3xx.cfg]
-source [find chip/st/spear/spear3xx_ddr.tcl]
-source [find chip/st/spear/spear3xx.tcl]
-
-arm7_9 dcc_downloads enable
-arm7_9 fast_memory_access enable
-
-
-# Serial NOR on SMI CS0. 8Mbyte.
-set _FLASHNAME1 $_CHIPNAME.snor
-flash bank $_FLASHNAME1 stmsmi 0xf8000000 0 0 0 $_TARGETNAME
-
-if { [info exists BOARD_HAS_SRST] } {
- # Modified board has SRST on JTAG connector
- reset_config trst_and_srst separate srst_gates_jtag \
- trst_push_pull srst_open_drain
-} else {
- # Standard board has no SRST on JTAG connector
- reset_config trst_only separate srst_gates_jtag trst_push_pull
- source [find chip/st/spear/quirk_no_srst.tcl]
-}
-
-$_TARGETNAME configure -event reset-init { spear320cpu_init }
-
-if { [info exists DDR_CHIPS] } {
- set _DDR_CHIPS $DDR_CHIPS
-} else {
- set _DDR_CHIPS 1
-}
-
-proc spear320cpu_init {} {
- global _DDR_CHIPS
- reg pc 0xffff0020; # loop forever
-
- sp3xx_clock_default
- sp3xx_common_init
- sp3xx_ddr_init "mt47h64m16_3_333_cl5_async" $_DDR_CHIPS
- sp320_init
-}
diff --git a/openocd-0.10.0/scripts/board/spear320cpu_mod.cfg b/openocd-0.10.0/scripts/board/spear320cpu_mod.cfg
deleted file mode 100644
index 1d62e3b554c931dd24acbc25b06e8178d878461b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/spear320cpu_mod.cfg
+++ /dev/null
@@ -1,25 +0,0 @@
-# Configuration for the ST SPEAr320 Evaluation board
-# EVAL_SPEAr320CPU Rev. 2.0, modified to enable SRST on JTAG connector
-# http://www.st.com/spear
-#
-# List of board modifications to enable SRST, as reported in
-# ST Application Note (FIXME: add reference).
-# - Modifications on the bottom layer:
-# 1. replace reset chip U7 with a STM6315SDW13F;
-# 2. add 0 ohm resistor R45. It is located close to JTAG connector.
-# 3. add a 10K ohm pull-up resistor on the reset wire named as
-# POWERGOOD in the schematic.
-#
-# The easier way to do modification 3, is to use a resistor in package
-# 0603 or 0402 and solder it between R15 and R45:
-# - one pad soldered with the pad of R15 connected to 3.3V (this
-# is the pad of R15 closer to R45)
-# - the other pad soldered with the nearest pad of R45.
-#
-# Date: 2011-11-18
-# Author: Antonio Borneo <borneo.antonio@gmail.com>
-
-
-# Modified boards has SRST on JTAG connector
-set BOARD_HAS_SRST 1
-source [find board/spear320cpu.cfg]
diff --git a/openocd-0.10.0/scripts/board/st_nucleo_f0.cfg b/openocd-0.10.0/scripts/board/st_nucleo_f0.cfg
deleted file mode 100644
index e9fda19a690ae4c72717b7c3ef24ed54b65aef47..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/st_nucleo_f0.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-# This is for all ST NUCLEO with any STM32F0. Known boards at the moment:
-# STM32F030R8
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259997
-# NUCLEO-F072RB
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259997
-# STM32F091RC
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260944
-
-source [find interface/stlink-v2-1.cfg]
-
-transport select hla_swd
-
-source [find target/stm32f0x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/st_nucleo_f103rb.cfg b/openocd-0.10.0/scripts/board/st_nucleo_f103rb.cfg
deleted file mode 100644
index 71a92f704e312bd37451bd3b34e97d37bd6fe7ef..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/st_nucleo_f103rb.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# This is an ST NUCLEO F103RB board with a single STM32F103RBT6 chip.
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259875
-
-source [find interface/stlink-v2-1.cfg]
-
-transport select hla_swd
-
-source [find target/stm32f1x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/st_nucleo_f3.cfg b/openocd-0.10.0/scripts/board/st_nucleo_f3.cfg
deleted file mode 100644
index 9dffdcbbdec3ed81875f660b6ee8ee28fb06393c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/st_nucleo_f3.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# This is an ST NUCLEO F334R8 board with a single STM32F334R8T6 chip.
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260004
-
-source [find interface/stlink-v2-1.cfg]
-
-transport select hla_swd
-
-source [find target/stm32f3x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/st_nucleo_f4.cfg b/openocd-0.10.0/scripts/board/st_nucleo_f4.cfg
deleted file mode 100644
index b5a78c1c094f2bd5248540ff2d1fef0316890d1a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/st_nucleo_f4.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-# This is for all ST NUCLEO with any STM32F4. Known boards at the moment:
-# STM32F401RET6
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260000
-# STM32F411RET6
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260320
-
-source [find interface/stlink-v2-1.cfg]
-
-transport select hla_swd
-
-source [find target/stm32f4x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/st_nucleo_l1.cfg b/openocd-0.10.0/scripts/board/st_nucleo_l1.cfg
deleted file mode 100644
index 56e275627be838b5df6c19b11099ffe5e23c7d0f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/st_nucleo_l1.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# This is an ST NUCLEO L152RE board with a single STM32L152RET6 chip.
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260002
-
-source [find interface/stlink-v2-1.cfg]
-
-transport select hla_swd
-
-source [find target/stm32l1.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/st_nucleo_l476rg.cfg b/openocd-0.10.0/scripts/board/st_nucleo_l476rg.cfg
deleted file mode 100644
index 2baa34e76ce8d4e70e4e89ad4bb01ad761ceee8b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/st_nucleo_l476rg.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-# This is a ST NUCLEO L476RG board with a single STM32L476RGT6 chip.
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF261636
-
-source [find interface/stlink-v2-1.cfg]
-
-transport select hla_swd
-
-source [find target/stm32l4x.cfg]
-
-# use hardware reset
-reset_config srst_only srst_nogate
-
diff --git a/openocd-0.10.0/scripts/board/steval_pcc010.cfg b/openocd-0.10.0/scripts/board/steval_pcc010.cfg
deleted file mode 100644
index ddfdbb36fde907ff23a990e695a5034484ddde84..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/steval_pcc010.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-# Use for the STM207VG plug-in board (1 MiB Flash and 112+16 KiB Ram
-# comming with the STEVAL-PCC010 board
-# http://www.st.com/internet/evalboard/product/251530.jsp
-# or any other board with only a STM32F2x in the JTAG chain
-
-# increase working area to 32KB for faster flash programming
-set WORKAREASIZE 0x8000
-
-source [find target/stm32f2x.cfg]
diff --git a/openocd-0.10.0/scripts/board/stm320518_eval.cfg b/openocd-0.10.0/scripts/board/stm320518_eval.cfg
deleted file mode 100644
index 6f1f322717ee168a0dbdcddaac8f7da3dfc7fd48..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm320518_eval.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-# STM320518-EVAL: This is an STM32F0 eval board with a single STM32F051R8T6
-# (64KB) chip.
-# http://www.st.com/internet/evalboard/product/252994.jsp
-#
-
-# increase working area to 8KB
-set WORKAREASIZE 0x2000
-
-# chip name
-set CHIPNAME STM32F051R8T6
-
-source [find target/stm32f0x.cfg]
diff --git a/openocd-0.10.0/scripts/board/stm320518_eval_stlink.cfg b/openocd-0.10.0/scripts/board/stm320518_eval_stlink.cfg
deleted file mode 100644
index ce074cbf2a37e19fb3ba7d74b6f2e3466f3ae8a1..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm320518_eval_stlink.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-# STM320518-EVAL: This is an STM32F0 eval board with a single STM32F051R8T6
-# (64KB) chip.
-# http://www.st.com/internet/evalboard/product/252994.jsp
-#
-# This is for using the onboard STLINK/V2
-
-source [find interface/stlink-v2.cfg]
-
-transport select hla_swd
-
-# increase working area to 8KB
-set WORKAREASIZE 0x2000
-
-# chip name
-set CHIPNAME STM32F051R8T6
-
-source [find target/stm32f0x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/stm32100b_eval.cfg b/openocd-0.10.0/scripts/board/stm32100b_eval.cfg
deleted file mode 100644
index 41153e555b884be027fbc156edfb8dbef7ff2cc8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32100b_eval.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-# This is an STM32 eval board with a single STM32F100VBT6 chip.
-# http://www.st.com/internet/evalboard/product/247099.jsp
-
-# The chip has only 8KB sram
-set WORKAREASIZE 0x2000
-
-source [find target/stm32f1x.cfg]
diff --git a/openocd-0.10.0/scripts/board/stm3210b_eval.cfg b/openocd-0.10.0/scripts/board/stm3210b_eval.cfg
deleted file mode 100644
index ff3f7771abc8d0bbc0fea94b40f63f2254a1c534..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm3210b_eval.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-# This is an STM32 eval board with a single STM32F10x (128KB) chip.
-# http://www.st.com/internet/evalboard/product/176090.jsp
-
-# increase working area to 32KB for faster flash programming
-set WORKAREASIZE 0x8000
-
-source [find target/stm32f1x.cfg]
diff --git a/openocd-0.10.0/scripts/board/stm3210c_eval.cfg b/openocd-0.10.0/scripts/board/stm3210c_eval.cfg
deleted file mode 100644
index e069c049941f82176e2b4a573ce4c27f468ae1e8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm3210c_eval.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-# This is an STM32 eval board with a single STM32F107VCT chip.
-# http://www.st.com/internet/evalboard/product/217965.jsp
-
-# increase working area to 32KB for faster flash programming
-set WORKAREASIZE 0x8000
-
-source [find target/stm32f1x.cfg]
diff --git a/openocd-0.10.0/scripts/board/stm3210e_eval.cfg b/openocd-0.10.0/scripts/board/stm3210e_eval.cfg
deleted file mode 100644
index 91807ce3094906861e6bb70d5d4b2ee4a573f1d2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm3210e_eval.cfg
+++ /dev/null
@@ -1,63 +0,0 @@
-# This is an STM32 eval board with a single STM32F103ZET6 chip.
-# http://www.st.com/internet/evalboard/product/204176.jsp
-
-# increase working area to 32KB for faster flash programming
-set WORKAREASIZE 0x8000
-
-source [find target/stm32f1x.cfg]
-
-#
-# configure FSMC Bank 1 (NOR/PSRAM Bank 2) NOR flash
-# M29W128GL70ZA6E
-#
-
-set _FLASHNAME $_CHIPNAME.norflash
-flash bank $_FLASHNAME cfi 0x64000000 0x01000000 2 2 $_TARGETNAME
-
-proc stm32_enable_fsmc {} {
-
- echo "Enabling FSMC Bank 1 (NOR/PSRAM Bank 2)"
-
- # enable gpio (defg) clocks for fsmc
- # RCC_APB2ENR
- mww 0x40021018 0x000001E0
-
- # enable fsmc clock
- # RCC_AHBENR
- mww 0x40021014 0x00000114
-
- # configure gpio to alternate function
- # GPIOD_CRL
- mww 0x40011400 0x44BB44BB
- # GPIOD_CRH
- mww 0x40011404 0xBBBBBBBB
-
- # GPIOE_CRL
- mww 0x40011800 0xBBBBB444
- # GPIOE_CRH
- mww 0x40011804 0xBBBBBBBB
-
- # GPIOF_CRL
- mww 0x40011C00 0x44BBBBBB
- # GPIOF_CRH
- mww 0x40011C04 0xBBBB4444
-
- # GPIOG_CRL
- mww 0x40012000 0x44BBBBBB
- # GPIOG_CRH
- mww 0x40012004 0x444444B4
-
- # setup fsmc timings
- # FSMC_BCR1
- mww 0xA0000008 0x00001058
-
- # FSMC_BTR1
- mww 0xA000000C 0x10000502
-
- # FSMC_BCR1 - enable fsmc
- mww 0xA0000008 0x00001059
-}
-
-$_TARGETNAME configure -event reset-init {
- stm32_enable_fsmc
-}
diff --git a/openocd-0.10.0/scripts/board/stm3220g_eval.cfg b/openocd-0.10.0/scripts/board/stm3220g_eval.cfg
deleted file mode 100644
index 472843298702675a62ee49fd42413472084214b4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm3220g_eval.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# STM3220G-EVAL: This is an STM32F2 eval board with a single STM32F207IGH6
-# (128KB) chip.
-# http://www.st.com/internet/evalboard/product/250374.jsp
-
-# increase working area to 128KB
-set WORKAREASIZE 0x20000
-
-# chip name
-set CHIPNAME STM32F207IGH6
-
-source [find target/stm32f2x.cfg]
diff --git a/openocd-0.10.0/scripts/board/stm3220g_eval_stlink.cfg b/openocd-0.10.0/scripts/board/stm3220g_eval_stlink.cfg
deleted file mode 100644
index 43a4df98601c5fff70f015942e5291d1fbf5cb3a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm3220g_eval_stlink.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-# STM3220G-EVAL: This is an STM32F2 eval board with a single STM32F207IGH6
-# (128KB) chip.
-# http://www.st.com/internet/evalboard/product/250374.jsp
-#
-# This is for using the onboard STLINK/V2
-
-source [find interface/stlink-v2.cfg]
-
-transport select hla_swd
-
-# increase working area to 128KB
-set WORKAREASIZE 0x20000
-
-# chip name
-set CHIPNAME STM32F207IGH6
-
-source [find target/stm32f2x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/stm3241g_eval.cfg b/openocd-0.10.0/scripts/board/stm3241g_eval.cfg
deleted file mode 100644
index 5f1c449d354624d128654c1bc6a26ae59f161f4e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm3241g_eval.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# STM3241G-EVAL: This is an STM32F4 eval board with a single STM32F417IGH6
-# (1024KB) chip.
-# http://www.st.com/internet/evalboard/product/252216.jsp
-
-# increase working area to 128KB
-set WORKAREASIZE 0x20000
-
-# chip name
-set CHIPNAME STM32F417IGH6
-
-source [find target/stm32f4x.cfg]
diff --git a/openocd-0.10.0/scripts/board/stm3241g_eval_stlink.cfg b/openocd-0.10.0/scripts/board/stm3241g_eval_stlink.cfg
deleted file mode 100644
index 9c7ad5d95fa914d624261bcfafb3bc22fc0f61d7..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm3241g_eval_stlink.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-# STM3241G-EVAL: This is an STM32F4 eval board with a single STM32F417IGH6
-# (1024KB) chip.
-# http://www.st.com/internet/evalboard/product/252216.jsp
-#
-# This is for using the onboard STLINK/V2
-
-source [find interface/stlink-v2.cfg]
-
-transport select hla_swd
-
-# increase working area to 128KB
-set WORKAREASIZE 0x20000
-
-# chip name
-set CHIPNAME STM32F417IGH6
-
-source [find target/stm32f4x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/stm32429i_eval.cfg b/openocd-0.10.0/scripts/board/stm32429i_eval.cfg
deleted file mode 100644
index a5d3f53c92d8ef825ade79d935fbbb5764c02953..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32429i_eval.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# STM32429I-EVAL: This is an STM32F4 eval board with a single STM32F429NIH6
-# (2048KB) chip.
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259093
-
-# increase working area to 128KB
-set WORKAREASIZE 0x20000
-
-# chip name
-set CHIPNAME STM32F429NIH6
-
-source [find target/stm32f4x.cfg]
diff --git a/openocd-0.10.0/scripts/board/stm32429i_eval_stlink.cfg b/openocd-0.10.0/scripts/board/stm32429i_eval_stlink.cfg
deleted file mode 100644
index 2b51cea675907cdca7554f0aeb7ebed4175f406d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32429i_eval_stlink.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-# STM32429I-EVAL: This is an STM32F4 eval board with a single STM32F429NIH6
-# (2048KB) chip.
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259093
-#
-# This is for using the onboard STLINK/V2
-
-source [find interface/stlink-v2.cfg]
-
-transport select hla_swd
-
-# increase working area to 128KB
-set WORKAREASIZE 0x20000
-
-# chip name
-set CHIPNAME STM32F429NIH6
-
-source [find target/stm32f4x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/stm32439i_eval.cfg b/openocd-0.10.0/scripts/board/stm32439i_eval.cfg
deleted file mode 100644
index 8ebdc82675a93f59b61b7f84708f0cd8daa7d481..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32439i_eval.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# STM32439I-EVAL: This is an STM32F4 eval board with a single STM32F439NIH6
-# (2048KB) chip.
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259094
-
-# increase working area to 128KB
-set WORKAREASIZE 0x20000
-
-# chip name
-set CHIPNAME STM32F439NIH6
-
-source [find target/stm32f4x.cfg]
diff --git a/openocd-0.10.0/scripts/board/stm32439i_eval_stlink.cfg b/openocd-0.10.0/scripts/board/stm32439i_eval_stlink.cfg
deleted file mode 100644
index 5995fb1d286c81668d43b5abdeb725d87cee1bfc..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32439i_eval_stlink.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-# STM32439I-EVAL: This is an STM32F4 eval board with a single STM32F439NIH6
-# (2048KB) chip.
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF259094
-#
-# This is for using the onboard STLINK/V2
-
-source [find interface/stlink-v2.cfg]
-
-transport select hla_swd
-
-# increase working area to 128KB
-set WORKAREASIZE 0x20000
-
-# chip name
-set CHIPNAME STM32F439NIH6
-
-source [find target/stm32f4x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/stm327x6g_eval.cfg b/openocd-0.10.0/scripts/board/stm327x6g_eval.cfg
deleted file mode 100644
index a5e5896b32f4a9dbe26905ad924af0537a641d27..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm327x6g_eval.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# STM327[4|5]6G-EVAL: This is for the STM32F7 eval boards.
-# STM32746G-EVAL
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF261639
-# STM32756G-EVAL
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1199/PF261640
-
-# increase working area to 256KB
-set WORKAREASIZE 0x40000
-
-source [find target/stm32f7x.cfg]
diff --git a/openocd-0.10.0/scripts/board/stm32f0discovery.cfg b/openocd-0.10.0/scripts/board/stm32f0discovery.cfg
deleted file mode 100644
index bae9a69ba0d40f43ca69c6bbc74e6d33927abf91..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32f0discovery.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# This is an STM32F0 discovery board with a single STM32F051R8T6 chip.
-# http://www.st.com/internet/evalboard/product/253215.jsp
-
-source [find interface/stlink-v2.cfg]
-
-transport select hla_swd
-
-set WORKAREASIZE 0x2000
-source [find target/stm32f0x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/stm32f334discovery.cfg b/openocd-0.10.0/scripts/board/stm32f334discovery.cfg
deleted file mode 100644
index be817d7165db2d2382395690e685946fbde49a66..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32f334discovery.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-# This is an STM32F334 discovery board with a single STM32F334C8T6 chip.
-# As it is one of the few boards with stlink V.2-1, we source the corresponding
-# nucleo file.
-# http://www.st.com/web/en/catalog/tools/FM116/SC959/SS1532/LN1848/PF260318
-
-source [find board/st_nucleo_f3.cfg]
diff --git a/openocd-0.10.0/scripts/board/stm32f3discovery.cfg b/openocd-0.10.0/scripts/board/stm32f3discovery.cfg
deleted file mode 100644
index 5a17b4c992f609a81cc49df66d3918b050abd92c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32f3discovery.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# This is an STM32F3 discovery board with a single STM32F303VCT6 chip.
-# http://www.st.com/internet/evalboard/product/254044.jsp
-
-source [find interface/stlink-v2.cfg]
-
-transport select hla_swd
-
-source [find target/stm32f3x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/stm32f429disc1.cfg b/openocd-0.10.0/scripts/board/stm32f429disc1.cfg
deleted file mode 100644
index 9d3cdd7575ac665586bbbd3d79cb3ec0ba566686..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32f429disc1.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# This is an STM32F429 discovery board with a single STM32F429ZI chip.
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090
-#
-
-source [find interface/stlink-v2-1.cfg]
-
-transport select hla_swd
-
-source [find target/stm32f4x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/stm32f429discovery.cfg b/openocd-0.10.0/scripts/board/stm32f429discovery.cfg
deleted file mode 100644
index e06d2a51c5b09f3782934007d6229e3e206d2cb7..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32f429discovery.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# This is an STM32F429 discovery board with a single STM32F429ZI chip.
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090
-#
-
-source [find interface/stlink-v2.cfg]
-
-transport select hla_swd
-
-# increase working area to 128KB
-set WORKAREASIZE 0x20000
-
-source [find target/stm32f4x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/stm32f469discovery.cfg b/openocd-0.10.0/scripts/board/stm32f469discovery.cfg
deleted file mode 100644
index 63b13638afa3b19ddde6261c93cb959a2800b71f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32f469discovery.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# This is an STM32F469 discovery board with a single STM32F469NI chip.
-# http://www.st.com/web/catalog/tools/FM116/CL1620/SC959/SS1532/LN1848/PF262395
-#
-
-source [find interface/stlink-v2-1.cfg]
-
-transport select hla_swd
-
-# increase working area to 128KB
-set WORKAREASIZE 0x20000
-
-source [find target/stm32f4x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/stm32f4discovery.cfg b/openocd-0.10.0/scripts/board/stm32f4discovery.cfg
deleted file mode 100644
index 963e0f95931daf202ecc72c4ac8ea255866afbac..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32f4discovery.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-# This is an STM32F4 discovery board with a single STM32F407VGT6 chip.
-# http://www.st.com/internet/evalboard/product/252419.jsp
-
-source [find interface/stlink-v2.cfg]
-
-transport select hla_swd
-
-# increase working area to 64KB
-set WORKAREASIZE 0x10000
-
-source [find target/stm32f4x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/stm32f7discovery.cfg b/openocd-0.10.0/scripts/board/stm32f7discovery.cfg
deleted file mode 100644
index 085340f306a928fa8c2a51cbb8b8a715a138b71d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32f7discovery.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-# This is an STM32F7 discovery board with a single STM32F756NGH6 chip.
-# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1848/PF261641
-
-# This is for using the onboard STLINK/V2-1
-source [find interface/stlink-v2-1.cfg]
-
-transport select hla_swd
-
-# increase working area to 256KB
-set WORKAREASIZE 0x40000
-
-source [find target/stm32f7x.cfg]
diff --git a/openocd-0.10.0/scripts/board/stm32l0discovery.cfg b/openocd-0.10.0/scripts/board/stm32l0discovery.cfg
deleted file mode 100644
index a035062242f36e286d38f394744c083066c6e21c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32l0discovery.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# This is an STM32L053 discovery board with a single STM32L053 chip.
-# http://www.st.com/web/en/catalog/tools/PF260319
-
-source [find interface/stlink-v2-1.cfg]
-
-transport select hla_swd
-
-set WORKAREASIZE 0x2000
-source [find target/stm32l0.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/stm32l4discovery.cfg b/openocd-0.10.0/scripts/board/stm32l4discovery.cfg
deleted file mode 100644
index eb19331163f2ce05348d407729d4407a3cf7a754..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32l4discovery.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-# Explicitly for the STM32L476 discovery board:
-# http://www.st.com/web/en/catalog/tools/PF261635
-# but perfectly functional for any other STM32L4 board connected via
-# an stlink-v2-1 interface.
-# This is for STM32L4 boards that are connected via stlink-v2-1.
-
-source [find interface/stlink-v2-1.cfg]
-
-transport select hla_swd
-
-source [find target/stm32l4x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/stm32ldiscovery.cfg b/openocd-0.10.0/scripts/board/stm32ldiscovery.cfg
deleted file mode 100644
index 8678d290bd144dd79672ce01258b32fdb212f0e8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32ldiscovery.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# This is an STM32L discovery board with a single STM32L152RBT6 chip.
-# http://www.st.com/internet/evalboard/product/250990.jsp
-
-source [find interface/stlink-v2.cfg]
-
-transport select hla_swd
-
-set WORKAREASIZE 0x4000
-source [find target/stm32l1.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/stm32vldiscovery.cfg b/openocd-0.10.0/scripts/board/stm32vldiscovery.cfg
deleted file mode 100644
index 970b5101e81ecb6b9e6a1bcb64e48c357582542c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/stm32vldiscovery.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# This is an STM32VL discovery board with a single STM32F100RB chip.
-# http://www.st.com/internet/evalboard/product/250863.jsp
-
-source [find interface/stlink-v1.cfg]
-
-transport select hla_swd
-
-set WORKAREASIZE 0x2000
-source [find target/stm32f1x.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/str910-eval.cfg b/openocd-0.10.0/scripts/board/str910-eval.cfg
deleted file mode 100644
index 5fe7a4e733d06f9b2fd4836311df0b99ffcd5bde..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/str910-eval.cfg
+++ /dev/null
@@ -1,64 +0,0 @@
-# str910-eval eval board
-#
-# Need reset scripts
-reset_config trst_and_srst
-
-# FIXME use some standard target config, maybe create one from this
-#
-# source [find target/...cfg]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str912
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists FLASHTAPID] } {
- set _FLASHTAPID $FLASHTAPID
-} else {
- set _FLASHTAPID 0x04570041
-}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
-
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x25966041
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID] } {
- set _BSTAPID $BSTAPID
-} else {
- set _BSTAPID 0x1457f041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1
-
-$_TARGETNAME configure -event reset-init {
- # We can increase speed now that we know the target is halted.
- #jtag_rclk 3000
-
- # -- Enable 96K RAM
- # PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
-
- str9x flash_config 0 4 2 0 0x80000
- flash protect 0 0 7 off
-}
-
-#flash bank str9x <base> <size> 0 0 <target#> <variant>
-set _FLASHNAME $_CHIPNAME.flash0
-flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
diff --git a/openocd-0.10.0/scripts/board/telo.cfg b/openocd-0.10.0/scripts/board/telo.cfg
deleted file mode 100644
index 1d3afdf0b341f223186d014b1a847fe907f74d47..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/telo.cfg
+++ /dev/null
@@ -1,58 +0,0 @@
-source [find target/c100.cfg]
-# basic register defintion for C100
-source [find target/c100regs.tcl]
-# board-config info
-source [find target/c100config.tcl]
-# C100 helper functions
-source [find target/c100helper.tcl]
-
-
-# Telo board & C100 support trst and srst
-# make the reset asserted to
-# allow RC circuit to discharge for: [ms]
-adapter_nsrst_assert_width 100
-jtag_ntrst_assert_width 100
-# don't talk to JTAG after reset for: [ms]
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-reset_config trst_and_srst separate
-
-
-
-
-# issue telnet: reset init
-# issue gdb: monitor reset init
-$_TARGETNAME configure -event reset-init {
- adapter_khz 100
- # this will setup Telo board
- setupTelo
- #turn up the JTAG speed
- adapter_khz 3000
- echo "JTAG speek now 3MHz"
- echo "type helpC100 to get help on C100"
-}
-
-$_TARGETNAME configure -event reset-deassert-post {
- # Force target into ARM state.
-# soft_reset_halt ;# not implemented on ARM11
- echo "Detected SRSRT asserted on C100.CPU"
-
-}
-
-$_TARGETNAME configure -event reset-assert-post {
- echo "Assering reset"
- #sleep 10
-}
-
-proc power_restore {} { echo "Sensed power restore. No action." }
-proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
-
-
-# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
-# it's really 16MB but the upper 8mb is controller via gpio
-# openocd does not support 'complex reads/writes' to NOR
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
-
-# writing data to memory does not work without this
-arm11 memwrite burst disable
diff --git a/openocd-0.10.0/scripts/board/ti-cc3200-launchxl.cfg b/openocd-0.10.0/scripts/board/ti-cc3200-launchxl.cfg
deleted file mode 100644
index fd80c531008c1678f2e6b6b8399b462783710209..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ti-cc3200-launchxl.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# TI SimpleLink Wi-Fi CC3200 LaunchPad
-#
-# http://www.ti.com/tool/cc3200-launchxl
-#
-
-source [find interface/ftdi/ti-icdi.cfg]
-
-if { [info exists TRANSPORT] } {
- transport select $TRANSPORT
-} else {
- transport select jtag
-}
-
-set WORKAREASIZE 0x40000
-source [find target/cc32xx.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/ti_am335xevm.cfg b/openocd-0.10.0/scripts/board/ti_am335xevm.cfg
deleted file mode 100644
index 3e2ee3ff97b3931f578c0a6ea25575a7d26ba0ce..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ti_am335xevm.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# TI AM335x Evaluation Module
-#
-# For more information please see http://www.ti.com/tool/tmdxevm3358
-#
-jtag_rclk 6000
-
-source [find target/am335x.cfg]
-
-reset_config trst_and_srst
diff --git a/openocd-0.10.0/scripts/board/ti_am437x_idk.cfg b/openocd-0.10.0/scripts/board/ti_am437x_idk.cfg
deleted file mode 100644
index 65e2094e8e8eb6f05c9066bdf26476b55499c07e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ti_am437x_idk.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-# Texas Instruments AM437x Industrial Development Kit
-
-# The JTAG interface is built directly on the board.
-source [find interface/ftdi/xds100v2.cfg]
-
-transport select jtag
-adapter_khz 30000
-
-source [find target/am437x.cfg]
-$_TARGETNAME configure -event reset-init { init_platform 0x61a11b32 }
-
-reset_config trst_and_srst
diff --git a/openocd-0.10.0/scripts/board/ti_am43xx_evm.cfg b/openocd-0.10.0/scripts/board/ti_am43xx_evm.cfg
deleted file mode 100644
index d536314ba1e7eef52b90f66a7198ed0ffb2a43f7..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ti_am43xx_evm.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-# Works on both AM437x GP EVM and AM438x ePOS EVM
-transport select jtag
-adapter_khz 16000
-
-source [find target/am437x.cfg]
-
-reset_config trst_and_srst
diff --git a/openocd-0.10.0/scripts/board/ti_beagleboard.cfg b/openocd-0.10.0/scripts/board/ti_beagleboard.cfg
deleted file mode 100644
index 9b3b8b01665b3dce609e846b72ece1657ea03acf..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ti_beagleboard.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-# OMAP3 BeagleBoard
-# http://beagleboard.org
-
-# Fall back to 6MHz if RTCK is not supported
-jtag_rclk 6000
-
-source [find target/omap3530.cfg]
-
-# TI-14 JTAG connector
-reset_config trst_only
-
-# Later run: omap3_dbginit
diff --git a/openocd-0.10.0/scripts/board/ti_beagleboard_xm.cfg b/openocd-0.10.0/scripts/board/ti_beagleboard_xm.cfg
deleted file mode 100644
index e4e93e333b6981ed610bd3c35cd2a08edd4babe7..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ti_beagleboard_xm.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-# BeagleBoard xM (DM37x)
-# http://beagleboard.org
-
-set CHIPTYPE "dm37x"
-source [find target/amdm37x.cfg]
-
-# The TI-14 JTAG connector does not have srst. CPU reset is handled in
-# hardware.
-reset_config trst_only
-
-# "amdm37x_dbginit dm37x.cpu" needs to be run after init.
-
diff --git a/openocd-0.10.0/scripts/board/ti_beaglebone.cfg b/openocd-0.10.0/scripts/board/ti_beaglebone.cfg
deleted file mode 100644
index 5d31d1d971e0bc88f4a405c1d6054b1ff719fb81..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ti_beaglebone.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-# AM335x Beaglebone
-# http://beagleboard.org/bone
-
-# The JTAG interface is built directly on the board.
-source [find interface/ftdi/xds100v2.cfg]
-
-adapter_khz 16000
-
-source [find target/am335x.cfg]
-
-reset_config trst_and_srst
-
-
diff --git a/openocd-0.10.0/scripts/board/ti_blaze.cfg b/openocd-0.10.0/scripts/board/ti_blaze.cfg
deleted file mode 100644
index c9bbe25c060b07d8109a36150243a56a3398dd76..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ti_blaze.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-jtag_rclk 6000
-
-source [find target/omap4430.cfg]
-
-reset_config trst_and_srst
-
diff --git a/openocd-0.10.0/scripts/board/ti_pandaboard.cfg b/openocd-0.10.0/scripts/board/ti_pandaboard.cfg
deleted file mode 100644
index bd2cd370310daeddc6d0ace0233ac97228d876a4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ti_pandaboard.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-jtag_rclk 6000
-
-source [find target/omap4430.cfg]
-
-reset_config trst_only
-
diff --git a/openocd-0.10.0/scripts/board/ti_pandaboard_es.cfg b/openocd-0.10.0/scripts/board/ti_pandaboard_es.cfg
deleted file mode 100644
index 2abd7e97ad6ba75f9e67ee85dc2e9bcdaea5fe01..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ti_pandaboard_es.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-jtag_rclk 6000
-
-source [find target/omap4460.cfg]
-
-reset_config trst_only
-
diff --git a/openocd-0.10.0/scripts/board/ti_tmdx570ls20susb.cfg b/openocd-0.10.0/scripts/board/ti_tmdx570ls20susb.cfg
deleted file mode 100644
index 87cab2690747e3a64e282b6feb9810ddffc05789..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ti_tmdx570ls20susb.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-# TMS570 Microcontroller USB Kit
-# http://www.ti.com/tool/TMDX570LS20SUSB
-
-# Board uses a FT2232H to emulate an XDS100v2 JTAG debugger
-# TODO: board also supports an SCI UART on the 2232's B Bus
-source [find interface/ftdi/xds100v2.cfg]
-
-# Processor is TMS570LS20216
-source [find target/ti_tms570ls20xxx.cfg]
-
-reset_config trst_only
-
-# xds100v2 config says add this to the end
-init
-ftdi_set_signal PWR_RST 1
-jtag arp_init
diff --git a/openocd-0.10.0/scripts/board/ti_tmdx570ls31usb.cfg b/openocd-0.10.0/scripts/board/ti_tmdx570ls31usb.cfg
deleted file mode 100644
index 550244429dbc31c8e9a9f1ad9fe0dde452bf811b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/ti_tmdx570ls31usb.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-adapter_khz 1500
-
-source [find interface/ftdi/xds100v2.cfg]
-source [find target/ti_tms570.cfg]
-
-reset_config trst_only
diff --git a/openocd-0.10.0/scripts/board/topas910.cfg b/openocd-0.10.0/scripts/board/topas910.cfg
deleted file mode 100644
index 90c18c4846cd8922e5a34ff001053893107a6e42..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/topas910.cfg
+++ /dev/null
@@ -1,119 +0,0 @@
-######################################
-# Target: Toshiba TOPAS910 -- TMPA910 Starterkit
-#
-######################################
-
-# We add to the minimal configuration.
-source [find target/tmpa910.cfg]
-
-######################
-# Target configuration
-######################
-
-#$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { topas910_init }
-
-proc topas910_init { } {
-# Init PLL
-# my settings
- mww 0xf005000c 0x00000007
- mww 0xf0050010 0x00000065
- mww 0xf005000c 0x000000a7
- sleep 10
- mdw 0xf0050008
- mww 0xf0050008 0x00000002
- mww 0xf0050004 0x00000000
-# NEW: set CLKCR5
- mww 0xf0050054 0x00000040
-#
- sleep 10
-# Init SDRAM
-# _PMCDRV = 0x00000071;
-# //
-# // Initialize SDRAM timing paramater
-# //
-# _DMC_CAS_LATENCY = 0x00000006;
-# _DMC_T_DQSS = 0x00000000;
-# _DMC_T_MRD = 0x00000002;
-# _DMC_T_RAS = 0x00000007;
-#
-# _DMC_T_RC = 0x0000000A;
-# _DMC_T_RCD = 0x00000013;
-#
-# _DMC_T_RFC = 0x0000010A;
-#
-# _DMC_T_RP = 0x00000013;
-# _DMC_T_RRD = 0x00000002;
-# _DMC_T_WR = 0x00000002;
-# _DMC_T_WTR = 0x00000001;
-# _DMC_T_XP = 0x0000000A;
-# _DMC_T_XSR = 0x0000000B;
-# _DMC_T_ESR = 0x00000014;
-#
-# //
-# // Configure SDRAM type parameter
-# _DMC_MEMORY_CFG = 0x00008011;
-# _DMC_USER_CONFIG = 0x00000011;
-# // 32 bit memory interface
-#
-#
-# _DMC_REFRESH_PRD = 0x00000A60;
-# _DMC_CHIP_0_CFG = 0x000140FC;
-#
-# _DMC_DIRECT_CMD = 0x000C0000;
-# _DMC_DIRECT_CMD = 0x00000000;
-#
-# _DMC_DIRECT_CMD = 0x00040000;
-# _DMC_DIRECT_CMD = 0x00040000;
-# _DMC_DIRECT_CMD = 0x00080031;
-# //
-# // Finally start SDRAM
-# //
-# _DMC_MEMC_CMD = MEMC_CMD_GO;
-# */
-
- mww 0xf0020260 0x00000071
- mww 0xf4300014 0x00000006
- mww 0xf4300018 0x00000000
- mww 0xf430001C 0x00000002
- mww 0xf4300020 0x00000007
- mww 0xf4300024 0x0000000A
- mww 0xf4300028 0x00000013
- mww 0xf430002C 0x0000010A
- mww 0xf4300030 0x00000013
- mww 0xf4300034 0x00000002
- mww 0xf4300038 0x00000002
- mww 0xf430003C 0x00000001
- mww 0xf4300040 0x0000000A
- mww 0xf4300044 0x0000000B
- mww 0xf4300048 0x00000014
- mww 0xf430000C 0x00008011
- mww 0xf4300304 0x00000011
- mww 0xf4300010 0x00000A60
- mww 0xf4300200 0x000140FC
- mww 0xf4300008 0x000C0000
- mww 0xf4300008 0x00000000
- mww 0xf4300008 0x00040000
- mww 0xf4300008 0x00040000
- mww 0xf4300008 0x00080031
- mww 0xf4300004 0x00000000
-
- sleep 10
-# adapter_khz NNNN
-
-# remap off in case of IROM boot
- mww 0xf0000004 0x00000001
-
-}
-
-# comment the following out if usinf J-Link, it soes not support DCC
-arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
-
-
-#####################
-# Flash configuration
-#####################
-
-#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x20000000 0x2000000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/topasa900.cfg b/openocd-0.10.0/scripts/board/topasa900.cfg
deleted file mode 100644
index 2a388d5116f3d7fb99bb5d217ec436683e7dfff6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/topasa900.cfg
+++ /dev/null
@@ -1,126 +0,0 @@
-# Thanks to Pieter Conradie for this script!
-# Target: Toshiba TOPAS900 -- TMPA900 Starterkit
-######################################
-
-# We add to the minimal configuration.
-source [find target/tmpa900.cfg]
-
-######################
-# Target configuration
-######################
-
-#$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { topasa900_init }
-
-proc topasa900_init { } {
-# Init PLL
-# my settings
- mww 0xf005000c 0x00000007
- mww 0xf0050010 0x00000065
- mww 0xf005000c 0x000000a7
- sleep 10
- mdw 0xf0050008
- mww 0xf0050008 0x00000002
- mww 0xf0050004 0x00000000
-# NEW: set CLKCR5
- mww 0xf0050054 0x00000040
-#
-# bplan settings
-# mww 0xf0050004 0x00000000
-# mww 0xf005000c 0x000000a7
-# sleep 10
-# mdw 0xf0050008
-# mww 0xf0050008 0x00000002
-# mww 0xf0050010 0x00000065
-# mww 0xf0050054 0x00000040
- sleep 10
-# Init SDRAM
-# _PMCDRV = 0x00000071;
-# //
-# // Initialize SDRAM timing paramater
-# //
-# _DMC_CAS_LATENCY = 0x00000006;
-# _DMC_T_DQSS = 0x00000000;
-# _DMC_T_MRD = 0x00000002;
-# _DMC_T_RAS = 0x00000007;
-#
-# _DMC_T_RC = 0x0000000A;
-# _DMC_T_RCD = 0x00000013;
-#
-# _DMC_T_RFC = 0x0000010A;
-#
-# _DMC_T_RP = 0x00000013;
-# _DMC_T_RRD = 0x00000002;
-# _DMC_T_WR = 0x00000002;
-# _DMC_T_WTR = 0x00000001;
-# _DMC_T_XP = 0x0000000A;
-# _DMC_T_XSR = 0x0000000B;
-# _DMC_T_ESR = 0x00000014;
-#
-# //
-# // Configure SDRAM type parameter
-# _DMC_MEMORY_CFG = 0x00008011;
-# _DMC_USER_CONFIG = 0x00000011; // 32 bit memory interface
-#
-#
-# _DMC_REFRESH_PRD = 0x00000A60;
-# _DMC_CHIP_0_CFG = 0x000140FC;
-#
-# _DMC_DIRECT_CMD = 0x000C0000;
-# _DMC_DIRECT_CMD = 0x00000000;
-#
-# _DMC_DIRECT_CMD = 0x00040000;
-# _DMC_DIRECT_CMD = 0x00040000;
-# _DMC_DIRECT_CMD = 0x00080031;
-# //
-# // Finally start SDRAM
-# //
-# _DMC_MEMC_CMD = MEMC_CMD_GO;
-# */
-
- mww 0xf0020260 0x00000071
- mww 0xf4300014 0x00000006
- mww 0xf4300018 0x00000000
- mww 0xf430001C 0x00000002
- mww 0xf4300020 0x00000007
- mww 0xf4300024 0x0000000A
- mww 0xf4300028 0x00000013
- mww 0xf430002C 0x0000010A
- mww 0xf4300030 0x00000013
- mww 0xf4300034 0x00000002
- mww 0xf4300038 0x00000002
- mww 0xf430003C 0x00000001
- mww 0xf4300040 0x0000000A
- mww 0xf4300044 0x0000000B
- mww 0xf4300048 0x00000014
- mww 0xf430000C 0x00008011
- mww 0xf4300304 0x00000011
- mww 0xf4300010 0x00000A60
- mww 0xf4300200 0x000140FC
- mww 0xf4300008 0x000C0000
- mww 0xf4300008 0x00000000
- mww 0xf4300008 0x00040000
- mww 0xf4300008 0x00040000
- mww 0xf4300008 0x00080031
- mww 0xf4300004 0x00000000
-
- sleep 10
-# adapter_khz NNNN
-
-# remap off in case of IROM boot
- mww 0xf0000004 0x00000001
-
-}
-
-# comment the following out if usinf J-Link, it soes not support DCC
-arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
-
-
-#####################
-# Flash configuration
-#####################
-
-#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x20000000 0x1000000 2 2 $_TARGETNAME
-
diff --git a/openocd-0.10.0/scripts/board/tp-link_tl-mr3020.cfg b/openocd-0.10.0/scripts/board/tp-link_tl-mr3020.cfg
deleted file mode 100644
index b7d8d5b6150f57354e226cdca88d122f1ea5bab9..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/tp-link_tl-mr3020.cfg
+++ /dev/null
@@ -1,44 +0,0 @@
-source [find target/atheros_ar9331.cfg]
-
-proc ar9331_25mhz_pll_init {} {
- mww 0xb8050008 0x00018004 ;# bypass PLL; AHB_POST_DIV - ratio 4
- mww 0xb8050004 0x00000352 ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
- mww 0xb8050000 0x40818000 ;# Power down control for CPU PLL
- ;# OUTDIV | REFDIV | DIV_INT
- mww 0xb8050010 0x001003e8 ;# CPU PLL Dither FRAC Register
- ;# (disabled?)
- mww 0xb8050000 0x00818000 ;# Power on | OUTDIV | REFDIV | DIV_INT
- mww 0xb8050008 0x00008000 ;# remove bypass;
- ;# AHB_POST_DIV - ratio 2
-}
-
-proc ar9331_ddr1_init {} {
- mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs
- mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs
-
- mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
- mww 0xb8000008 0x133 ;# mode reg: 0x133 - default
- mww 0xb8000010 0x1 ;# Forces an MRS update cycl
- mww 0xb800000c 0x2 ;# Extended mode register value.
- ;# default 0x2 - Reset to weak driver, DLL on
- mww 0xb8000010 0x2 ;# Forces an EMRS update cycle
- mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
- mww 0xb8000008 0x33 ;# mode reg: remove some bit?
- mww 0xb8000010 0x1 ;# Forces an MRS update cycl
- mww 0xb8000014 0x4186 ;# enable refres: bit(14) - set refresh rate
- mww 0xb800001c 0x8 ;# This register is used along with DQ Lane 0,
- ;# DQ[7:0], DQS_0
- mww 0xb8000020 0x9 ;# This register is used along with DQ Lane 1,
- ;# DQ[15:8], DQS_1.
- mww 0xb8000018 0xff ;# DDR read and capture bit mask.
- ;# Each bit represents a cycle of valid data.
-}
-
-$_TARGETNAME configure -event reset-init {
- ar9331_25mhz_pll_init
- sleep 1
- ar9331_ddr1_init
-}
-
-set ram_boot_address 0xa0000000
-$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
diff --git a/openocd-0.10.0/scripts/board/twr-k60f120m.cfg b/openocd-0.10.0/scripts/board/twr-k60f120m.cfg
deleted file mode 100644
index e96d045262a4b307e1ed7de6dc3ae0bc43ca5571..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/twr-k60f120m.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Freescale TWRK60F120M development board
-#
-
-source [find target/k60.cfg]
-
-$_TARGETNAME configure -event reset-init {
- puts "-event reset-init occured"
-}
-
-#
-# Definitions for the additional 'program flash' banks
-# (instructions and/or data)
-#
-flash bank pflash.1 kinetis 0x00040000 0x40000 0 4 $_TARGETNAME
-flash bank pflash.2 kinetis 0x00080000 0x40000 0 4 $_TARGETNAME
-flash bank pflash.3 kinetis 0x000c0000 0x40000 0 4 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/twr-k60n512.cfg b/openocd-0.10.0/scripts/board/twr-k60n512.cfg
deleted file mode 100644
index d2312cf146946e5812f52a3414d888b4745aa9cf..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/twr-k60n512.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Freescale TWRK60N512 development board
-#
-
-source [find target/k60.cfg]
-
-$_TARGETNAME configure -event reset-init {
- puts "-event reset-init occured"
-}
-
-#
-# Definitions for the additional 'program flash' bank
-# (instructions and/or data)
-#
-flash bank pflash.1 kinetis 0x00040000 0x40000 0 4 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/twr-vf65gs10.cfg b/openocd-0.10.0/scripts/board/twr-vf65gs10.cfg
deleted file mode 100644
index a80407f3853560af5fbb38036d41acf01496bc2d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/twr-vf65gs10.cfg
+++ /dev/null
@@ -1,201 +0,0 @@
-#
-# Board configuration file for the Freescale VF65GS10 tower board
-#
-# Board has a 20 pin Cortex+ETM debug connector with only nSRST available
-reset_config srst_only
-
-# This configuration file only deals with the hardware JTAG.
-# There is has also an embedded Kinetis K20 with OpenSDA
-# where a CMSIS-DAP application can be installed.
-
-# Source generic VF6xx target configuration
-source [find target/vybrid_vf6xx.cfg]
-
-# basic DDR memory init, setting up pad configuration
-# for DDR first then configuring the DDRMC for the
-# board
-proc ddr_init { } {
- # iomux ddr
- mww phys 0x40048220 0x00000180
- mww phys 0x40048224 0x00000180
- mww phys 0x40048228 0x00000180
- mww phys 0x4004822c 0x00000180
- mww phys 0x40048230 0x00000180
- mww phys 0x40048234 0x00000180
- mww phys 0x40048238 0x00000180
- mww phys 0x4004823c 0x00000180
- mww phys 0x40048240 0x00000180
- mww phys 0x40048244 0x00000180
- mww phys 0x40048248 0x00000180
- mww phys 0x4004824c 0x00000180
- mww phys 0x40048250 0x00000180
- mww phys 0x40048254 0x00000180
- mww phys 0x40048258 0x00000180
- mww phys 0x4004825c 0x00000180
- mww phys 0x40048260 0x00000180
- mww phys 0x40048264 0x00000180
- mww phys 0x40048268 0x00000180
- mww phys 0x4004826c 0x00000180
- mww phys 0x40048270 0x00000180
- mww phys 0x40048274 0x00000180
- mww phys 0x40048278 0x00000180
- mww phys 0x4004827c 0x00010180
- mww phys 0x40048280 0x00010180
- mww phys 0x40048284 0x00010180
- mww phys 0x40048288 0x00010180
- mww phys 0x4004828c 0x00010180
- mww phys 0x40048290 0x00010180
- mww phys 0x40048294 0x00010180
- mww phys 0x40048298 0x00010180
- mww phys 0x4004829c 0x00010180
- mww phys 0x400482a0 0x00010180
- mww phys 0x400482a4 0x00010180
- mww phys 0x400482a8 0x00010180
- mww phys 0x400482ac 0x00010180
- mww phys 0x400482b0 0x00010180
- mww phys 0x400482b4 0x00010180
- mww phys 0x400482b8 0x00010180
- mww phys 0x400482bc 0x00010180
- mww phys 0x400482c0 0x00010180
- mww phys 0x400482c4 0x00010180
- mww phys 0x400482c8 0x00010180
- mww phys 0x400482cc 0x00000180
- mww phys 0x400482d0 0x00000180
- mww phys 0x400482d4 0x00000180
- mww phys 0x400482d8 0x00000180
- mww phys 0x4004821c 0x000001a0
- # ddr_ctrl_init
- mww phys 0x400ae000 0x00000600
- mww phys 0x400ae008 0x00000020
- mww phys 0x400ae028 0x00013880
- mww phys 0x400ae02c 0x00030d40
- mww phys 0x400ae030 0x0000050c
- mww phys 0x400ae034 0x15040400
- mww phys 0x400ae038 0x1406040f
- mww phys 0x400ae040 0x04040000
- mww phys 0x400ae044 0x006db00c
- mww phys 0x400ae048 0x00000403
- mww phys 0x400ae050 0x01000000
- mww phys 0x400ae054 0x00060001
- mww phys 0x400ae058 0x000c0000
- mww phys 0x400ae05c 0x03000200
- mww phys 0x400ae060 0x00000006
- mww phys 0x400ae064 0x00010000
- mww phys 0x400ae068 0x0c30002c
- mww phys 0x400ae070 0x00000000
- mww phys 0x400ae074 0x00000003
- mww phys 0x400ae078 0x0000000a
- mww phys 0x400ae07c 0x003001d4
- mww phys 0x400ae084 0x00010000
- mww phys 0x400ae088 0x00050500
- mww phys 0x400ae098 0x00000000
- mww phys 0x400ae09c 0x04001002
- mww phys 0x400ae0a4 0x00000001
- mww phys 0x400ae0c0 0x00460420
- mww phys 0x400ae108 0x01000200
- mww phys 0x400ae10c 0x00000040
- mww phys 0x400ae114 0x00000200
- mww phys 0x400ae118 0x00000040
- mww phys 0x400ae120 0x00000000
- mww phys 0x400ae124 0x0a010300
- mww phys 0x400ae128 0x01014040
- mww phys 0x400ae12c 0x01010101
- mww phys 0x400ae130 0x03030100
- mww phys 0x400ae134 0x01000101
- mww phys 0x400ae138 0x0700000c
- mww phys 0x400ae13c 0x00000000
- mww phys 0x400ae148 0x10000000
- mww phys 0x400ae15c 0x01000000
- mww phys 0x400ae160 0x00040000
- mww phys 0x400ae164 0x00000002
- mww phys 0x400ae16c 0x00020000
- mww phys 0x400ae180 0x00002819
- mww phys 0x400ae184 0x01000000
- mww phys 0x400ae188 0x00000000
- mww phys 0x400ae18c 0x00000000
- mww phys 0x400ae198 0x00000000
- mww phys 0x400ae1a4 0x00000c00
- mww phys 0x400ae1a8 0x00000000
- mww phys 0x400ae1b8 0x0000000c
- mww phys 0x400ae1c8 0x00000000
- mww phys 0x400ae1cc 0x00000000
- mww phys 0x400ae1d4 0x00000000
- mww phys 0x400ae1d8 0x01010000
- mww phys 0x400ae1e0 0x02020000
- mww phys 0x400ae1e4 0x00000202
- mww phys 0x400ae1e8 0x01010064
- mww phys 0x400ae1ec 0x00010101
- mww phys 0x400ae1f0 0x00000064
- mww phys 0x400ae1f8 0x00000800
- mww phys 0x400ae210 0x00000506
- mww phys 0x400ae224 0x00020000
- mww phys 0x400ae228 0x01000000
- mww phys 0x400ae22c 0x04070303
- mww phys 0x400ae230 0x00000040
- mww phys 0x400ae23c 0x06000080
- mww phys 0x400ae240 0x04070303
- mww phys 0x400ae244 0x00000040
- mww phys 0x400ae248 0x00000040
- mww phys 0x400ae24c 0x000f0000
- mww phys 0x400ae250 0x000f0000
- mww phys 0x400ae25c 0x00000101
- mww phys 0x400ae268 0x682c4000
- mww phys 0x400ae26c 0x00000012
- mww phys 0x400ae278 0x00000006
- mww phys 0x400ae284 0x00010202
- mww phys 0x400ae400 0x00002613
- mww phys 0x400ae440 0x00002613
- mww phys 0x400ae404 0x00002615
- mww phys 0x400ae444 0x00002615
- mww phys 0x400ae408 0x00210000
- mww phys 0x400ae448 0x00210000
- mww phys 0x400ae488 0x00210000
- mww phys 0x400ae40c 0x0001012a
- mww phys 0x400ae44c 0x0001012a
- mww phys 0x400ae48c 0x0001012a
- mww phys 0x400ae410 0x00002400
- mww phys 0x400ae450 0x00002400
- mww phys 0x400ae490 0x00002400
- mww phys 0x400ae4c4 0x00000000
- mww phys 0x400ae4c8 0x00001100
- mww phys 0x400ae4d0 0x00010101
- mww phys 0x400ae000 0x00000601
-}
-
-# clock control init, setting up basic
-# clocks
-proc clock_init { } {
- # captured from u-boot
- mww phys 0x4006b040 0xffffffff
- mww phys 0x4006b044 0xffffffff
- mww phys 0x4006b048 0xffffffff
- mww phys 0x4006b04c 0xffffffff
- mww phys 0x4006b050 0xffffffff
- mww phys 0x4006b058 0xffffffff
- mww phys 0x4006b05c 0xffffffff
- mww phys 0x4006b060 0xffffffff
- mww phys 0x4006b064 0xffffffff
- mww phys 0x4006b068 0xffffffff
- mww phys 0x40050030 0x00002001
- mww phys 0x40050270 0x80002001
- mww phys 0x4006b000 0x00011005
- mww phys 0x4006b008 0x0001ff24
- mww phys 0x4006b00c 0x00000810
- mww phys 0x4006b010 0x00cc0000
- mww phys 0x4006b014 0x01000000
- mww phys 0x4006b018 0x20000000
- mww phys 0x4006b01c 0x0000001f
- mww phys 0x4006b020 0x00000000
-}
-
-# This function applies the initial configuration after a "reset init"
-# command
-proc board_init { } {
- clock_init
- ddr_init
-}
-
-# hook the init function into the reset-init event
-${_TARGETNAME}0 configure -event reset-init { board_init }
-# set a slow default JTAG clock, can be overridden later
-adapter_khz 1000
diff --git a/openocd-0.10.0/scripts/board/twr-vf65gs10_cmsisdap.cfg b/openocd-0.10.0/scripts/board/twr-vf65gs10_cmsisdap.cfg
deleted file mode 100644
index e8db75491d5e5ba498b1d64fb5d5062b3c286d99..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/twr-vf65gs10_cmsisdap.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Board configuration file for the Freescale VF65GS10 tower board
-#
-# CMSIS-DAP via USB-OTG connector
-#
-source [find interface/cmsis-dap.cfg]
-
-# only SWD is supported by the CMSIS-DAP on this board
-transport select swd
-
-# Source generic part of twr-vf65gs10 configuration
-source [find board/twr-vf65gs10.cfg]
-
-# override reset configuration
-reset_config srst_only
\ No newline at end of file
diff --git a/openocd-0.10.0/scripts/board/tx25_stk5.cfg b/openocd-0.10.0/scripts/board/tx25_stk5.cfg
deleted file mode 100644
index 846bf58f5c1ec88a0c8e3496d3de8aa68d76f5de..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/tx25_stk5.cfg
+++ /dev/null
@@ -1,158 +0,0 @@
-# -------------------------------------------------------------------------
-# KaRo TX25 CPU Module on a StarterkitV base board
-# http://www.karo-electronics.com/tx25.html
-# -------------------------------------------------------------------------
-
-
-source [find tcl/target/imx25.cfg]
-
- #-------------------------------------------------------------------------
- # Declare Nand
- #-------------------------------------------------------------------------
-
- nand device K9F1G08UOC mxc imx25.cpu mx25 hwecc biswap
-
-
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { tx25_init }
-
-
-proc tx25_init { } {
-
- #-------------------------------------------------------------------------
- # AIPS setup - Only setup MPROTx registers. The PACR default values are good.
- # Set all MPROTx to be non-bufferable, trusted for R/W,
- # not forced to user-mode.
- #-------------------------------------------------------------------------
-
- mww 0x43f00000 0x77777777
- mww 0x43f00004 0x77777777
- mww 0x53f00000 0x77777777
- mww 0x53f00004 0x77777777
-
- sleep 100
-
- #-------------------------------------------------------------------------
- # MAX (Multi-Layer AHB Crossbar Switch) setup
- # MPR - priority for MX25 is (SDHC2/SDMA)>USBOTG>RTIC>IAHB>DAHB
- #-------------------------------------------------------------------------
-
- mww 0x43f04000 0x00043210
- mww 0x43f04100 0x00043210
- mww 0x43f04200 0x00043210
- mww 0x43f04300 0x00043210
- mww 0x43f04400 0x00043210
-
- # SGPCR - always park on last master
- mww 0x43f04010 0x10
- mww 0x43f04110 0x10
- mww 0x43f04210 0x10
- mww 0x43f04310 0x10
- mww 0x43f04410 0x10
-
- # MGPCR - restore default values
- mww 0x43f04800 0x0
- mww 0x43f04900 0x0
- mww 0x43f04a00 0x0
- mww 0x43f04b00 0x0
- mww 0x43f04c00 0x0
-
- # Configure M3IF registers
- # M3IF Control Register (M3IFCTL) for MX25
- # MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
- # MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
- # MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
- # MRRP[3] = USB HOST not on priority list (0 << 3) = 0x00000000
- # MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
- # MRRP[5] = SD/ATA/FEC not on priority list (0 << 5) = 0x00000000
- # MRRP[6] = SCMFBC not on priority list (0 << 6) = 0x00000000
- # MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
- # ----------
- # 0x00000001
- mww 0xb8003000 0x00000001
-
- #-------------------------------------------------------------------------
- # configure ARM CLK
- #-------------------------------------------------------------------------
-
- # Set the Clock CTL (HRM p. 355)
- mww 0x53F80008 0x20034000
-
- # Setup Clock Gating CTL 0-2 (HRM p. 357)
- mww 0x53F8000C 0x1fffffff
- mww 0x53F80010 0xffffffff
- mww 0x53F80014 0x000fdfff
-
- #-------------------------------------------------------------------------
- # SDRAM initialization
- #-------------------------------------------------------------------------
-
- # set to 3.3v SDRAM
- mww 0x43FAC454 0x00000800
-
- # reset (set up ESDMISC)
- mww 0xB8001010 0x00000002
-
- # Setup for SDRAM Bank 0
- #-------------------------------------------------------------------------
-
- # Write ESDCFG0
- mww 0xB8001004 0x00095728
-
- # CTL SMode = Precharge command
- mww 0xB8001000 0x92116480
- mww 0x80000400 0x00000000
-
- # CTL SMode = Auto Refresh command
- mww 0xB8001000 0xA2116480
- mww 0x80000000 0x0
- mww 0x80000000 0x0
- mww 0x80000000 0x0
- mww 0x80000000 0x0
- mww 0x80000000 0x0
- mww 0x80000000 0x0
- mww 0x80000000 0x0
- mww 0x80000000 0x0
-
- # CTL SMode = Load Mode Register command
- mww 0xB8001000 0xB2116480
- mwb 0x80000033 0x00
-
- # CTL SMode = normal
- mww 0xB8001000 0x82116480
-
- # Setup for SDRAM Bank 1
- #-------------------------------------------------------------------------
-
- # Write ESDCFG1
- mww 0xB800100C 0x00095728
-
- # CTL SMode = Precharge command
- mww 0xB8001008 0x92116480
- mww 0x90000400 0x00000000
-
- # CTL SMode = Auto Refresh command
- mww 0xB8001008 0xA2116480
- mww 0x90000000 0x00000000
- mww 0x90000000 0x00000000
- mww 0x90000000 0x00000000
- mww 0x90000000 0x00000000
- mww 0x90000000 0x00000000
- mww 0x90000000 0x00000000
- mww 0x90000000 0x00000000
- mww 0x90000000 0x00000000
-
- # CTL SMode = Load Mode Register command
- mww 0xB8001008 0xB2116480
- mwb 0x90000033 0x00
-
- # CTL SMode = normal
- mww 0xB8001008 0x82116480
-
- # GPIO configuration
- #-------------------------------------------------------------------------
-
- mww 0x43FAC02C 0x00000015
- mww 0x53FD0000 0x01000000
- mww 0x53FD0004 0x00000080
-}
diff --git a/openocd-0.10.0/scripts/board/tx27_stk5.cfg b/openocd-0.10.0/scripts/board/tx27_stk5.cfg
deleted file mode 100644
index bb933e149d39f7e6be83e17d0ae1bddb29f459e9..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/tx27_stk5.cfg
+++ /dev/null
@@ -1,64 +0,0 @@
-# KaRo TX27 CPU Module on a StarterkitV base board
-#
-# http://www.karo-electronics.com/tx27.html
-#
-source [find target/imx27.cfg]
-
-$_TARGETNAME configure -event gdb-attach { reset init }
-$_TARGETNAME configure -event reset-init { tx27_init }
-
-proc tx27_init { } {
- # This setup puts RAM at 0xA0000000
- # init_aipi (AIPI1.PSR0, AIPI2.PSR0, AIPI1.PSR1 and AIPI2.PSR1)
- mww 0x10000000 0x20040304
- mww 0x10020000 0x00000000
- mww 0x10000004 0xDFFBFCFB
- mww 0x10020004 0xFFFFFFFF
-
- sleep 100
-
- #init_max ( PORT0.MPR, #PORT0.AMPR, #PORT1.MPR, #PORT1.AMPR, #PORT2.MPR, #PORT2.AMPR)
- mww 0x1003F000 0x00302145
- mww 0x1003F004 0x00302145
- mww 0x1003F100 0x00302145
- mww 0x1003F104 0x00302145
- mww 0x1003F200 0x00302145
- mww 0x1003F204 0x00302145
-
- #init_drive_strength (#DSCR3, #DSCR5, #DSCR6, #DSCR7, #DSCR8 )
- mww 0x10027828 0x55555555
- mww 0x10027830 0x55555555
- mww 0x10027834 0x55555555
- mww 0x10027838 0x00005005
- mww 0x1002783C 0x15555555
-
- #init_sdram_speed
- #mww 0xD8001010 0x00000004
- mww 0xD8001010 0x00000024
-
- mww 0xD8001004 0x00395729
-
- mww 0xD8001000 0x92120000
- mww 0xA0000400 0x0
-
- mww 0xD8001000 0xA2120000
- mww 0xA0000000 0x0
- mww 0xA0000000 0x0
-
- mww 0xD8001000 0xB2120000
- mdb 0xA0000000
- mdb 0xA0000033
-
- mww 0xD8001000 0x82126485
-
- # =============================================
- # Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz)
- # =============================================
- mww 0xD8002000 0x23524E80
- mww 0xD8002004 0x10000D03
- mww 0xD8002008 0x00720900
-
- nand probe 0
-}
-
-nand device tx27.nand mxc $_TARGETNAME mx27 hwecc biswap
diff --git a/openocd-0.10.0/scripts/board/unknown_at91sam9260.cfg b/openocd-0.10.0/scripts/board/unknown_at91sam9260.cfg
deleted file mode 100644
index de49a69f567ab58e71305e1cc042238eea2c5436..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/unknown_at91sam9260.cfg
+++ /dev/null
@@ -1,97 +0,0 @@
-# Thanks to Pieter Conradie for this script!
-#
-# Unknown vendor board contains:
-#
-# Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz
-# OSCSEL configured for internal RC oscillator (22 to 42 kHz)
-#
-# 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit
-# 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks
-##################################################################
-
-# We add to the minimal configuration.
-source [find target/at91sam9260.cfg]
-
-$_TARGETNAME configure -event reset-start {
- # At reset CPU runs at 22 to 42 kHz.
- # JTAG Frequency must be 6 times slower.
- jtag_rclk 3
- halt
- # RSTC_MR : enable user reset, MMU may be enabled... use physical address
- mww phys 0xfffffd08 0xa5000501
-}
-
-
-$_TARGETNAME configure -event reset-init {
- mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
-
- mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
- sleep 20 ;# wait 20 ms
- mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
- sleep 10 ;# wait 10 ms
- mww 0xfffffc28 0x205dbf09 ;# CKGR_PLLAR: Set PLLA Register for 192.512MHz
- sleep 20 ;# wait 20 ms
- mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
- sleep 10 ;# wait 10 ms
- mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected (96.256 MHz)
- sleep 10 ;# wait 10 ms
-
- # Increase JTAG Speed to 6 MHz if RCLK is not supported
- jtag_rclk 6000
-
- arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
-
- mww 0xffffec00 0x01020102 ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
- mww 0xffffec04 0x09070806 ;# SMC_PULSE0
- mww 0xffffec08 0x000d000b ;# SMC_CYCLE0
- mww 0xffffec0c 0x00001003 ;# SMC_MODE0
-
- flash probe 0 ;# Identify flash bank 0
-
- mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
- mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
- mww 0xfffff860 0xffff0000 ;# PIO_PUDR : Disable D15..D31 pull-ups
-
- mww 0xffffef1c 0x00010102 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
- # VDDIOMSEL set for +3V3 memory
- # Disable D0..D15 pull-ups
-
- mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
-
- mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
- mww 0x20000000 0
- mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
- mww 0x20000000 0
- mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
- mww 0x20000000 0
- mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
- mww 0x20000000 0
- mww 0xffffea04 0x2a2 ;# SDRAMC_TR : Set refresh timer count to 7us
-}
-
-
-#####################
-# Flash configuration
-#####################
-
-#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
-
-
diff --git a/openocd-0.10.0/scripts/board/uptech_2410.cfg b/openocd-0.10.0/scripts/board/uptech_2410.cfg
deleted file mode 100644
index 950f2a7c1b0bf656dd05e23e4e7b2038900bc131..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/uptech_2410.cfg
+++ /dev/null
@@ -1,65 +0,0 @@
-# Target Configuration for the Uptech 2410 board.
-# This configuration hould also work on smdk2410, but I havn't tested it yet.
-# Author: xionglingfeng@Gmail.com
-
-source [find target/samsung_s3c2410.cfg]
-
-$_TARGETNAME configure -event reset-init { uptech2410_init }
-$_TARGETNAME configure -event gdb-attach { reset init }
-
-proc init_pll_sdram { } {
- #echo "---------- Initializing PLL and SDRAM ---------"
- #watchdog timer disable
- mww phys 0x53000000 0x00000000
-
- #disable all interrupts
- mww phys 0x4a000008 0xffffffff
-
- #disable all sub-interrupts
- mww phys 0x4a00001c 0x000007ff
-
- #clear all source pending bits
- mww phys 0x4a000000 0xffffffff
-
- #clear all sub-source pending bits
- mww phys 0x4a000018 0x000007ff
-
- #clear interrupt pending bit
- mww phys 0x4a000010 0xffffffff
-
- #PLL locktime counter
- mww phys 0x4c000000 0x00ffffff
-
- #Fin=12MHz Fout=202.8MHz
- #mww phys 0x4c000004 0x000a1031
-
- #FCLK:HCLK:PCLK = 1:2:4
- mww phys 0x4c000014 0x00000003
-
-
- mww phys 0x48000000 0x11111110
- mww phys 0x48000004 0x00007FFC
- mww phys 0x48000008 0x00007FFC
- mww phys 0x4800000c 0x00000700
- mww phys 0x48000010 0x00000700
- mww phys 0x48000014 0x00002E50
- mww phys 0x48000018 0x00002E50
- mww phys 0x4800001c 0x00018005
- mww phys 0x48000020 0x00018005
- mww phys 0x48000024 0x008c04e9
- mww phys 0x48000028 0x000000b2
- mww phys 0x4800002c 0x00000030
- mww phys 0x48000030 0x00000030
-}
-
-proc uptech2410_init { } {
- init_pll_sdram
- #echo "---------- Probing Nand flash ----------"
- nand probe 0
- #echo "---------- Enable some functions ----------"
-}
-
-set _NANDNAME $_CHIPNAME.nand
-nand device $_NANDNAME s3c2410 $_TARGETNAME
-
-
diff --git a/openocd-0.10.0/scripts/board/verdex.cfg b/openocd-0.10.0/scripts/board/verdex.cfg
deleted file mode 100644
index 6da98752893a7093ce2e7f413aa6b41b477eea85..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/verdex.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-# Config for Gumstix Verdex XM4 and XL6P (PXA270)
-
-set CHIPNAME verdex
-source [find target/pxa270.cfg]
-
-# The board supports separate reset lines
-# Override this in the interface config for parallel dongles
-reset_config trst_and_srst separate
-
-# XM4 = 400MHz, XL6P = 600MHz...let's run at 0.1*400MHz=40MHz
-adapter_khz 40000
-
-# flash bank <driver> <base> <size> <chip_width> <bus_width>
-# XL6P has 32 MB flash
-flash bank $_CHIPNAME.flash0 cfi 0x00000000 0x02000000 2 2 $_TARGETNAME
-# XM4 has 16 MB flash
-#flash bank $_CHIPNAME.flash0 cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/voipac.cfg b/openocd-0.10.0/scripts/board/voipac.cfg
deleted file mode 100644
index c59277ec43720609b287b70d15ccb1eed9d16dbb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/voipac.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-# Config for Voipac PXA270/PXA270M module.
-
-set CHIPNAME voipac
-source [find target/pxa270.cfg]
-
-# The board supports separate reset lines
-# Override this in the interface config for parallel dongles
-reset_config trst_and_srst separate
-
-# flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank $_CHIPNAME.flash0 cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
-flash bank $_CHIPNAME.flash1 cfi 0x02000000 0x2000000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/board/voltcraft_dso-3062c.cfg b/openocd-0.10.0/scripts/board/voltcraft_dso-3062c.cfg
deleted file mode 100644
index 01e37e9a4d9785dcf17c3c0452868991ba5ab38a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/voltcraft_dso-3062c.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# Voltcraft DSO-3062C digital oscilloscope (uses a Samsung S3C2440)
-#
-# http://www.eevblog.com/forum/general-chat/hantek-tekway-dso-hack-get-200mhz-bw-for-free/
-# http://www.mikrocontroller.net/topic/249628
-# http://elinux.org/Das_Oszi
-# http://randomprojects.org/wiki/Voltcraft_DSO-3062C
-#
-
-# Enable this if your JTAG adapter supports multiple transports (JTAG or SWD).
-# Otherwise comment it out, as it will cause an OpenOCD error.
-### transport select jtag
-
-source [find target/samsung_s3c2440.cfg]
-
-adapter_khz 16000
-
-# Samsung K9F1208U0C NAND flash chip (64MiB, 3.3V, 8-bit)
-nand device $_CHIPNAME.nand s3c2440 $_TARGETNAME
-
-# arm7_9 fast_memory_access enable
-# arm7_9 dcc_downloads enable
-
-init
-reset
-halt
-scan_chain
-targets
-nand probe 0
-nand list
-
diff --git a/openocd-0.10.0/scripts/board/x300t.cfg b/openocd-0.10.0/scripts/board/x300t.cfg
deleted file mode 100644
index 9d9a320fbbc57234004969b61f2b92bd8ddc064d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/x300t.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# This is for the T-Home X300T / X301T IPTV box,
-# which are based on IPTV reference designs from Kiss/Cisco KMM-3***
-#
-# It has Sigma Designs SMP8634 chip.
-source [find target/smp8634.cfg]
-
-$_TARGETNAME configure -event reset-init { x300t_init }
-
-# 1MB CFI capable flash
-# flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0xac000000 0x100000 2 2 $_TARGETNAME
-
-proc x300t_init { } {
- # Setup SDRAM config and flash mapping
- # initialize ram
- mww 0xa003fffc 3
- mww 0xa003fffc 2
- mww 0xa0030000 0xE34111BA
- mww 0xa003fffc 0xa4444
- mww 0xa003fffc 0
-
- # remap boot vector in CPU local RAM
- mww 0xa006f000 0x60000
-
- # map flash to CPU address space REG_BASE_cpu_block+CPU_remap4
- mww 0x0006f010 0x48000000
-
- # map flash addr to REG_BASE_cpu_block + LR_XENV_LOCATION (normally done by XOS)
- mww 0x00061ff0 0x48000000
-}
diff --git a/openocd-0.10.0/scripts/board/xmc-2go.cfg b/openocd-0.10.0/scripts/board/xmc-2go.cfg
deleted file mode 100644
index 90dbf43660c373034fb60a52908260544acc5839..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/xmc-2go.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Infineon XMC 2Go
-#
-
-#
-# Segger J-Link Lite XMC4200 on-board
-#
-source [find interface/jlink.cfg]
-transport select swd
-
-set CHIPNAME xmc1100
-set WORKAREASIZE 0x4000
-source [find target/xmc1xxx.cfg]
-
-reset_config srst_only srst_nogate
diff --git a/openocd-0.10.0/scripts/board/xmc1100-boot-kit.cfg b/openocd-0.10.0/scripts/board/xmc1100-boot-kit.cfg
deleted file mode 100644
index 5e7c607344766a8618a27a0a4923ecdd727404fd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/xmc1100-boot-kit.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Infineon XMC1100 Boot Kit
-#
-
-#
-# Segger J-Link Lite XMC4200 on-board
-#
-source [find interface/jlink.cfg]
-transport select swd
-
-set CHIPNAME xmc1100
-set WORKAREASIZE 0x4000
-source [find target/xmc1xxx.cfg]
-
-reset_config srst_only srst_nogate
diff --git a/openocd-0.10.0/scripts/board/xmc4200-application-kit-actuator.cfg b/openocd-0.10.0/scripts/board/xmc4200-application-kit-actuator.cfg
deleted file mode 100644
index 4e3dde8d76480b47ca36514af7109253ac84b1e5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/xmc4200-application-kit-actuator.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Infineon XMC4200 Application Kit - Actuator
-#
-
-#
-# Segger J-Link Lite XMC4200 on-board
-#
-source [find interface/jlink.cfg]
-transport select swd
-
-set CHIPNAME xmc4200
-source [find target/xmc4xxx.cfg]
diff --git a/openocd-0.10.0/scripts/board/xmc4300-relax.cfg b/openocd-0.10.0/scripts/board/xmc4300-relax.cfg
deleted file mode 100644
index bb46ccfd97e9df2a39867f8ebbbe3dcbb09d2866..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/xmc4300-relax.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Infineon XMC4300 Relax EtherCAT Kit
-#
-
-#
-# Segger J-Link Lite XMC4200 on-board
-#
-source [find interface/jlink.cfg]
-transport select swd
-
-set CHIPNAME xmc4300
-source [find target/xmc4xxx.cfg]
diff --git a/openocd-0.10.0/scripts/board/xmc4500-application-kit-general.cfg b/openocd-0.10.0/scripts/board/xmc4500-application-kit-general.cfg
deleted file mode 100644
index 47c8b9982a91dd6ec7cbb64b4de85d72e701bbc1..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/xmc4500-application-kit-general.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Infineon XMC4500 Application Kit - General Purpose
-#
-
-set CHIPNAME xmc4500
-source [find target/xmc4xxx.cfg]
-
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/board/xmc4500-application-kit-sdram.cfg b/openocd-0.10.0/scripts/board/xmc4500-application-kit-sdram.cfg
deleted file mode 100644
index fe44d01a90d604da146ccb5e3aa27f8af1ee6185..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/xmc4500-application-kit-sdram.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Infineon XMC4500 Application Kit - SDRAM
-#
-
-#
-# Segger J-Link Lite XMC4200 on-board
-#
-
-set CHIPNAME xmc4500
-source [find target/xmc4xxx.cfg]
diff --git a/openocd-0.10.0/scripts/board/xmc4500-relax.cfg b/openocd-0.10.0/scripts/board/xmc4500-relax.cfg
deleted file mode 100644
index 1753b24c1eb83e2e95a963b388c583849af0b486..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/xmc4500-relax.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Infineon XMC4500 Relax Kit / Relax Lite Kit
-#
-
-#
-# Segger J-Link Lite XMC4500 on-board
-#
-source [find interface/jlink.cfg]
-transport select swd
-
-# There's also an unpopulated 10-pin 0.05" pinout.
-
-set CHIPNAME xmc4500
-source [find target/xmc4xxx.cfg]
diff --git a/openocd-0.10.0/scripts/board/xmc4700-relax.cfg b/openocd-0.10.0/scripts/board/xmc4700-relax.cfg
deleted file mode 100644
index 29953f6347bfb7d5c846aedc9c8af3ed16033976..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/xmc4700-relax.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# Infineon XMC4700 Relax Lite Kit / Relax Kit for 5V Shields / Relax Kit
-#
-
-#
-# Segger J-Link Lite XMC4200 on-board
-#
-source [find interface/jlink.cfg]
-transport select swd
-
-# There's also an unpopulated 10-pin 0.05" pinout.
-
-set CHIPNAME xmc4700
-source [find target/xmc4xxx.cfg]
-
-# Relax Kit only: N25Q032A qSPI flash
diff --git a/openocd-0.10.0/scripts/board/xmc4800-relax.cfg b/openocd-0.10.0/scripts/board/xmc4800-relax.cfg
deleted file mode 100644
index fa3fc8f3fb653177c13de9d498e5cc9b941e044e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/xmc4800-relax.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# Infineon XMC4800 Relax EtherCAT Kit
-#
-
-#
-# Segger J-Link Lite XMC4200 on-board
-#
-source [find interface/jlink.cfg]
-transport select swd
-
-# There's also an unpopulated 10-pin 0.05" pinout.
-
-set CHIPNAME xmc4800
-source [find target/xmc4xxx.cfg]
-
-# N25Q032A qSPI flash
diff --git a/openocd-0.10.0/scripts/board/xmos_xk-xac-xa8_arm.cfg b/openocd-0.10.0/scripts/board/xmos_xk-xac-xa8_arm.cfg
deleted file mode 100644
index 3d12afb2c5c0f45739b10c697ae651523d1575c2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/xmos_xk-xac-xa8_arm.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# xCORE-XA Core Module
-#
-# https://www.xmos.com/support/boards?product=17940
-#
-
-#
-# J-Link OB STM32F103
-#
-source [find interface/jlink.cfg]
-transport select swd
-
-#
-# XS1-XAU8A-10
-#
-source [find target/xmos_xs1-xau8a-10_arm.cfg]
diff --git a/openocd-0.10.0/scripts/board/zy1000.cfg b/openocd-0.10.0/scripts/board/zy1000.cfg
deleted file mode 100644
index 57deaa8375f327aebfab1f321d1c5e5040e613fe..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/board/zy1000.cfg
+++ /dev/null
@@ -1,117 +0,0 @@
-#Script for ZY1000
-
-#Atmel ties SRST & TRST together, at which point it makes
-#no sense to use TRST, but use TMS instead.
-#
-#The annoying thing with tying SRST & TRST together is that
-#there is no way to halt the CPU *before and during* the
-#SRST reset, which means that the CPU will run a number
-#of cycles before it can be halted(as much as milliseconds).
-reset_config srst_only srst_pulls_trst
-
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME zy1000
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x1f0f0f0f
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# at CPU CLK <32kHz this must be disabled
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x01000000 0x200000 2 2 $_TARGETNAME
-
-$_TARGETNAME configure -event reset-init {
- # Set up chip selects & timings
- mww 0xFFE00000 0x0100273D
- mww 0xFFE00004 0x08002125
- mww 0xFFEe0008 0x02002125
- mww 0xFFE0000c 0x03002125
- mww 0xFFE00010 0x40000000
- mww 0xFFE00014 0x50000000
- mww 0xFFE00018 0x60000000
- mww 0xFFE0001c 0x70000000
- mww 0xFFE00020 0x00000001
- mww 0xFFE00024 0x00000000
-
- # remap
- mww 0xFFFFF124 0xFFFFFFFF
- mww 0xffff0010 0x100
- mww 0xffff0034 0x100
-
- #disable 16x5x UART interrupts
- mww 0x08020004 0
-}
-
-$_TARGETNAME configure -event gdb-attach {
- # Without this gdb-attach will first time as probe will fail
- reset init
-}
-
-# required for usable performance. Used for lots of
-# other things than flash programming.
-$_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
-
-adapter_khz 16000
-
-
-proc production_info {} {
- return "Serial number is official MAC number. Format XXXXXXXXXXXX"
-}
-
-# There is no return value from this procedure. If it is
-# successful it does not throw an exception
-#
-# Progress messages are output via puts
-proc production {firmwarefile serialnumber} {
- if {[string length $serialnumber]!=12} {
- echo "Invalid serial number"
- return
- }
-
- echo "Power cycling target"
- power off
- sleep 3000
- power on
- sleep 1000
- reset init
- flash write_image erase $firmwarefile 0x1000000 bin
- verify_image $firmwarefile 0x1000000 bin
-
- # Big endian... weee!!!!
- echo "Setting MAC number to $serialnumber"
- flash fillw [expr 0x1030000-0x8] "0x[string range $serialnumber 2 3][string range $serialnumber 0 1]0000" 1
- flash fillw [expr 0x1030000-0x4] "0x[string range $serialnumber 10 11][string range $serialnumber 8 9][string range $serialnumber 6 7][string range $serialnumber 4 5]" 1
- echo "Production successful"
-}
-
-
-proc production_test {} {
- power on
- sleep 1000
- target_request debugmsgs enable
- reset run
- sleep 25000
- target_request debugmsgs disable
- return "See IP address above..."
-}
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/aic.tcl b/openocd-0.10.0/scripts/chip/atmel/at91/aic.tcl
deleted file mode 100644
index 6dae36ad663d33c993ad21aa5dc32cb3ff4091e5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/aic.tcl
+++ /dev/null
@@ -1,101 +0,0 @@
-set AIC_SMR [expr $AT91C_BASE_AIC + 0x00000000 ]
-global AIC_SMR
-set AIC_SVR [expr $AT91C_BASE_AIC + 0x00000080 ]
-global AIC_SVR
-set AIC_IVR [expr $AT91C_BASE_AIC + 0x00000100 ]
-global AIC_IVR
-set AIC_FVR [expr $AT91C_BASE_AIC + 0x00000104 ]
-global AIC_FVR
-set AIC_ISR [expr $AT91C_BASE_AIC + 0x00000108 ]
-global AIC_ISR
-set AIC_IPR [expr $AT91C_BASE_AIC + 0x0000010C ]
-global AIC_IPR
-set AIC_IMR [expr $AT91C_BASE_AIC + 0x00000110 ]
-global AIC_IMR
-set AIC_CISR [expr $AT91C_BASE_AIC + 0x00000114 ]
-global AIC_CISR
-set AIC_IECR [expr $AT91C_BASE_AIC + 0x00000120 ]
-global AIC_IECR
-set AIC_IDCR [expr $AT91C_BASE_AIC + 0x00000124 ]
-global AIC_IDCR
-set AIC_ICCR [expr $AT91C_BASE_AIC + 0x00000128 ]
-global AIC_ICCR
-set AIC_ISCR [expr $AT91C_BASE_AIC + 0x0000012C ]
-global AIC_ISCR
-set AIC_EOICR [expr $AT91C_BASE_AIC + 0x00000130 ]
-global AIC_EOICR
-set AIC_SPU [expr $AT91C_BASE_AIC + 0x00000134 ]
-global AIC_SPU
-set AIC_DCR [expr $AT91C_BASE_AIC + 0x00000138 ]
-global AIC_DCR
-set AIC_FFER [expr $AT91C_BASE_AIC + 0x00000140 ]
-global AIC_FFER
-set AIC_FFDR [expr $AT91C_BASE_AIC + 0x00000144 ]
-global AIC_FFDR
-set AIC_FFSR [expr $AT91C_BASE_AIC + 0x00000148 ]
-global AIC_FFSR
-
-
-proc aic_enable_disable_list { VAL ENAME DNAME } {
- global AT91C_ID
-
- show_mmr32_bits AT91C_ID $VAL
-
-}
-
-proc show_AIC_IPR_helper { NAME ADDR VAL } {
- aic_enable_disable_list $VAL "IRQ PENDING" "irq not-pending"
-}
-
-proc show_AIC_IMR_helper { NAME ADDR VAL } {
- aic_enable_disable_list $VAL "IRQ ENABLED" "irq disabled"
-}
-
-
-proc show_AIC { } {
- global AIC_SMR
- if [catch { mem2array aaa 32 $AIC_SMR [expr 32 * 4] } msg ] {
- error [format "%s (%s)" $msg AIC_SMR]
- }
- echo "AIC_SMR: Mode & Type"
- global AT91C_ID
- for { set x 0 } { $x < 32 } { } {
- echo -n " "
- echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
- incr x
- echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
- incr x
- echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
- incr x
- echo [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) $aaa($x)]
- incr x
- }
- global AIC_SVR
- if [catch { mem2array aaa 32 $AIC_SVR [expr 32 * 4] } msg ] {
- error [format "%s (%s)" $msg AIC_SVR]
- }
- echo "AIC_SVR: Vectors"
- for { set x 0 } { $x < 32 } { } {
- echo -n " "
- echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
- incr x
- echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
- incr x
- echo -n [format "%2d: %5s 0x%08x | " $x $AT91C_ID($x) $aaa($x)]
- incr x
- echo [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) $aaa($x)]
- incr x
- }
-
- foreach REG {
- AIC_IVR AIC_FVR AIC_ISR
- AIC_IPR AIC_IMR AIC_CISR AIC_IECR AIC_IDCR
- AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU AIC_DCR
- AIC_FFER AIC_FFDR AIC_FFSR } {
- if [catch { show_mmr32_reg $REG } msg ] {
- error $msg
- break
- }
- }
-}
-
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/at91_pio.cfg b/openocd-0.10.0/scripts/chip/atmel/at91/at91_pio.cfg
deleted file mode 100644
index 2373c19fe9e9c64419711106b47941c3057c43d8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/at91_pio.cfg
+++ /dev/null
@@ -1,29 +0,0 @@
-set PIO_PER 0x00 ;# Enable Register
-set PIO_PDR 0x04 ;# Disable Register
-set PIO_PSR 0x08 ;# Status Register
-set PIO_OER 0x10 ;# Output Enable Register
-set PIO_ODR 0x14 ;# Output Disable Register
-set PIO_OSR 0x18 ;# Output Status Register
-set PIO_IFER 0x20 ;# Glitch Input Filter Enable
-set PIO_IFDR 0x24 ;# Glitch Input Filter Disable
-set PIO_IFSR 0x28 ;# Glitch Input Filter Status
-set PIO_SODR 0x30 ;# Set Output Data Register
-set PIO_CODR 0x34 ;# Clear Output Data Register
-set PIO_ODSR 0x38 ;# Output Data Status Register
-set PIO_PDSR 0x3c ;# Pin Data Status Register
-set PIO_IER 0x40 ;# Interrupt Enable Register
-set PIO_IDR 0x44 ;# Interrupt Disable Register
-set PIO_IMR 0x48 ;# Interrupt Mask Register
-set PIO_ISR 0x4c ;# Interrupt Status Register
-set PIO_MDER 0x50 ;# Multi-driver Enable Register
-set PIO_MDDR 0x54 ;# Multi-driver Disable Register
-set PIO_MDSR 0x58 ;# Multi-driver Status Register
-set PIO_PUDR 0x60 ;# Pull-up Disable Register
-set PIO_PUER 0x64 ;# Pull-up Enable Register
-set PIO_PUSR 0x68 ;# Pull-up Status Register
-set PIO_ASR 0x70 ;# Peripheral A Select Register
-set PIO_BSR 0x74 ;# Peripheral B Select Register
-set PIO_ABSR 0x78 ;# AB Status Register
-set PIO_OWER 0xa0 ;# Output Write Enable Register
-set PIO_OWDR 0xa4 ;# Output Write Disable Register
-set PIO_OWSR 0xa8 ;# Output Write Status Register
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/at91_pmc.cfg b/openocd-0.10.0/scripts/chip/atmel/at91/at91_pmc.cfg
deleted file mode 100644
index 88b137024adedd7faf57c4f93554f277433e2adc..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/at91_pmc.cfg
+++ /dev/null
@@ -1,113 +0,0 @@
-set AT91_PMC_SCER [expr ($AT91_PMC + 0x00)] ;# System Clock Enable Register
-set AT91_PMC_SCDR [expr ($AT91_PMC + 0x04)] ;# System Clock Disable Register
-
-set AT91_PMC_SCSR [expr ($AT91_PMC + 0x08)] ;# System Clock Status Register
-set AT91_PMC_PCK [expr (1 << 0)] ;# Processor Clock
-set AT91RM9200_PMC_UDP [expr (1 << 1)] ;# USB Devcice Port Clock [AT91RM9200 only]
-set AT91RM9200_PMC_MCKUDP [expr (1 << 2)] ;# USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only]
-set AT91CAP9_PMC_DDR [expr (1 << 2)] ;# DDR Clock [CAP9 revC & some SAM9 only]
-set AT91RM9200_PMC_UHP [expr (1 << 4)] ;# USB Host Port Clock [AT91RM9200 only]
-set AT91SAM926x_PMC_UHP [expr (1 << 6)] ;# USB Host Port Clock [AT91SAM926x only]
-set AT91CAP9_PMC_UHP [expr (1 << 6)] ;# USB Host Port Clock [AT91CAP9 only]
-set AT91SAM926x_PMC_UDP [expr (1 << 7)] ;# USB Devcice Port Clock [AT91SAM926x only]
-set AT91_PMC_PCK0 [expr (1 << 8)] ;# Programmable Clock 0
-set AT91_PMC_PCK1 [expr (1 << 9)] ;# Programmable Clock 1
-set AT91_PMC_PCK2 [expr (1 << 10)] ;# Programmable Clock 2
-set AT91_PMC_PCK3 [expr (1 << 11)] ;# Programmable Clock 3
-set AT91_PMC_HCK0 [expr (1 << 16)] ;# AHB Clock (USB host) [AT91SAM9261 only]
-set AT91_PMC_HCK1 [expr (1 << 17)] ;# AHB Clock (LCD) [AT91SAM9261 only]
-
-set AT91_PMC_PCER [expr ($AT91_PMC + 0x10)] ;# Peripheral Clock Enable Register
-set AT91_PMC_PCDR [expr ($AT91_PMC + 0x14)] ;# Peripheral Clock Disable Register
-set AT91_PMC_PCSR [expr ($AT91_PMC + 0x18)] ;# Peripheral Clock Status Register
-
-set AT91_CKGR_UCKR [expr ($AT91_PMC + 0x1C)] ;# UTMI Clock Register [some SAM9, CAP9]
-set AT91_PMC_UPLLEN [expr (1 << 16)] ;# UTMI PLL Enable
-set AT91_PMC_UPLLCOUNT [expr (0xf << 20)] ;# UTMI PLL Start-up Time
-set AT91_PMC_BIASEN [expr (1 << 24)] ;# UTMI BIAS Enable
-set AT91_PMC_BIASCOUNT [expr (0xf << 28)] ;# UTMI BIAS Start-up Time
-
-set AT91_CKGR_MOR [expr ($AT91_PMC + 0x20)] ;# Main Oscillator Register [not on SAM9RL]
-set AT91_PMC_MOSCEN [expr (1 << 0)] ;# Main Oscillator Enable
-set AT91_PMC_OSCBYPASS [expr (1 << 1)] ;# Oscillator Bypass [SAM9x, CAP9]
-set AT91_PMC_OSCOUNT [expr (0xff << 8)] ;# Main Oscillator Start-up Time
-
-set AT91_CKGR_MCFR [expr ($AT91_PMC + 0x24)] ;# Main Clock Frequency Register
-set AT91_PMC_MAINF [expr (0xffff << 0)] ;# Main Clock Frequency
-set AT91_PMC_MAINRDY [expr (1 << 16)] ;# Main Clock Ready
-
-set AT91_CKGR_PLLAR [expr ($AT91_PMC + 0x28)] ;# PLL A Register
-set AT91_CKGR_PLLBR [expr ($AT91_PMC + 0x2c)] ;# PLL B Register
-set AT91_PMC_DIV [expr (0xff << 0)] ;# Divider
-set AT91_PMC_PLLCOUNT [expr (0x3f << 8)] ;# PLL Counter
-set AT91_PMC_OUT [expr (3 << 14)] ;# PLL Clock Frequency Range
-set AT91_PMC_MUL [expr (0x7ff << 16)] ;# PLL Multiplier
-set AT91_PMC_USBDIV [expr (3 << 28)] ;# USB Divisor (PLLB only)
-set AT91_PMC_USBDIV_1 [expr (0 << 28)]
-set AT91_PMC_USBDIV_2 [expr (1 << 28)]
-set AT91_PMC_USBDIV_4 [expr (2 << 28)]
-set AT91_PMC_USB96M [expr (1 << 28)] ;# Divider by 2 Enable (PLLB only)
-set AT91_PMC_PLLA_WR_ERRATA [expr (1 << 29)] ;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register
-
-set AT91_PMC_MCKR [expr ($AT91_PMC + 0x30)] ;# Master Clock Register
-set AT91_PMC_CSS [expr (3 << 0)] ;# Master Clock Selection
-set AT91_PMC_CSS_SLOW [expr (0 << 0)]
-set AT91_PMC_CSS_MAIN [expr (1 << 0)]
-set AT91_PMC_CSS_PLLA [expr (2 << 0)]
-set AT91_PMC_CSS_PLLB [expr (3 << 0)]
-set AT91_PMC_CSS_UPLL [expr (3 << 0)] ;# [some SAM9 only]
-set AT91_PMC_PRES [expr (7 << 2)] ;# Master Clock Prescaler
-set AT91_PMC_PRES_1 [expr (0 << 2)]
-set AT91_PMC_PRES_2 [expr (1 << 2)]
-set AT91_PMC_PRES_4 [expr (2 << 2)]
-set AT91_PMC_PRES_8 [expr (3 << 2)]
-set AT91_PMC_PRES_16 [expr (4 << 2)]
-set AT91_PMC_PRES_32 [expr (5 << 2)]
-set AT91_PMC_PRES_64 [expr (6 << 2)]
-set AT91_PMC_MDIV [expr (3 << 8)] ;# Master Clock Division
-set AT91RM9200_PMC_MDIV_1 [expr (0 << 8)] ;# [AT91RM9200 only]
-set AT91RM9200_PMC_MDIV_2 [expr (1 << 8)]
-set AT91RM9200_PMC_MDIV_3 [expr (2 << 8)]
-set AT91RM9200_PMC_MDIV_4 [expr (3 << 8)]
-set AT91SAM9_PMC_MDIV_1 [expr (0 << 8)] ;# [SAM9,CAP9 only]
-set AT91SAM9_PMC_MDIV_2 [expr (1 << 8)]
-set AT91SAM9_PMC_MDIV_4 [expr (2 << 8)]
-set AT91SAM9_PMC_MDIV_6 [expr (3 << 8)] ;# [some SAM9 only]
-set AT91SAM9_PMC_MDIV_3 [expr (3 << 8)] ;# [some SAM9 only]
-set AT91_PMC_PDIV [expr (1 << 12)] ;# Processor Clock Division [some SAM9 only]
-set AT91_PMC_PDIV_1 [expr (0 << 12)]
-set AT91_PMC_PDIV_2 [expr (1 << 12)]
-set AT91_PMC_PLLADIV2 [expr (1 << 12)] ;# PLLA divisor by 2 [some SAM9 only]
-set AT91_PMC_PLLADIV2_OFF [expr (0 << 12)]
-set AT91_PMC_PLLADIV2_ON [expr (1 << 12)]
-
-set AT91_PMC_USB [expr ($AT91_PMC + 0x38)] ;# USB Clock Register [some SAM9 only]
-set AT91_PMC_USBS [expr (0x1 << 0)] ;# USB OHCI Input clock selection
-set AT91_PMC_USBS_PLLA [expr (0 << 0)]
-set AT91_PMC_USBS_UPLL [expr (1 << 0)]
-set AT91_PMC_OHCIUSBDIV [expr (0xF << 8)] ;# Divider for USB OHCI Clock
-
-;# set AT91_PMC_PCKR(n) [expr ($AT91_PMC + 0x40 + ((n) * 4))] ;# Programmable Clock 0-N Registers
-set AT91_PMC_CSSMCK [expr (0x1 << 8)] ;# CSS or Master Clock Selection
-set AT91_PMC_CSSMCK_CSS [expr (0 << 8)]
-set AT91_PMC_CSSMCK_MCK [expr (1 << 8)]
-
-set AT91_PMC_IER [expr ($AT91_PMC + 0x60)] ;# Interrupt Enable Register
-set AT91_PMC_IDR [expr ($AT91_PMC + 0x64)] ;# Interrupt Disable Register
-set AT91_PMC_SR [expr ($AT91_PMC + 0x68)] ;# Status Register
-set AT91_PMC_MOSCS [expr (1 << 0)] ;# MOSCS Flag
-set AT91_PMC_LOCKA [expr (1 << 1)] ;# PLLA Lock
-set AT91_PMC_LOCKB [expr (1 << 2)] ;# PLLB Lock
-set AT91_PMC_MCKRDY [expr (1 << 3)] ;# Master Clock
-set AT91_PMC_LOCKU [expr (1 << 6)] ;# UPLL Lock [some SAM9, AT91CAP9 only]
-set AT91_PMC_OSCSEL [expr (1 << 7)] ;# Slow Clock Oscillator [AT91CAP9 revC only]
-set AT91_PMC_PCK0RDY [expr (1 << 8)] ;# Programmable Clock 0
-set AT91_PMC_PCK1RDY [expr (1 << 9)] ;# Programmable Clock 1
-set AT91_PMC_PCK2RDY [expr (1 << 10)] ;# Programmable Clock 2
-set AT91_PMC_PCK3RDY [expr (1 << 11)] ;# Programmable Clock 3
-set AT91_PMC_IMR [expr ($AT91_PMC + 0x6c)] ;# Interrupt Mask Register
-
-set AT91_PMC_PROT [expr ($AT91_PMC + 0xe4)] ;# Protect Register [AT91CAP9 revC only]
-set AT91_PMC_PROTKEY 0x504d4301 ;# Activation Code
-
-set AT91_PMC_VER [expr ($AT91_PMC + 0xfc)] ;# PMC Module Version [AT91CAP9 only]
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/at91_rstc.cfg b/openocd-0.10.0/scripts/chip/atmel/at91/at91_rstc.cfg
deleted file mode 100644
index ed6082227801c742bc4257e2d64d1b91e321adb1..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/at91_rstc.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-set AT91_RSTC_CR [expr ($AT91_RSTC + 0x00)] ;# Reset Controller Control Register
-set AT91_RSTC_PROCRST [expr (1 << 0)] ;# Processor Reset
-set AT91_RSTC_PERRST [expr (1 << 2)] ;# Peripheral Reset
-set AT91_RSTC_EXTRST [expr (1 << 3)] ;# External Reset
-set AT91_RSTC_KEY [expr (0xa5 << 24)] ;# KEY Password
-
-set AT91_RSTC_SR [expr ($AT91_RSTC + 0x04)] ;# Reset Controller Status Register
-set AT91_RSTC_URSTS [expr (1 << 0)] ;# User Reset Status
-set AT91_RSTC_RSTTYP [expr (7 << 8)] ;# Reset Type
-set AT91_RSTC_RSTTYP_GENERAL [expr (0 << 8)]
-set AT91_RSTC_RSTTYP_WAKEUP [expr (1 << 8)]
-set AT91_RSTC_RSTTYP_WATCHDOG [expr (2 << 8)]
-set AT91_RSTC_RSTTYP_SOFTWARE [expr (3 << 8)]
-set AT91_RSTC_RSTTYP_USER [expr (4 << 8)]
-set AT91_RSTC_NRSTL [expr (1 << 16)] ;# NRST Pin Level
-set AT91_RSTC_SRCMP [expr (1 << 17)] ;# Software Reset Command in Progress
-
-set AT91_RSTC_MR [expr ($AT91_RSTC + 0x08)] ;# Reset Controller Mode Register
-set AT91_RSTC_URSTEN [expr (1 << 0)] ;# User Reset Enable
-set AT91_RSTC_URSTIEN [expr (1 << 4)] ;# User Reset Interrupt Enable
-set AT91_RSTC_ERSTL [expr (0xf << 8)] ;# External Reset Length
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/at91_wdt.cfg b/openocd-0.10.0/scripts/chip/atmel/at91/at91_wdt.cfg
deleted file mode 100644
index a263cc7f6ba15561c84d150fc36ac684ae145704..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/at91_wdt.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-set AT91_WDT_CR [expr ($AT91_WDT + 0x00)] ;# Watchdog Control Register
-set AT91_WDT_WDRSTT [expr (1 << 0)] ;# Restart
-set AT91_WDT_KEY [expr (0xa5 << 24)] ;# KEY Password
-
-set AT91_WDT_MR [expr ($AT91_WDT + 0x04)] ;# Watchdog Mode Register
-set AT91_WDT_WDV [expr (0xfff << 0)] ;# Counter Value
-set AT91_WDT_WDFIEN [expr (1 << 12)] ;# Fault Interrupt Enable
-set AT91_WDT_WDRSTEN [expr (1 << 13)] ;# Reset Processor
-set AT91_WDT_WDRPROC [expr (1 << 14)] ;# Timer Restart
-set AT91_WDT_WDDIS [expr (1 << 15)] ;# Watchdog Disable
-set AT91_WDT_WDD [expr (0xfff << 16)] ;# Delta Value
-set AT91_WDT_WDDBGHLT [expr (1 << 28)] ;# Debug Halt
-set AT91_WDT_WDIDLEHLT [expr (1 << 29)] ;# Idle Halt
-
-set AT91_WDT_SR [expr ($AT91_WDT + 0x08)] ;# Watchdog Status Register
-set AT91_WDT_WDUNF [expr (1 << 0)] ;# Watchdog Underflow
-set AT91_WDT_WDERR [expr (1 << 1)] ;# Watchdog Error
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam7x128.tcl b/openocd-0.10.0/scripts/chip/atmel/at91/at91sam7x128.tcl
deleted file mode 100644
index ce33cf0093733d1d3794f4e8599c1766cad254b2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam7x128.tcl
+++ /dev/null
@@ -1,128 +0,0 @@
-source [find bitsbytes.tcl]
-source [find cpu/arm/arm7tdmi.tcl]
-source [find memory.tcl]
-source [find mmr_helpers.tcl]
-
-set CHIP_MAKER atmel
-set CHIP_FAMILY at91sam7
-set CHIP_NAME at91sam7x128
-# how many flash regions.
-set N_FLASH 1
-set FLASH(0,CHIPSELECT) -1
-set FLASH(0,BASE) 0x00100000
-set FLASH(0,LEN) $__128K
-set FLASH(0,HUMAN) "internal flash"
-set FLASH(0,TYPE) "flash"
-set FLASH(0,RWX) $RWX_R_X
-set FLASH(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
-# how many ram regions.
-set N_RAM 1
-set RAM(0,CHIPSELECT) -1
-set RAM(0,BASE) 0x00200000
-set RAM(0,LEN) $__32K
-set RAM(0,HUMAN) "internal ram"
-set RAM(0,TYPE) "ram"
-set RAM(0,RWX) $RWX_RWX
-set RAM(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
-
-# I AM LAZY... I create 1 region for all MMRs.
-set N_MMREGS 1
-set MMREGS(0,CHIPSELECT) -1
-set MMREGS(0,BASE) 0xfff00000
-set MMREGS(0,LEN) 0x000fffff
-set MMREGS(0,HUMAN) "mm-regs"
-set MMREGS(0,TYPE) "mmr"
-set MMREGS(0,RWX) $RWX_RW
-set MMREGS(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
-
-# no external memory
-set N_XMEM 0
-
-
-
-
-set AT91C_BASE_SYS 0xFFFFF000
-set AT91C_BASE_AIC 0xFFFFF000
-set AT91C_BASE_PDC_DBGU 0xFFFFF300
-set AT91C_BASE_DBGU 0xFFFFF200
-set AT91C_BASE_PIOA 0xFFFFF400
-set AT91C_BASE_PIOB 0xFFFFF600
-set AT91C_BASE_CKGR 0xFFFFFC20
-set AT91C_BASE_PMC 0xFFFFFC00
-set AT91C_BASE_RSTC 0xFFFFFD00
-set AT91C_BASE_RTTC 0xFFFFFD20
-set AT91C_BASE_PITC 0xFFFFFD30
-set AT91C_BASE_WDTC 0xFFFFFD40
-set AT91C_BASE_VREG 0xFFFFFD60
-set AT91C_BASE_MC 0xFFFFFF00
-set AT91C_BASE_PDC_SPI1 0xFFFE4100
-set AT91C_BASE_SPI1 0xFFFE4000
-set AT91C_BASE_PDC_SPI0 0xFFFE0100
-set AT91C_BASE_SPI0 0xFFFE0000
-set AT91C_BASE_PDC_US1 0xFFFC4100
-set AT91C_BASE_US1 0xFFFC4000
-set AT91C_BASE_PDC_US0 0xFFFC0100
-set AT91C_BASE_US0 0xFFFC0000
-set AT91C_BASE_PDC_SSC 0xFFFD4100
-set AT91C_BASE_SSC 0xFFFD4000
-set AT91C_BASE_TWI 0xFFFB8000
-set AT91C_BASE_PWMC_CH3 0xFFFCC260
-set AT91C_BASE_PWMC_CH2 0xFFFCC240
-set AT91C_BASE_PWMC_CH1 0xFFFCC220
-set AT91C_BASE_PWMC_CH0 0xFFFCC200
-set AT91C_BASE_PWMC 0xFFFCC000
-set AT91C_BASE_UDP 0xFFFB0000
-set AT91C_BASE_TC0 0xFFFA0000
-set AT91C_BASE_TC1 0xFFFA0040
-set AT91C_BASE_TC2 0xFFFA0080
-set AT91C_BASE_TCB 0xFFFA0000
-set AT91C_BASE_CAN_MB0 0xFFFD0200
-set AT91C_BASE_CAN_MB1 0xFFFD0220
-set AT91C_BASE_CAN_MB2 0xFFFD0240
-set AT91C_BASE_CAN_MB3 0xFFFD0260
-set AT91C_BASE_CAN_MB4 0xFFFD0280
-set AT91C_BASE_CAN_MB5 0xFFFD02A0
-set AT91C_BASE_CAN_MB6 0xFFFD02C0
-set AT91C_BASE_CAN_MB7 0xFFFD02E0
-set AT91C_BASE_CAN 0xFFFD0000
-set AT91C_BASE_EMAC 0xFFFDC000
-set AT91C_BASE_PDC_ADC 0xFFFD8100
-set AT91C_BASE_ADC 0xFFFD8000
-
-set AT91C_ID(0) FIQ
-set AT91C_ID(1) SYS
-set AT91C_ID(2) PIOA
-set AT91C_ID(3) PIOB
-set AT91C_ID(4) SPI0
-set AT91C_ID(5) SPI1
-set AT91C_ID(6) US0
-set AT91C_ID(7) US1
-set AT91C_ID(8) SSC
-set AT91C_ID(9) TWI
-set AT91C_ID(10) PWMC
-set AT91C_ID(11) UDP
-set AT91C_ID(12) TC0
-set AT91C_ID(13) TC1
-set AT91C_ID(14) TC2
-set AT91C_ID(15) CAN
-set AT91C_ID(16) EMAC
-set AT91C_ID(17) ADC
-set AT91C_ID(18) ""
-set AT91C_ID(19) ""
-set AT91C_ID(20) ""
-set AT91C_ID(21) ""
-set AT91C_ID(22) ""
-set AT91C_ID(23) ""
-set AT91C_ID(24) ""
-set AT91C_ID(25) ""
-set AT91C_ID(26) ""
-set AT91C_ID(27) ""
-set AT91C_ID(28) ""
-set AT91C_ID(29) ""
-set AT91C_ID(30) IRQ0
-set AT91C_ID(31) IRQ1
-
-source [find chip/atmel/at91/aic.tcl]
-source [find chip/atmel/at91/usarts.tcl]
-source [find chip/atmel/at91/pmc.tcl]
-source [find chip/atmel/at91/rtt.tcl]
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam7x256.tcl b/openocd-0.10.0/scripts/chip/atmel/at91/at91sam7x256.tcl
deleted file mode 100644
index dc4918ab177f0fd38cb73d65c42eb4ec8c03dedd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam7x256.tcl
+++ /dev/null
@@ -1,126 +0,0 @@
-source [find bitsbytes.tcl]
-source [find cpu/arm/arm7tdmi.tcl]
-source [find memory.tcl]
-source [find mmr_helpers.tcl]
-
-set CHIP_MAKER atmel
-set CHIP_FAMILY at91sam7
-set CHIP_NAME at91sam7x256
-# how many flash regions.
-set N_FLASH 1
-set FLASH(0,CHIPSELECT) -1
-set FLASH(0,BASE) 0x00100000
-set FLASH(0,LEN) $__256K
-set FLASH(0,HUMAN) "internal flash"
-set FLASH(0,TYPE) "flash"
-set FLASH(0,RWX) $RWX_R_X
-set FLASH(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
-# how many ram regions.
-set N_RAM 1
-set RAM(0,CHIPSELECT) -1
-set RAM(0,BASE) 0x00200000
-set RAM(0,LEN) $__64K
-set RAM(0,HUMAN) "internal ram"
-set RAM(0,TYPE) "ram"
-set RAM(0,RWX) $RWX_RWX
-set RAM(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
-
-# I AM LAZY... I create 1 region for all MMRs.
-set N_MMREGS 1
-set MMREGS(0,CHIPSELECT) -1
-set MMREGS(0,BASE) 0xfff00000
-set MMREGS(0,LEN) 0x000fffff
-set MMREGS(0,HUMAN) "mm-regs"
-set MMREGS(0,TYPE) "mmr"
-set MMREGS(0,RWX) $RWX_RW
-set MMREGS(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
-
-# no external memory
-set N_XMEM 0
-
-set AT91C_BASE_SYS 0xFFFFF000
-set AT91C_BASE_AIC 0xFFFFF000
-set AT91C_BASE_PDC_DBGU 0xFFFFF300
-set AT91C_BASE_DBGU 0xFFFFF200
-set AT91C_BASE_PIOA 0xFFFFF400
-set AT91C_BASE_PIOB 0xFFFFF600
-set AT91C_BASE_CKGR 0xFFFFFC20
-set AT91C_BASE_PMC 0xFFFFFC00
-set AT91C_BASE_RSTC 0xFFFFFD00
-set AT91C_BASE_RTTC 0xFFFFFD20
-set AT91C_BASE_PITC 0xFFFFFD30
-set AT91C_BASE_WDTC 0xFFFFFD40
-set AT91C_BASE_VREG 0xFFFFFD60
-set AT91C_BASE_MC 0xFFFFFF00
-set AT91C_BASE_PDC_SPI1 0xFFFE4100
-set AT91C_BASE_SPI1 0xFFFE4000
-set AT91C_BASE_PDC_SPI0 0xFFFE0100
-set AT91C_BASE_SPI0 0xFFFE0000
-set AT91C_BASE_PDC_US1 0xFFFC4100
-set AT91C_BASE_US1 0xFFFC4000
-set AT91C_BASE_PDC_US0 0xFFFC0100
-set AT91C_BASE_US0 0xFFFC0000
-set AT91C_BASE_PDC_SSC 0xFFFD4100
-set AT91C_BASE_SSC 0xFFFD4000
-set AT91C_BASE_TWI 0xFFFB8000
-set AT91C_BASE_PWMC_CH3 0xFFFCC260
-set AT91C_BASE_PWMC_CH2 0xFFFCC240
-set AT91C_BASE_PWMC_CH1 0xFFFCC220
-set AT91C_BASE_PWMC_CH0 0xFFFCC200
-set AT91C_BASE_PWMC 0xFFFCC000
-set AT91C_BASE_UDP 0xFFFB0000
-set AT91C_BASE_TC0 0xFFFA0000
-set AT91C_BASE_TC1 0xFFFA0040
-set AT91C_BASE_TC2 0xFFFA0080
-set AT91C_BASE_TCB 0xFFFA0000
-set AT91C_BASE_CAN_MB0 0xFFFD0200
-set AT91C_BASE_CAN_MB1 0xFFFD0220
-set AT91C_BASE_CAN_MB2 0xFFFD0240
-set AT91C_BASE_CAN_MB3 0xFFFD0260
-set AT91C_BASE_CAN_MB4 0xFFFD0280
-set AT91C_BASE_CAN_MB5 0xFFFD02A0
-set AT91C_BASE_CAN_MB6 0xFFFD02C0
-set AT91C_BASE_CAN_MB7 0xFFFD02E0
-set AT91C_BASE_CAN 0xFFFD0000
-set AT91C_BASE_EMAC 0xFFFDC000
-set AT91C_BASE_PDC_ADC 0xFFFD8100
-set AT91C_BASE_ADC 0xFFFD8000
-
-set AT91C_ID(0) "FIQ"
-set AT91C_ID(1) "SYS"
-set AT91C_ID(2) "PIOA"
-set AT91C_ID(3) "PIOB"
-set AT91C_ID(4) "SPI0"
-set AT91C_ID(5) "SPI1"
-set AT91C_ID(6) "US0"
-set AT91C_ID(7) "US1"
-set AT91C_ID(8) "SSC"
-set AT91C_ID(9) "TWI"
-set AT91C_ID(10) "PWMC"
-set AT91C_ID(11) "UDP"
-set AT91C_ID(12) "TC0"
-set AT91C_ID(13) "TC1"
-set AT91C_ID(14) "TC2"
-set AT91C_ID(15) "CAN"
-set AT91C_ID(16) "EMAC"
-set AT91C_ID(17) "ADC"
-set AT91C_ID(18) ""
-set AT91C_ID(19) ""
-set AT91C_ID(20) ""
-set AT91C_ID(21) ""
-set AT91C_ID(22) ""
-set AT91C_ID(23) ""
-set AT91C_ID(24) ""
-set AT91C_ID(25) ""
-set AT91C_ID(26) ""
-set AT91C_ID(27) ""
-set AT91C_ID(28) ""
-set AT91C_ID(29) ""
-set AT91C_ID(30) "IRQ0"
-set AT91C_ID(31) "IRQ1"
-
-
-source [find chip/atmel/at91/aic.tcl]
-source [find chip/atmel/at91/usarts.tcl]
-source [find chip/atmel/at91/pmc.tcl]
-source [find chip/atmel/at91/rtt.tcl]
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9261.cfg b/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9261.cfg
deleted file mode 100644
index 61b0c0bf3d5f845bb22efcf618bfcd5a88ed0f6d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9261.cfg
+++ /dev/null
@@ -1,90 +0,0 @@
-#
-# Peripheral identifiers/interrupts.
-#
-set AT91_ID_FIQ 0 ;# Advanced Interrupt Controller (FIQ)
-set AT91_ID_SYS 1 ;# System Peripherals
-set AT91SAM9261_ID_PIOA 2 ;# Parallel IO Controller A
-set AT91SAM9261_ID_PIOB 3 ;# Parallel IO Controller B
-set AT91SAM9261_ID_PIOC 4 ;# Parallel IO Controller C
-set AT91SAM9261_ID_US0 6 ;# USART 0
-set AT91SAM9261_ID_US1 7 ;# USART 1
-set AT91SAM9261_ID_US2 8 ;# USART 2
-set AT91SAM9261_ID_MCI 9 ;# Multimedia Card Interface
-set AT91SAM9261_ID_UDP 10 ;# USB Device Port
-set AT91SAM9261_ID_TWI 11 ;# Two-Wire Interface
-set AT91SAM9261_ID_SPI0 12 ;# Serial Peripheral Interface 0
-set AT91SAM9261_ID_SPI1 13 ;# Serial Peripheral Interface 1
-set AT91SAM9261_ID_SSC0 14 ;# Serial Synchronous Controller 0
-set AT91SAM9261_ID_SSC1 15 ;# Serial Synchronous Controller 1
-set AT91SAM9261_ID_SSC2 16 ;# Serial Synchronous Controller 2
-set AT91SAM9261_ID_TC0 17 ;# Timer Counter 0
-set AT91SAM9261_ID_TC1 18 ;# Timer Counter 1
-set AT91SAM9261_ID_TC2 19 ;# Timer Counter 2
-set AT91SAM9261_ID_UHP 20 ;# USB Host port
-set AT91SAM9261_ID_LCDC 21 ;# LDC Controller
-set AT91SAM9261_ID_IRQ0 29 ;# Advanced Interrupt Controller (IRQ0)
-set AT91SAM9261_ID_IRQ1 30 ;# Advanced Interrupt Controller (IRQ1)
-set AT91SAM9261_ID_IRQ2 31 ;# Advanced Interrupt Controller (IRQ2)
-
-
-#
-# User Peripheral physical base addresses.
-#
-set AT91SAM9261_BASE_TCB0 0xfffa0000
-set AT91SAM9261_BASE_TC0 0xfffa0000
-set AT91SAM9261_BASE_TC1 0xfffa0040
-set AT91SAM9261_BASE_TC2 0xfffa0080
-set AT91SAM9261_BASE_UDP 0xfffa4000
-set AT91SAM9261_BASE_MCI 0xfffa8000
-set AT91SAM9261_BASE_TWI 0xfffac000
-set AT91SAM9261_BASE_US0 0xfffb0000
-set AT91SAM9261_BASE_US1 0xfffb4000
-set AT91SAM9261_BASE_US2 0xfffb8000
-set AT91SAM9261_BASE_SSC0 0xfffbc000
-set AT91SAM9261_BASE_SSC1 0xfffc0000
-set AT91SAM9261_BASE_SSC2 0xfffc4000
-set AT91SAM9261_BASE_SPI0 0xfffc8000
-set AT91SAM9261_BASE_SPI1 0xfffcc000
-set AT91_BASE_SYS 0xffffea00
-
-
-#
-# System Peripherals (offset from AT91_BASE_SYS)
-#
-set AT91_SDRAMC 0xffffea00
-set AT91_SMC 0xffffec00
-set AT91_MATRIX 0xffffee00
-set AT91_AIC 0xfffff000
-set AT91_DBGU 0xfffff200
-set AT91_PIOA 0xfffff400
-set AT91_PIOB 0xfffff600
-set AT91_PIOC 0xfffff800
-set AT91_PMC 0xfffffc00
-set AT91_RSTC 0xfffffd00
-set AT91_SHDWC 0xfffffd10
-set AT91_RTT 0xfffffd20
-set AT91_PIT 0xfffffd30
-set AT91_WDT 0xfffffd40
-set AT91_GPBR 0xfffffd50
-
-set AT91_USART0 $AT91SAM9261_BASE_US0
-set AT91_USART1 $AT91SAM9261_BASE_US1
-set AT91_USART2 $AT91SAM9261_BASE_US2
-
-
-#
-# Internal Memory.
-#
-set AT91SAM9261_SRAM_BASE 0x00300000 ;# Internal SRAM base address
-set AT91SAM9261_SRAM_SIZE 0x00028000 ;# Internal SRAM size (160Kb)
-
-set AT91SAM9261_ROM_BASE 0x00400000 ;# Internal ROM base address
-set AT91SAM9261_ROM_SIZE 0x00008000 ;# Internal ROM size (32Kb)
-
-set AT91SAM9261_UHP_BASE 0x00500000 ;# USB Host controller
-set AT91SAM9261_LCDC_BASE 0x00600000 ;# LDC controller
-
-#
-# Cpu Name
-#
-set AT91_CPU_NAME "AT91SAM9261"
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9261_matrix.cfg b/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9261_matrix.cfg
deleted file mode 100644
index dc8de237625ca44d40b9b88b074016ecfc157eea..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9261_matrix.cfg
+++ /dev/null
@@ -1,46 +0,0 @@
-
-set AT91_MATRIX_MCFG [expr ($AT91_MATRIX + 0x00)] ;# Master Configuration Register #
-set AT91_MATRIX_RCB0 [expr (1 << 0)] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
-set AT91_MATRIX_RCB1 [expr (1 << 1)] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
-
-set AT91_MATRIX_SCFG0 [expr ($AT91_MATRIX + 0x04)] ;# Slave Configuration Register 0
-set AT91_MATRIX_SCFG1 [expr ($AT91_MATRIX + 0x08)] ;# Slave Configuration Register 1
-set AT91_MATRIX_SCFG2 [expr ($AT91_MATRIX + 0x0C)] ;# Slave Configuration Register 2
-set AT91_MATRIX_SCFG3 [expr ($AT91_MATRIX + 0x10)] ;# Slave Configuration Register 3
-set AT91_MATRIX_SCFG4 [expr ($AT91_MATRIX + 0x14)] ;# Slave Configuration Register 4
-set AT91_MATRIX_SLOT_CYCLE [expr (0xff << 0)] ;# Maximum Number of Allowed Cycles for a Burst
-set AT91_MATRIX_DEFMSTR_TYPE [expr (3 << 16)] ;# Default Master Type
-set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr (0 << 16)]
-set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr (1 << 16)]
-set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr (2 << 16)]
-set AT91_MATRIX_FIXED_DEFMSTR [expr (7 << 18)] ;# Fixed Index of Default Master
-
-set AT91_MATRIX_TCR [expr ($AT91_MATRIX + 0x24)] ;# TCM Configuration Register
-set AT91_MATRIX_ITCM_SIZE [expr (0xf << 0)] ;# Size of ITCM enabled memory block
-set AT91_MATRIX_ITCM_0 [expr (0 << 0)]
-set AT91_MATRIX_ITCM_16 [expr (5 << 0)]
-set AT91_MATRIX_ITCM_32 [expr (6 << 0)]
-set AT91_MATRIX_ITCM_64 [expr (7 << 0)]
-set AT91_MATRIX_DTCM_SIZE [expr (0xf << 4)] ;# Size of DTCM enabled memory block
-set AT91_MATRIX_DTCM_0 [expr (0 << 4)]
-set AT91_MATRIX_DTCM_16 [expr (5 << 4)]
-set AT91_MATRIX_DTCM_32 [expr (6 << 4)]
-set AT91_MATRIX_DTCM_64 [expr (7 << 4)]
-
-set AT91_MATRIX_EBICSA [expr ($AT91_MATRIX + 0x30)] ;# EBI Chip Select Assignment Register
-set AT91_MATRIX_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment
-set AT91_MATRIX_CS1A_SMC [expr (0 << 1)]
-set AT91_MATRIX_CS1A_SDRAMC [expr (1 << 1)]
-set AT91_MATRIX_CS3A [expr (1 << 3)] ;# Chip Select 3 Assignment
-set AT91_MATRIX_CS3A_SMC [expr (0 << 3)]
-set AT91_MATRIX_CS3A_SMC_SMARTMEDIA [expr (1 << 3)]
-set AT91_MATRIX_CS4A [expr (1 << 4)] ;# Chip Select 4 Assignment
-set AT91_MATRIX_CS4A_SMC [expr (0 << 4)]
-set AT91_MATRIX_CS4A_SMC_CF1 [expr (1 << 4)]
-set AT91_MATRIX_CS5A [expr (1 << 5)] ;# Chip Select 5 Assignment
-set AT91_MATRIX_CS5A_SMC [expr (0 << 5)]
-set AT91_MATRIX_CS5A_SMC_CF2 [expr (1 << 5)]
-set AT91_MATRIX_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration
-
-set AT91_MATRIX_USBPUCR [expr ($AT91_MATRIX + 0x34)] ;# USB Pad Pull-Up Control Register
-set AT91_MATRIX_USBPUCR_PUON [expr (1 << 30)] ;# USB Device PAD Pull-up Enable
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9263.cfg b/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9263.cfg
deleted file mode 100644
index 8e22eb2db07aa1ea4cd99f44c099532bdcc0fa37..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9263.cfg
+++ /dev/null
@@ -1,113 +0,0 @@
-#
-# Peripheral identifiers/interrupts.
-#
-set AT91_ID_FIQ 0 ;# Advanced Interrupt Controller (FIQ)
-set AT91_ID_SYS 1 ;# System Peripherals
-set AT91SAM9263_ID_PIOA 2 ;# Parallel IO Controller A
-set AT91SAM9263_ID_PIOB 3 ;# Parallel IO Controller B
-set AT91SAM9263_ID_PIOCDE 4 ;# Parallel IO Controller C, D and E
-set AT91SAM9263_ID_US0 7 ;# USART 0
-set AT91SAM9263_ID_US1 8 ;# USART 1
-set AT91SAM9263_ID_US2 9 ;# USART 2
-set AT91SAM9263_ID_MCI0 10 ;# Multimedia Card Interface 0
-set AT91SAM9263_ID_MCI1 11 ;# Multimedia Card Interface 1
-set AT91SAM9263_ID_CAN 12 ;# CAN
-set AT91SAM9263_ID_TWI 13 ;# Two-Wire Interface
-set AT91SAM9263_ID_SPI0 14 ;# Serial Peripheral Interface 0
-set AT91SAM9263_ID_SPI1 15 ;# Serial Peripheral Interface 1
-set AT91SAM9263_ID_SSC0 16 ;# Serial Synchronous Controller 0
-set AT91SAM9263_ID_SSC1 17 ;# Serial Synchronous Controller 1
-set AT91SAM9263_ID_AC97C 18 ;# AC97 Controller
-set AT91SAM9263_ID_TCB 19 ;# Timer Counter 0, 1 and 2
-set AT91SAM9263_ID_PWMC 20 ;# Pulse Width Modulation Controller
-set AT91SAM9263_ID_EMAC 21 ;# Ethernet
-set AT91SAM9263_ID_2DGE 23 ;# 2D Graphic Engine
-set AT91SAM9263_ID_UDP 24 ;# USB Device Port
-set AT91SAM9263_ID_ISI 25 ;# Image Sensor Interface
-set AT91SAM9263_ID_LCDC 26 ;# LCD Controller
-set AT91SAM9263_ID_DMA 27 ;# DMA Controller
-set AT91SAM9263_ID_UHP 29 ;# USB Host port
-set AT91SAM9263_ID_IRQ0 30 ;# Advanced Interrupt Controller (IRQ0)
-set AT91SAM9263_ID_IRQ1 31 ;# Advanced Interrupt Controller (IRQ1)
-
-
-#
-# User Peripheral physical base addresses.
-#
-set AT91SAM9263_BASE_UDP 0xfff78000
-set AT91SAM9263_BASE_TCB0 0xfff7c000
-set AT91SAM9263_BASE_TC0 0xfff7c000
-set AT91SAM9263_BASE_TC1 0xfff7c040
-set AT91SAM9263_BASE_TC2 0xfff7c080
-set AT91SAM9263_BASE_MCI0 0xfff80000
-set AT91SAM9263_BASE_MCI1 0xfff84000
-set AT91SAM9263_BASE_TWI 0xfff88000
-set AT91SAM9263_BASE_US0 0xfff8c000
-set AT91SAM9263_BASE_US1 0xfff90000
-set AT91SAM9263_BASE_US2 0xfff94000
-set AT91SAM9263_BASE_SSC0 0xfff98000
-set AT91SAM9263_BASE_SSC1 0xfff9c000
-set AT91SAM9263_BASE_AC97C 0xfffa0000
-set AT91SAM9263_BASE_SPI0 0xfffa4000
-set AT91SAM9263_BASE_SPI1 0xfffa8000
-set AT91SAM9263_BASE_CAN 0xfffac000
-set AT91SAM9263_BASE_PWMC 0xfffb8000
-set AT91SAM9263_BASE_EMAC 0xfffbc000
-set AT91SAM9263_BASE_ISI 0xfffc4000
-set AT91SAM9263_BASE_2DGE 0xfffc8000
-set AT91_BASE_SYS 0xffffe000
-
-#
-# System Peripherals (offset from AT91_BASE_SYS)
-#
-set AT91_ECC0 0xffffe000
-set AT91_SDRAMC0 0xffffe200
-set AT91_SMC0 0xffffe400
-set AT91_ECC1 0xffffe600
-set AT91_SDRAMC1 0xffffe800
-set AT91_SMC1 0xffffea00
-set AT91_MATRIX 0xffffec00
-set AT91_CCFG 0xffffed10
-set AT91_DBGU 0xffffee00
-set AT91_AIC 0xfffff000
-set AT91_PIOA 0xfffff200
-set AT91_PIOB 0xfffff400
-set AT91_PIOC 0xfffff600
-set AT91_PIOD 0xfffff800
-set AT91_PIOE 0xfffffa00
-set AT91_PMC 0xfffffc00
-set AT91_RSTC 0xfffffd00
-set AT91_SHDWC 0xfffffd10
-set AT91_RTT0 0xfffffd20
-set AT91_PIT 0xfffffd30
-set AT91_WDT 0xfffffd40
-set AT91_RTT1 0xfffffd50
-set AT91_GPBR 0xfffffd60
-
-set AT91_USART0 $AT91SAM9263_BASE_US0
-set AT91_USART1 $AT91SAM9263_BASE_US1
-set AT91_USART2 $AT91SAM9263_BASE_US2
-
-set AT91_SMC $AT91_SMC0
-set AT91_SDRAMC $AT91_SDRAMC0
-
-#
-# Internal Memory.
-#
-set AT91SAM9263_SRAM0_BASE 0x00300000 ;# Internal SRAM 0 base address
-set AT91SAM9263_SRAM0_SIZE 0x00014000 ;# Internal SRAM 0 size (80Kb)
-
-set AT91SAM9263_ROM_BASE 0x00400000 ;# Internal ROM base address
-set AT91SAM9263_ROM_SIZE 0x00020000 ;# Internal ROM size (128Kb)
-
-set AT91SAM9263_SRAM1_BASE 0x00500000 ;# Internal SRAM 1 base address
-set AT91SAM9263_SRAM1_SIZE 0x00004000 ;# Internal SRAM 1 size (16Kb)
-
-set AT91SAM9263_LCDC_BASE 0x00700000 ;# LCD Controller
-set AT91SAM9263_DMAC_BASE 0x00800000 ;# DMA Controller
-set AT91SAM9263_UHP_BASE 0x00a00000 ;# USB Host controller
-
-#
-# Cpu Name
-#
-set AT91_CPU_NAME "AT91SAM9263"
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9263_matrix.cfg b/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9263_matrix.cfg
deleted file mode 100644
index ad3d9a2a31a1394d2ecef89f40d94daded9e2da8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9263_matrix.cfg
+++ /dev/null
@@ -1,112 +0,0 @@
-set AT91_MATRIX_MCFG0 [expr ($AT91_MATRIX + 0x00)] ;# Master Configuration Register 0
-set AT91_MATRIX_MCFG1 [expr ($AT91_MATRIX + 0x04)] ;# Master Configuration Register 1
-set AT91_MATRIX_MCFG2 [expr ($AT91_MATRIX + 0x08)] ;# Master Configuration Register 2
-set AT91_MATRIX_MCFG3 [expr ($AT91_MATRIX + 0x0C)] ;# Master Configuration Register 3
-set AT91_MATRIX_MCFG4 [expr ($AT91_MATRIX + 0x10)] ;# Master Configuration Register 4
-set AT91_MATRIX_MCFG5 [expr ($AT91_MATRIX + 0x14)] ;# Master Configuration Register 5
-set AT91_MATRIX_MCFG6 [expr ($AT91_MATRIX + 0x18)] ;# Master Configuration Register 6
-set AT91_MATRIX_MCFG7 [expr ($AT91_MATRIX + 0x1C)] ;# Master Configuration Register 7
-set AT91_MATRIX_MCFG8 [expr ($AT91_MATRIX + 0x20)] ;# Master Configuration Register 8
-set AT91_MATRIX_ULBT [expr (7 << 0)] ;# Undefined Length Burst Type
-set AT91_MATRIX_ULBT_INFINITE [expr (0 << 0)]
-set AT91_MATRIX_ULBT_SINGLE [expr (1 << 0)]
-set AT91_MATRIX_ULBT_FOUR [expr (2 << 0)]
-set AT91_MATRIX_ULBT_EIGHT [expr (3 << 0)]
-set AT91_MATRIX_ULBT_SIXTEEN [expr (4 << 0)]
-
-set AT91_MATRIX_SCFG0 [expr ($AT91_MATRIX + 0x40)] ;# Slave Configuration Register 0
-set AT91_MATRIX_SCFG1 [expr ($AT91_MATRIX + 0x44)] ;# Slave Configuration Register 1
-set AT91_MATRIX_SCFG2 [expr ($AT91_MATRIX + 0x48)] ;# Slave Configuration Register 2
-set AT91_MATRIX_SCFG3 [expr ($AT91_MATRIX + 0x4C)] ;# Slave Configuration Register 3
-set AT91_MATRIX_SCFG4 [expr ($AT91_MATRIX + 0x50)] ;# Slave Configuration Register 4
-set AT91_MATRIX_SCFG5 [expr ($AT91_MATRIX + 0x54)] ;# Slave Configuration Register 5
-set AT91_MATRIX_SCFG6 [expr ($AT91_MATRIX + 0x58)] ;# Slave Configuration Register 6
-set AT91_MATRIX_SCFG7 [expr ($AT91_MATRIX + 0x5C)] ;# Slave Configuration Register 7
-set AT91_MATRIX_SLOT_CYCLE [expr (0xff << 0)] ;# Maximum Number of Allowed Cycles for a Burst
-set AT91_MATRIX_DEFMSTR_TYPE [expr (3 << 16)] ;# Default Master Type
-set AT91_MATRIX_DEFMSTR_TYPE_NONE [expr (0 << 16)]
-set AT91_MATRIX_DEFMSTR_TYPE_LAST [expr (1 << 16)]
-set AT91_MATRIX_DEFMSTR_TYPE_FIXED [expr (2 << 16)]
-set AT91_MATRIX_FIXED_DEFMSTR [expr (0xf << 18)] ;# Fixed Index of Default Master
-set AT91_MATRIX_ARBT [expr (3 << 24)] ;# Arbitration Type
-set AT91_MATRIX_ARBT_ROUND_ROBIN [expr (0 << 24)]
-set AT91_MATRIX_ARBT_FIXED_PRIORITY [expr (1 << 24)]
-
-set AT91_MATRIX_PRAS0 [expr ($AT91_MATRIX + 0x80)] ;# Priority Register A for Slave 0
-set AT91_MATRIX_PRBS0 [expr ($AT91_MATRIX + 0x84)] ;# Priority Register B for Slave 0
-set AT91_MATRIX_PRAS1 [expr ($AT91_MATRIX + 0x88)] ;# Priority Register A for Slave 1
-set AT91_MATRIX_PRBS1 [expr ($AT91_MATRIX + 0x8C)] ;# Priority Register B for Slave 1
-set AT91_MATRIX_PRAS2 [expr ($AT91_MATRIX + 0x90)] ;# Priority Register A for Slave 2
-set AT91_MATRIX_PRBS2 [expr ($AT91_MATRIX + 0x94)] ;# Priority Register B for Slave 2
-set AT91_MATRIX_PRAS3 [expr ($AT91_MATRIX + 0x98)] ;# Priority Register A for Slave 3
-set AT91_MATRIX_PRBS3 [expr ($AT91_MATRIX + 0x9C)] ;# Priority Register B for Slave 3
-set AT91_MATRIX_PRAS4 [expr ($AT91_MATRIX + 0xA0)] ;# Priority Register A for Slave 4
-set AT91_MATRIX_PRBS4 [expr ($AT91_MATRIX + 0xA4)] ;# Priority Register B for Slave 4
-set AT91_MATRIX_PRAS5 [expr ($AT91_MATRIX + 0xA8)] ;# Priority Register A for Slave 5
-set AT91_MATRIX_PRBS5 [expr ($AT91_MATRIX + 0xAC)] ;# Priority Register B for Slave 5
-set AT91_MATRIX_PRAS6 [expr ($AT91_MATRIX + 0xB0)] ;# Priority Register A for Slave 6
-set AT91_MATRIX_PRBS6 [expr ($AT91_MATRIX + 0xB4)] ;# Priority Register B for Slave 6
-set AT91_MATRIX_PRAS7 [expr ($AT91_MATRIX + 0xB8)] ;# Priority Register A for Slave 7
-set AT91_MATRIX_PRBS7 [expr ($AT91_MATRIX + 0xBC)] ;# Priority Register B for Slave 7
-set AT91_MATRIX_M0PR [expr (3 << 0)] ;# Master 0 Priority
-set AT91_MATRIX_M1PR [expr (3 << 4)] ;# Master 1 Priority
-set AT91_MATRIX_M2PR [expr (3 << 8)] ;# Master 2 Priority
-set AT91_MATRIX_M3PR [expr (3 << 12)] ;# Master 3 Priority
-set AT91_MATRIX_M4PR [expr (3 << 16)] ;# Master 4 Priority
-set AT91_MATRIX_M5PR [expr (3 << 20)] ;# Master 5 Priority
-set AT91_MATRIX_M6PR [expr (3 << 24)] ;# Master 6 Priority
-set AT91_MATRIX_M7PR [expr (3 << 28)] ;# Master 7 Priority
-set AT91_MATRIX_M8PR [expr (3 << 0)] ;# Master 8 Priority (in Register B)
-
-set AT91_MATRIX_MRCR [expr ($AT91_MATRIX + 0x100)] ;# Master Remap Control Register
-set AT91_MATRIX_RCB0 [expr (1 << 0)] ;# Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master)
-set AT91_MATRIX_RCB1 [expr (1 << 1)] ;# Remap Command for AHB Master 1 (ARM926EJ-S Data Master)
-set AT91_MATRIX_RCB2 [expr (1 << 2)]
-set AT91_MATRIX_RCB3 [expr (1 << 3)]
-set AT91_MATRIX_RCB4 [expr (1 << 4)]
-set AT91_MATRIX_RCB5 [expr (1 << 5)]
-set AT91_MATRIX_RCB6 [expr (1 << 6)]
-set AT91_MATRIX_RCB7 [expr (1 << 7)]
-set AT91_MATRIX_RCB8 [expr (1 << 8)]
-
-set AT91_MATRIX_TCMR [expr ($AT91_MATRIX + 0x114)] ;# TCM Configuration Register
-set AT91_MATRIX_ITCM_SIZE [expr (0xf << 0)] ;# Size of ITCM enabled memory block
-set AT91_MATRIX_ITCM_0 [expr (0 << 0)]
-set AT91_MATRIX_ITCM_16 [expr (5 << 0)]
-set AT91_MATRIX_ITCM_32 [expr (6 << 0)]
-set AT91_MATRIX_DTCM_SIZE [expr (0xf << 4)] ;# Size of DTCM enabled memory block
-set AT91_MATRIX_DTCM_0 [expr (0 << 4)]
-set AT91_MATRIX_DTCM_16 [expr (5 << 4)]
-set AT91_MATRIX_DTCM_32 [expr (6 << 4)]
-
-set AT91_MATRIX_EBI0CSA [expr ($AT91_MATRIX + 0x120)] ;# EBI0 Chip Select Assignment Register
-set AT91_MATRIX_EBI0_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment
-set AT91_MATRIX_EBI0_CS1A_SMC [expr (0 << 1)]
-set AT91_MATRIX_EBI0_CS1A_SDRAMC [expr (1 << 1)]
-set AT91_MATRIX_EBI0_CS3A [expr (1 << 3)] ;# Chip Select 3 Assignmen
-set AT91_MATRIX_EBI0_CS3A_SMC [expr (0 << 3)]
-set AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA [expr (1 << 3)]
-set AT91_MATRIX_EBI0_CS4A [expr (1 << 4)] ;# Chip Select 4 Assignment
-set AT91_MATRIX_EBI0_CS4A_SMC [expr (0 << 4)]
-set AT91_MATRIX_EBI0_CS4A_SMC_CF1 [expr (1 << 4)]
-set AT91_MATRIX_EBI0_CS5A [expr (1 << 5)] ;# Chip Select 5 Assignment
-set AT91_MATRIX_EBI0_CS5A_SMC [expr (0 << 5)]
-set AT91_MATRIX_EBI0_CS5A_SMC_CF2 [expr (1 << 5)]
-set AT91_MATRIX_EBI0_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration
-set AT91_MATRIX_EBI0_VDDIOMSEL [expr (1 << 16)] ;# Memory voltage selection
-set AT91_MATRIX_EBI0_VDDIOMSEL_1_8V [expr (0 << 16)]
-set AT91_MATRIX_EBI0_VDDIOMSEL_3_3V [expr (1 << 16)]
-
-set AT91_MATRIX_EBI1CSA [expr ($AT91_MATRIX + 0x124)] ;# EBI1 Chip Select Assignment Register
-set AT91_MATRIX_EBI1_CS1A [expr (1 << 1)] ;# Chip Select 1 Assignment
-set AT91_MATRIX_EBI1_CS1A_SMC [expr (0 << 1)]
-set AT91_MATRIX_EBI1_CS1A_SDRAMC [expr (1 << 1)]
-set AT91_MATRIX_EBI1_CS2A [expr (1 << 3)] ;# Chip Select 3 Assignment
-set AT91_MATRIX_EBI1_CS2A_SMC [expr (0 << 3)]
-set AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA [expr (1 << 3)]
-set AT91_MATRIX_EBI1_DBPUC [expr (1 << 8)] ;# Data Bus Pull-up Configuration
-set AT91_MATRIX_EBI1_VDDIOMSEL [expr (1 << 16)] ;# Memory voltage selection
-set AT91_MATRIX_EBI1_VDDIOMSEL_1_8V [expr (0 << 16)]
-set AT91_MATRIX_EBI1_VDDIOMSEL_3_3V [expr (1 << 16)]
-
-
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9_init.cfg b/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9_init.cfg
deleted file mode 100644
index 2d78d241db42a4805060c36848d61b42ec6ede1c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9_init.cfg
+++ /dev/null
@@ -1,95 +0,0 @@
-uplevel #0 [list source [find chip/atmel/at91/at91sam9_sdramc.cfg]]
-uplevel #0 [list source [find chip/atmel/at91/at91_pmc.cfg]]
-uplevel #0 [list source [find chip/atmel/at91/at91_pio.cfg]]
-uplevel #0 [list source [find chip/atmel/at91/at91_rstc.cfg]]
-uplevel #0 [list source [find chip/atmel/at91/at91_wdt.cfg]]
-
-proc at91sam9_reset_start { } {
-
- arm7_9 fast_memory_access disable
-
- jtag_rclk 8
- halt
- wait_halt 10000
- set rstc_mr_val [expr $::AT91_RSTC_KEY]
- set rstc_mr_val [expr ($rstc_mr_val | (5 << 8))]
- set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
- mww $::AT91_RSTC_MR $rstc_mr_val ;# RSTC_MR : enable user reset.
-}
-
-proc at91sam9_reset_init { config } {
-
- mww $::AT91_WDT_MR $config(wdt_mr_val) ;# disable watchdog
-
- set ckgr_mor [expr ($::AT91_PMC_MOSCEN | (255 << 8))]
-
- mww $::AT91_CKGR_MOR $ckgr_mor ;# CKGR_MOR - enable main osc.
- while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 }
-
- set pllar_val [expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog
- set pllar_val [expr ($pllar_val | $::AT91_PMC_OUT)]
- set pllar_val [expr ($pllar_val | $::AT91_PMC_PLLCOUNT)]
- set pllar_val [expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)]
- set pllar_val [expr ($pllar_val | $config(master_pll_div))]
-
- mww $::AT91_CKGR_PLLAR $pllar_val ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz
- while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA] != $::AT91_PMC_LOCKA } { sleep 1 }
-
- ;# PCK/2 = MCK Master Clock from PLLA
- set mckr_val [expr $::AT91_PMC_CSS_PLLA]
- set mckr_val [expr ($mckr_val | $::AT91_PMC_PRES_1)]
- set mckr_val [expr ($mckr_val | $::AT91SAM9_PMC_MDIV_2)]
- set mckr_val [expr ($mckr_val | $::AT91_PMC_PDIV_1)]
-
- mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
- while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 }
-
- ## switch JTAG clock to highspeed clock
- jtag_rclk 0
-
- arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
- arm7_9 fast_memory_access enable
-
- set rstc_mr_val [expr ($::AT91_RSTC_KEY)]
- set rstc_mr_val [expr ($rstc_mr_val | $::AT91_RSTC_URSTEN)]
- mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable
-
- if { [info exists config(sdram_piod)] } {
- set pdr_addr [expr ($::AT91_PIOD + $::PIO_PDR)]
- set pudr_addr [expr ($::AT91_PIOD + $::PIO_PUDR)]
- set asr_addr [expr ($::AT91_PIOD + $::PIO_ASR)]
- mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
- mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
- mww $asr_addr 0xffff0000
- } else {
- set pdr_addr [expr ($::AT91_PIOC + $::PIO_PDR)]
- set pudr_addr [expr ($::AT91_PIOC + $::PIO_PUDR)]
- mww $pdr_addr 0xffff0000 ;# define PDC[31:16] as DATA[31:16]
- mww $pudr_addr 0xffff0000 ;# no pull-up for D[31:16]
- }
-
- mww $config(matrix_ebicsa_addr) $config(matrix_ebicsa_val)
- mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_NORMAL ;# SDRAMC_MR Mode register
- mww $::AT91_SDRAMC_TR $config(sdram_tr_val) ;# SDRAMC_TR - Refresh Timer register
- mww $::AT91_SDRAMC_CR $config(sdram_cr_val) ;# SDRAMC_CR - Configuration register
- mww $::AT91_SDRAMC_MDR $::AT91_SDRAMC_MD_SDRAM ;# Memory Device Register -> SDRAM
- mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_PRECHARGE ;# SDRAMC_MR
- mww $config(sdram_base) 0 ;# SDRAM_BASE
- mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_REFRESH ;# SDRC_MR
- mww $config(sdram_base) 0 ;# SDRAM_BASE
- mww $config(sdram_base) 0 ;# SDRAM_BASE
- mww $config(sdram_base) 0 ;# SDRAM_BASE
- mww $config(sdram_base) 0 ;# SDRAM_BASE
- mww $config(sdram_base) 0 ;# SDRAM_BASE
- mww $config(sdram_base) 0 ;# SDRAM_BASE
- mww $config(sdram_base) 0 ;# SDRAM_BASE
- mww $config(sdram_base) 0 ;# SDRAM_BASE
- mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_LMR ;# SDRC_MR
- mww $config(sdram_base) 0 ;# SDRAM_BASE
- mww $::AT91_SDRAMC_MR $::AT91_SDRAMC_MODE_NORMAL ;# SDRC_MR
- mww $config(sdram_base) 0 ;# SDRAM_BASE
- mww $::AT91_SDRAMC_TR 1200 ;# SDRAM_TR
- mww $config(sdram_base) 0 ;# SDRAM_BASE
-
- mww $::AT91_MATRIX 0xf ;# MATRIX_MCFG - REMAP all masters
-}
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9_sdramc.cfg b/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9_sdramc.cfg
deleted file mode 100644
index dbca497b283080c19f7a05a7b7fdef6273004be0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9_sdramc.cfg
+++ /dev/null
@@ -1,66 +0,0 @@
-
-# SDRAM Controller (SDRAMC) registers
-set AT91_SDRAMC_MR [expr ($AT91_SDRAMC + 0x00)] ;# SDRAM Controller Mode Register
-set AT91_SDRAMC_MODE [expr (0xf << 0)] ;# Command Mode
-set AT91_SDRAMC_MODE_NORMAL 0
-set AT91_SDRAMC_MODE_NOP 1
-set AT91_SDRAMC_MODE_PRECHARGE 2
-set AT91_SDRAMC_MODE_LMR 3
-set AT91_SDRAMC_MODE_REFRESH 4
-set AT91_SDRAMC_MODE_EXT_LMR 5
-set AT91_SDRAMC_MODE_DEEP 6
-
-set AT91_SDRAMC_TR [expr ($AT91_SDRAMC + 0x04)] ;# SDRAM Controller Refresh Timer Register
-set AT91_SDRAMC_COUNT [expr (0xfff << 0)] ;# Refresh Timer Counter
-
-set AT91_SDRAMC_CR [expr ($AT91_SDRAMC + 0x08)] ;# SDRAM Controller Configuration Register
-set AT91_SDRAMC_NC [expr (3 << 0)] ;# Number of Column Bits
-set AT91_SDRAMC_NC_8 [expr (0 << 0)]
-set AT91_SDRAMC_NC_9 [expr (1 << 0)]
-set AT91_SDRAMC_NC_10 [expr (2 << 0)]
-set AT91_SDRAMC_NC_11 [expr (3 << 0)]
-set AT91_SDRAMC_NR [expr (3 << 2)] ;# Number of Row Bits
-set AT91_SDRAMC_NR_11 [expr (0 << 2)]
-set AT91_SDRAMC_NR_12 [expr (1 << 2)]
-set AT91_SDRAMC_NR_13 [expr (2 << 2)]
-set AT91_SDRAMC_NB [expr (1 << 4)] ;# Number of Banks
-set AT91_SDRAMC_NB_2 [expr (0 << 4)]
-set AT91_SDRAMC_NB_4 [expr (1 << 4)]
-set AT91_SDRAMC_CAS [expr (3 << 5)] ;# CAS Latency
-set AT91_SDRAMC_CAS_1 [expr (1 << 5)]
-set AT91_SDRAMC_CAS_2 [expr (2 << 5)]
-set AT91_SDRAMC_CAS_3 [expr (3 << 5)]
-set AT91_SDRAMC_DBW [expr (1 << 7)] ;# Data Bus Width
-set AT91_SDRAMC_DBW_32 [expr (0 << 7)]
-set AT91_SDRAMC_DBW_16 [expr (1 << 7)]
-set AT91_SDRAMC_TWR [expr (0xf << 8)] ;# Write Recovery Delay
-set AT91_SDRAMC_TRC [expr (0xf << 12)] ;# Row Cycle Delay
-set AT91_SDRAMC_TRP [expr (0xf << 16)] ;# Row Precharge Delay
-set AT91_SDRAMC_TRCD [expr (0xf << 20)] ;# Row to Column Delay
-set AT91_SDRAMC_TRAS [expr (0xf << 24)] ;# Active to Precharge Delay
-set AT91_SDRAMC_TXSR [expr (0xf << 28)] ;# Exit Self Refresh to Active Delay
-
-set AT91_SDRAMC_LPR [expr ($AT91_SDRAMC + 0x10)] ;# SDRAM Controller Low Power Register
-set AT91_SDRAMC_LPCB [expr (3 << 0)] ;# Low-power Configurations
-set AT91_SDRAMC_LPCB_DISABLE 0
-set AT91_SDRAMC_LPCB_SELF_REFRESH 1
-set AT91_SDRAMC_LPCB_POWER_DOWN 2
-set AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
-set AT91_SDRAMC_PASR [expr (7 << 4)] ;# Partial Array Self Refresh
-set AT91_SDRAMC_TCSR [expr (3 << 8)] ;# Temperature Compensated Self Refresh
-set AT91_SDRAMC_DS [expr (3 << 10)] ;# Drive Strength
-set AT91_SDRAMC_TIMEOUT [expr (3 << 12)] ;# Time to define when Low Power Mode is enabled
-set AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES [expr (0 << 12)]
-set AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES [expr (1 << 12)]
-set AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES [expr (2 << 12)]
-
-set AT91_SDRAMC_IER [expr ($AT91_SDRAMC + 0x14)] ;# SDRAM Controller Interrupt Enable Register
-set AT91_SDRAMC_IDR [expr ($AT91_SDRAMC + 0x18)] ;# SDRAM Controller Interrupt Disable Register
-set AT91_SDRAMC_IMR [expr ($AT91_SDRAMC + 0x1C)] ;# SDRAM Controller Interrupt Mask Register
-set AT91_SDRAMC_ISR [expr ($AT91_SDRAMC + 0x20)] ;# SDRAM Controller Interrupt Status Register
-set AT91_SDRAMC_RES [expr (1 << 0)] ;# Refresh Error Status
-
-set AT91_SDRAMC_MDR [expr ($AT91_SDRAMC + 0x24)] ;# SDRAM Memory Device Register
-set AT91_SDRAMC_MD [expr (3 << 0)] ;# Memory Device Type
-set AT91_SDRAMC_MD_SDRAM 0
-set AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9_smc.cfg b/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9_smc.cfg
deleted file mode 100644
index 7dc7638582178f789c6e6d7fba717dc8707890a1..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/at91sam9_smc.cfg
+++ /dev/null
@@ -1,20 +0,0 @@
-set AT91_SMC_READMODE [expr (1 << 0)] ;# Read Mode
-set AT91_SMC_WRITEMODE [expr (1 << 1)] ;# Write Mode
-set AT91_SMC_EXNWMODE [expr (3 << 4)] ;# NWAIT Mode
-set AT91_SMC_EXNWMODE_DISABLE [expr (0 << 4)]
-set AT91_SMC_EXNWMODE_FROZEN [expr (2 << 4)]
-set AT91_SMC_EXNWMODE_READY [expr (3 << 4)]
-set AT91_SMC_BAT [expr (1 << 8)] ;# Byte Access Type
-set AT91_SMC_BAT_SELECT [expr (0 << 8)]
-set AT91_SMC_BAT_WRITE [expr (1 << 8)]
-set AT91_SMC_DBW [expr (3 << 12)] ;# Data Bus Width */
-set AT91_SMC_DBW_8 [expr (0 << 12)]
-set AT91_SMC_DBW_16 [expr (1 << 12)]
-set AT91_SMC_DBW_32 [expr (2 << 12)]
-set AT91_SMC_TDFMODE [expr (1 << 20)] ;# TDF Optimization - Enabled
-set AT91_SMC_PMEN [expr (1 << 24)] ;# Page Mode Enabled
-set AT91_SMC_PS [expr (3 << 28)] ;# Page Size
-set AT91_SMC_PS_4 [expr (0 << 28)]
-set AT91_SMC_PS_8 [expr (1 << 28)]
-set AT91_SMC_PS_16 [expr (2 << 28)]
-set AT91_SMC_PS_32 [expr (3 << 28)]
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/hardware.cfg b/openocd-0.10.0/scripts/chip/atmel/at91/hardware.cfg
deleted file mode 100644
index a25eab975bbc2bc4b965b65d5e5ff45498d8b753..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/hardware.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-# External Memory Map
-set AT91_CHIPSELECT_0 0x10000000
-set AT91_CHIPSELECT_1 0x20000000
-set AT91_CHIPSELECT_2 0x30000000
-set AT91_CHIPSELECT_3 0x40000000
-set AT91_CHIPSELECT_4 0x50000000
-set AT91_CHIPSELECT_5 0x60000000
-set AT91_CHIPSELECT_6 0x70000000
-set AT91_CHIPSELECT_7 0x80000000
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/pmc.tcl b/openocd-0.10.0/scripts/chip/atmel/at91/pmc.tcl
deleted file mode 100644
index 584acb80bdf2e34360301ca4a7ec7d1deca659c7..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/pmc.tcl
+++ /dev/null
@@ -1,17 +0,0 @@
-
-if [info exists AT91C_MAINOSC_FREQ] {
- # user set this... let it be.
-} {
- # 18.432mhz is a common thing...
- set AT91C_MAINOSC_FREQ 18432000
-}
-global AT91C_MAINOSC_FREQ
-
-if [info exists AT91C_SLOWOSC_FREQ] {
- # user set this... let it be.
-} {
- # 32khz is the norm
- set AT91C_SLOWOSC_FREQ 32768
-}
-global AT91C_SLOWOSC_FREQ
-
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/rtt.tcl b/openocd-0.10.0/scripts/chip/atmel/at91/rtt.tcl
deleted file mode 100644
index 8be6a56b02a2ad47f96442091c525d001aee4fe4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/rtt.tcl
+++ /dev/null
@@ -1,56 +0,0 @@
-
-set RTTC_RTMR [expr $AT91C_BASE_RTTC + 0x00]
-set RTTC_RTAR [expr $AT91C_BASE_RTTC + 0x04]
-set RTTC_RTVR [expr $AT91C_BASE_RTTC + 0x08]
-set RTTC_RTSR [expr $AT91C_BASE_RTTC + 0x0c]
-global RTTC_RTMR
-global RTTC_RTAR
-global RTTC_RTVR
-global RTTC_RTSR
-
-proc show_RTTC_RTMR_helper { NAME ADDR VAL } {
- set rtpres [expr $VAL & 0x0ffff]
- global BIT16 BIT17
- if { $rtpres == 0 } {
- set rtpres 65536;
- }
- global AT91C_SLOWOSC_FREQ
- # Nasty hack, make this a float by tacking a .0 on the end
- # otherwise, jim makes the value an integer
- set f [expr $AT91C_SLOWOSC_FREQ.0 / $rtpres.0]
- echo [format "\tPrescale value: 0x%04x (%5d) => %f Hz" $rtpres $rtpres $f]
- if { $VAL & $BIT16 } {
- echo "\tBit16 -> Alarm IRQ Enabled"
- } else {
- echo "\tBit16 -> Alarm IRQ Disabled"
- }
- if { $VAL & $BIT17 } {
- echo "\tBit17 -> RTC Inc IRQ Enabled"
- } else {
- echo "\tBit17 -> RTC Inc IRQ Disabled"
- }
- # Bit 18 is write only.
-}
-
-proc show_RTTC_RTSR_helper { NAME ADDR VAL } {
- global BIT0 BIT1
- if { $VAL & $BIT0 } {
- echo "\tBit0 -> ALARM PENDING"
- } else {
- echo "\tBit0 -> alarm not pending"
- }
- if { $VAL & $BIT1 } {
- echo "\tBit0 -> RTINC PENDING"
- } else {
- echo "\tBit0 -> rtinc not pending"
- }
-}
-
-proc show_RTTC { } {
-
- show_mmr32_reg RTTC_RTMR
- show_mmr32_reg RTTC_RTAR
- show_mmr32_reg RTTC_RTVR
- show_mmr32_reg RTTC_RTSR
-}
-
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/sam9_smc.cfg b/openocd-0.10.0/scripts/chip/atmel/at91/sam9_smc.cfg
deleted file mode 100644
index db943cb24282ddf8ccbd93bda27ee2f3344df765..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/sam9_smc.cfg
+++ /dev/null
@@ -1,55 +0,0 @@
-# Setup register
-#
-# ncs_read_setup
-# nrd_setup
-# ncs_write_setup
-# set nwe_setup
-#
-#
-# Pulse register
-#
-# ncs_read_pulse
-# nrd_pulse
-# ncs_write_pulse
-# nwe_pulse
-#
-#
-# Cycle register
-#
-# read_cycle 0
-# write_cycle 0
-#
-#
-# Mode register
-#
-# mode
-# tdf_cycles
-proc sam9_smc_config { cs smc_config } {
- ;# Setup Register for CS n
- set AT91_SMC_SETUP [expr ($::AT91_SMC + 0x00 + ((cs)*0x10))]
- set val [expr ($smc_config(nwe_setup) << 0)]
- set val [expr ($val | $smc_config(ncs_write_setup) << 8]
- set val [expr ($val | $smc_config(nrd_setup)) << 16]
- set val [expr ($val | $smc_config(ncs_read_setup) << 24]
- mww $AT91_SMC_SETUP $val
-
- ;# Pulse Register for CS n
- set AT91_SMC_PULSE [expr ($::AT91_SMC + 0x04 + ((cs)*0x10))]
- set val [expr ($smc_config(nwe_pulse) << 0)]
- set val [expr ($val | $smc_config(ncs_write_pulse) << 8]
- set val [expr ($val | $smc_config(nrd_pulse) << 16]
- set val [expr ($val | $smc_config(ncs_read_pulse) << 24]
- mww $AT91_SMC_PULSE $val
-
- ;# Cycle Register for CS n
- set AT91_SMC_CYCLE [expr ($::AT91_SMC + 0x08 + ((cs)*0x10))]
- set val [expr ($smc_config(write_cycle) << 0)]
- set val [expr ($val | $smc_config(read_cycle) << 16]
- mww $AT91_SMC_CYCLE $val
-
- ;# Mode Register for CS n
- set AT91_SMC_MODE [expr ($::AT91_SMC + 0x0c + ((cs)*0x10))]
- set val [expr ($smc_config(mode) << 0)]
- set val [expr ($val | $smc_config(tdf_cycles) << 16]
- mww $AT91_SMC_MODE $val
-}
diff --git a/openocd-0.10.0/scripts/chip/atmel/at91/usarts.tcl b/openocd-0.10.0/scripts/chip/atmel/at91/usarts.tcl
deleted file mode 100644
index 68420292e91f2c53ac62bafdf0c6f5acecd978df..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/atmel/at91/usarts.tcl
+++ /dev/null
@@ -1,135 +0,0 @@
-# the DBGU and USARTs are 'almost' indentical'
-set DBGU_CR [expr $AT91C_BASE_DBGU + 0x00000000]
-set DBGU_MR [expr $AT91C_BASE_DBGU + 0x00000004]
-set DBGU_IER [expr $AT91C_BASE_DBGU + 0x00000008]
-set DBGU_IDR [expr $AT91C_BASE_DBGU + 0x0000000C]
-set DBGU_IMR [expr $AT91C_BASE_DBGU + 0x00000010]
-set DBGU_CSR [expr $AT91C_BASE_DBGU + 0x00000014]
-set DBGU_RHR [expr $AT91C_BASE_DBGU + 0x00000018]
-set DBGU_THR [expr $AT91C_BASE_DBGU + 0x0000001C]
-set DBGU_BRGR [expr $AT91C_BASE_DBGU + 0x00000020]
-# no RTOR
-# no TTGR
-# no FIDI
-# no NER
-set DBGU_CIDR [expr $AT91C_BASE_DBGU + 0x00000040]
-set DBGU_EXID [expr $AT91C_BASE_DBGU + 0x00000044]
-set DBGU_FNTR [expr $AT91C_BASE_DBGU + 0x00000048]
-
-
-set USx_CR 0x00000000
-set USx_MR 0x00000004
-set USx_IER 0x00000008
-set USx_IDR 0x0000000C
-set USx_IMR 0x00000010
-set USx_CSR 0x00000014
-set USx_RHR 0x00000018
-set USx_THR 0x0000001C
-set USx_BRGR 0x00000020
-set USx_RTOR 0x00000024
-set USx_TTGR 0x00000028
-set USx_FIDI 0x00000040
-set USx_NER 0x00000044
-set USx_IF 0x0000004C
-
-# Create all the uarts that exist..
-# we blow up if there are >9
-
-
-proc show_mmr_USx_MR_helper { NAME ADDR VAL } {
- # First - just print it
-
- set x [show_normalize_bitfield $VAL 3 0]
- if { $x == 0 } {
- echo "\tNormal operation"
- } else {
- echo [format "\tNon Normal operation mode: 0x%02x" $x]
- }
-
- set x [show_normalize_bitfield $VAL 11 9]
- set s "unknown"
- switch -exact $x {
- 0 { set s "Even" }
- 1 { set s "Odd" }
- 2 { set s "Force=0" }
- 3 { set s "Force=1" }
- * {
- set $x [expr $x & 6]
- switch -exact $x {
- 4 { set s "None" }
- 6 { set s "Multidrop Mode" }
- }
- }
- }
- echo [format "\tParity: %s " $s]
-
- set x [expr 5 + [show_normalize_bitfield $VAL 7 6]]
- echo [format "\tDatabits: %d" $x]
-
- set x [show_normalize_bitfield $VAL 13 12]
- switch -exact $x {
- 0 { echo "\tStop bits: 1" }
- 1 { echo "\tStop bits: 1.5" }
- 2 { echo "\tStop bits: 2" }
- 3 { echo "\tStop bits: Illegal/Reserved" }
- }
-}
-
-# For every possbile usart...
-foreach WHO { US0 US1 US2 US3 US4 US5 US6 US7 US8 US9 } {
- set n AT91C_BASE_[set WHO]
- set str ""
-
- # Only if it exists on the chip
- if [ info exists $n ] {
- # Hence: $n - is like AT91C_BASE_USx
- # For every sub-register
- foreach REG {CR MR IER IDR IMR CSR RHR THR BRGR RTOR TTGR FIDI NER IF} {
- # vn = variable name
- set vn [set WHO]_[set REG]
- # vn = USx_IER
- # vv = variable value
- set vv [expr $$n + [set USx_[set REG]]]
- # And VV is the address in memory of that register
-
-
- # make that VN a GLOBAL so others can find it
- global $vn
- set $vn $vv
-
- # Create a command for this specific register.
- proc show_$vn { } "show_mmr32_reg $vn"
-
- # Add this command to the Device(as a whole) command
- set str "$str\nshow_$vn"
- }
- # Now - create the DEVICE(as a whole) command
- set fn show_$WHO
- proc $fn { } $str
- }
-}
-
-# The Debug Uart is special..
-set str ""
-
-
-# For every sub-register
-foreach REG {DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR
- DBGU_CSR DBGU_RHR DBGU_THR DBGU_BRGR DBGU_CIDR DBGU_EXID DBGU_FNTR} {
-
- # Create a command for this specific register.
- proc show_$REG { } "show_mmr32_reg $REG"
-
- # Add this command to the Device(as a whole) command
- set str "$str\nshow_$REG"
-}
-
-# Now - create the DEVICE(as a whole) command
-proc show_DBGU { } $str
-
-unset str
-
-proc show_DBGU_MR_helper { NAME ADDR VAL } { show_mmr_USx_MR_helper $NAME $ADDR $VAL }
-
-
-
diff --git a/openocd-0.10.0/scripts/chip/st/spear/quirk_no_srst.tcl b/openocd-0.10.0/scripts/chip/st/spear/quirk_no_srst.tcl
deleted file mode 100644
index fd02d07c1d85b0e69e36df1ffa1656b6a164c5d9..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/st/spear/quirk_no_srst.tcl
+++ /dev/null
@@ -1,75 +0,0 @@
-# Quirks to bypass missing SRST on JTAG connector
-# EVALSPEAr310 Rev. 2.0
-# http://www.st.com/spear
-#
-# Date: 2010-08-17
-# Author: Antonio Borneo <borneo.antonio@gmail.com>
-
-# For boards that have JTAG SRST not connected.
-# We use "arm9 vector_catch reset" to catch button reset event.
-
-
-$_TARGETNAME configure -event reset-assert sp_reset_assert
-$_TARGETNAME configure -event reset-deassert-post sp_reset_deassert_post
-
-# keeps the name of the SPEAr target
-global sp_target_name
-set sp_target_name $_TARGETNAME
-
-# Keeps the argument of "reset" command (run, init, halt).
-global sp_reset_mode
-set sp_reset_mode ""
-
-# Helper procedure. Returns 0 is target is halted.
-proc sp_is_halted {} {
- global sp_target_name
-
- return [expr [string compare [$sp_target_name curstate] "halted" ] == 0]
-}
-
-# wait for reset button to be pressed, causing CPU to get halted
-proc sp_reset_deassert_post {} {
- global sp_reset_mode
-
- set bar(0) |
- set bar(1) /
- set bar(2) -
- set bar(3) \\
-
- poll on
- echo "====> Press reset button on the board <===="
- for {set i 0} { [sp_is_halted] == 0 } { set i [expr $i + 1]} {
- echo -n "$bar([expr $i & 3])\r"
- sleep 200
- }
-
- # Remove catch reset event
- arm9 vector_catch none
-
- # CPU is halted, but we typed "reset run" ...
- if { [string compare $sp_reset_mode "run"] == 0 } {
- resume
- }
-}
-
-# Override reset-assert, since no SRST available
-# Catch reset event
-proc sp_reset_assert {} {
- arm9 vector_catch reset
-}
-
-# Override default init_reset{mode} to catch parameter "mode"
-proc init_reset {mode} {
- global sp_reset_mode
-
- set sp_reset_mode $mode
-
- # We need to detect CPU get halted, so exit from halt
- if { [sp_is_halted] } {
- echo "Resuming CPU to detect reset"
- resume
- }
-
- # Execute default init_reset{mode}
- jtag arp_init-reset
-}
diff --git a/openocd-0.10.0/scripts/chip/st/spear/spear3xx.tcl b/openocd-0.10.0/scripts/chip/st/spear/spear3xx.tcl
deleted file mode 100644
index ef38841379501c7bc26188c940cf33875dc01646..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/st/spear/spear3xx.tcl
+++ /dev/null
@@ -1,129 +0,0 @@
-# Generic init scripts for all ST SPEAr3xx family
-# http://www.st.com/spear
-#
-# Date: 2010-09-23
-# Author: Antonio Borneo <borneo.antonio@gmail.com>
-
-
-# Initialize internal clock
-# Default:
-# - Crystal = 24 MHz
-# - PLL1 = 332 MHz
-# - PLL2 = 332 MHz
-# - CPU_CLK = 332 MHz
-# - DDR_CLK = 332 MHz async
-# - HCLK = 166 MHz
-# - PCLK = 83 MHz
-proc sp3xx_clock_default {} {
- mww 0xfca00000 0x00000002 ;# set sysclk slow
- mww 0xfca00014 0x0ffffff8 ;# set pll timeout to minimum (100us ?!?)
-
- # DDRCORE disable to change frequency
- set val [expr ([mrw 0xfca8002c] & ~0x20000000) | 0x40000000]
- mww 0xfca8002c $val
- mww 0xfca8002c $val ;# Yes, write twice!
-
- # programming PLL1
- mww 0xfca8000c 0xa600010c ;# M=166 P=1 N=12
- mww 0xfca80008 0x00001c0a ;# power down
- mww 0xfca80008 0x00001c0e ;# enable
- mww 0xfca80008 0x00001c06 ;# strobe
- mww 0xfca80008 0x00001c0e
- while { [expr [mrw 0xfca80008] & 0x01] == 0x00 } { sleep 1 }
-
- # programming PLL2
- mww 0xfca80018 0xa600010c ;# M=166, P=1, N=12
- mww 0xfca80014 0x00001c0a ;# power down
- mww 0xfca80014 0x00001c0e ;# enable
- mww 0xfca80014 0x00001c06 ;# strobe
- mww 0xfca80014 0x00001c0e
- while { [expr [mrw 0xfca80014] & 0x01] == 0x00 } { sleep 1 }
-
- mww 0xfca80028 0x00000082 ;# enable plltimeen
- mww 0xfca80024 0x00000511 ;# set hclkdiv="/2" & pclkdiv="/2"
-
- mww 0xfca00000 0x00000004 ;# setting SYSCTL to NORMAL mode
- while { [expr [mrw 0xfca00000] & 0x20] != 0x20 } { sleep 1 }
-
- # Select source of DDR clock
- #mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1
- mmw 0xfca80020 0x30000000 0x70000000 ;# PLL2
-
- # DDRCORE enable after change frequency
- mmw 0xfca8002c 0x20000000 0x00000000
-}
-
-proc sp3xx_common_init {} {
- mww 0xfca8002c 0xfffffff8 ;# enable clock of all peripherals
- mww 0xfca80038 0x00000000 ;# remove reset of all peripherals
-
- mww 0xfca80034 0x0000ffff ;# enable all RAS clocks
- mww 0xfca80040 0x00000000 ;# remove all RAS resets
-
- mww 0xfca800e4 0x78000008 ;# COMP1V8_REG
- mww 0xfca800ec 0x78000008 ;# COMP3V3_REG
-
- mww 0xfc000000 0x10000f5f ;# init SMI and set HW mode
- mww 0xfc000000 0x00000f5f
-
- # Initialize Bus Interconnection Matrix
- # All ports Round-Robin and lowest priority
- mww 0xfca8007c 0x80000007
- mww 0xfca80080 0x80000007
- mww 0xfca80084 0x80000007
- mww 0xfca80088 0x80000007
- mww 0xfca8008c 0x80000007
- mww 0xfca80090 0x80000007
- mww 0xfca80094 0x80000007
- mww 0xfca80098 0x80000007
- mww 0xfca8009c 0x80000007
-}
-
-
-# Specific init scripts for ST SPEAr300
-proc sp300_init {} {
- mww 0x99000000 0x00003fff ;# RAS function enable
-}
-
-
-# Specific init scripts for ST SPEAr310
-proc sp310_init {} {
- mww 0xb4000008 0x00002ff4 ;# RAS function enable
-
- mww 0xfca80050 0x00000001 ;# Enable clk mem port 1
-
- mww 0xfca8013c 0x2f7bc210 ;# plgpio_pad_drv
- mww 0xfca80140 0x017bdef6
-}
-
-proc sp310_emi_init {} {
- # set EMI pad strength
- mmw 0xfca80134 0x0e000000 0x00000000
- mmw 0xfca80138 0x0e739ce7 0x00000000
- mmw 0xfca8013c 0x00039ce7 0x00000000
-
- # set safe EMI timing as in BootROM
- #mww 0x4f000000 0x0000000f ;# tAP_0_reg
- #mww 0x4f000004 0x00000000 ;# tSDP_0_reg
- #mww 0x4f000008 0x000000ff ;# tDPw_0_reg
- #mww 0x4f00000c 0x00000111 ;# tDPr_0_reg
- #mww 0x4f000010 0x00000002 ;# tDCS_0_reg
-
- # set fast EMI timing as in Linux
- mww 0x4f000000 0x00000010 ;# tAP_0_reg
- mww 0x4f000004 0x00000005 ;# tSDP_0_reg
- mww 0x4f000008 0x0000000a ;# tDPw_0_reg
- mww 0x4f00000c 0x0000000a ;# tDPr_0_reg
- mww 0x4f000010 0x00000005 ;# tDCS_0_re
-
- # 32bit wide, 8/16/32bit access
- mww 0x4f000014 0x0000000e ;# control_0_reg
- mww 0x4f000094 0x0000003f ;# ack_reg
-}
-
-
-# Specific init scripts for ST SPEAr320
-proc sp320_init {} {
- mww 0xb300000c 0xffffac04 ;# RAS function enable
- mww 0xb3000010 0x00000001 ;# RAS mode select
-}
diff --git a/openocd-0.10.0/scripts/chip/st/spear/spear3xx_ddr.tcl b/openocd-0.10.0/scripts/chip/st/spear/spear3xx_ddr.tcl
deleted file mode 100644
index a9787d11d4c8d206ae3166976be2c495e47ba749..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/st/spear/spear3xx_ddr.tcl
+++ /dev/null
@@ -1,127 +0,0 @@
-# Init scripts to configure DDR controller of SPEAr3xx
-# http://www.st.com/spear
-# Original values taken from XLoader source code
-#
-# Date: 2010-09-23
-# Author: Antonio Borneo <borneo.antonio@gmail.com>
-
-
-proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} {
- if { $ddr_chips != 1 && $ddr_chips != 2 } {
- error "Only 1 or 2 DDR chips permitted. Wrong value "$ddr_chips
- }
-
- if { $ddr_type == "mt47h64m16_3_333_cl5_async" } {
- ddr_spr3xx_mt47h64m16_3_333_cl5_async $ddr_chips
- set ddr_size 0x08000000
- ## add here new DDR chip definition. Prototype:
- #} elseif { $ddr_type == "?????" } {
- # ????? $ddr_chips
- # set ddr_size 0x?????
- } else {
- error "sp3xx_ddr_init: unrecognized DDR type "$ddr_type
- }
-
- # MPMC START
- mww 0xfc60001c 0x01000100
-
- if { $ddr_chips == 2 } {
- echo [format \
- "Double chip DDR memory. Total memory size 0x%08x byte" \
- [expr 2 * $ddr_size]]
- } else {
- echo [format \
- "Single chip DDR memory. Memory size 0x%08x byte" \
- $ddr_size]
- }
-}
-
-
-# from Xloader file ddr/spr300_mt47h64m16_3_333_cl5_async.S
-proc ddr_spr3xx_mt47h64m16_3_333_cl5_async {ddr_chips} {
- # DDR_PAD_REG
- mww 0xfca800f0 0x00003aa5
-
- # Use "1:2 sync" only when DDR clock source is PLL1 and
- # HCLK is half of PLL1
- mww 0xfc600000 0x00000001 ;# MEMCTL_AHB_SET_00 # This is async
- mww 0xfc600004 0x00000000 ;# MEMCTL_AHB_SET_01
-# mww 0xfc600000 0x02020201 ;# MEMCTL_AHB_SET_00 # This is 1:2 sync
-# mww 0xfc600004 0x02020202 ;# MEMCTL_AHB_SET_01
-
- mww 0xfc600008 0x01000000 ;# MEMCTL_RFSH_SET_00
- mww 0xfc60000c 0x00000101 ;# MEMCTL_DLL_SET_00
- mww 0xfc600010 0x00000101 ;# MEMCTL_GP_00
- mww 0xfc600014 0x01000000 ;# MEMCTL_GP_01
- mww 0xfc600018 0x00010001 ;# MEMCTL_GP_02
- mww 0xfc60001c 0x00000100 ;# MEMCTL_GP_03
- mww 0xfc600020 0x00010001 ;# MEMCTL_GP_04
- if { $ddr_chips == 2 } {
- mww 0xfc600024 0x01020203 ;# MEMCTL_GP_05
- mww 0xfc600028 0x01000102 ;# MEMCTL_GP_06
- mww 0xfc60002c 0x02000202 ;# MEMCTL_AHB_SET_02
- } else {
- mww 0xfc600024 0x00000201 ;# MEMCTL_GP_05
- mww 0xfc600028 0x02000001 ;# MEMCTL_GP_06
- mww 0xfc60002c 0x02000201 ;# MEMCTL_AHB_SET_02
- }
- mww 0xfc600030 0x04040105 ;# MEMCTL_AHB_SET_03
- mww 0xfc600034 0x03030302 ;# MEMCTL_AHB_SET_04
- mww 0xfc600038 0x02040101 ;# MEMCTL_AHB_SET_05
- mww 0xfc60003c 0x00000002 ;# MEMCTL_AHB_SET_06
- mww 0xfc600044 0x03000405 ;# MEMCTL_DQS_SET_0
- mww 0xfc600048 0x03040002 ;# MEMCTL_TIME_SET_01
- mww 0xfc60004c 0x04000305 ;# MEMCTL_TIME_SET_02
- mww 0xfc600050 0x0505053f ;# MEMCTL_AHB_RELPR_00
- mww 0xfc600054 0x05050505 ;# MEMCTL_AHB_RELPR_01
- mww 0xfc600058 0x04040405 ;# MEMCTL_AHB_RELPR_02
- mww 0xfc60005c 0x04040404 ;# MEMCTL_AHB_RELPR_03
- mww 0xfc600060 0x03030304 ;# MEMCTL_AHB_RELPR_04
- mww 0xfc600064 0x03030303 ;# MEMCTL_AHB_RELPR_05
- mww 0xfc600068 0x02020203 ;# MEMCTL_AHB_RELPR_06
- mww 0xfc60006c 0x02020202 ;# MEMCTL_AHB_RELPR_07
- mww 0xfc600070 0x01010102 ;# MEMCTL_AHB_RELPR_08
- mww 0xfc600074 0x01010101 ;# MEMCTL_AHB_RELPR_09
- mww 0xfc600078 0x00000001 ;# MEMCTL_AHB_RELPR_10
- mww 0xfc600088 0x0a0c0a00 ;# MEMCTL_DQS_SET_1
- mww 0xfc60008c 0x0000023f ;# MEMCTL_GP_07
- mww 0xfc600090 0x00050a00 ;# MEMCTL_GP_08
- mww 0xfc600094 0x11000000 ;# MEMCTL_GP_09
- mww 0xfc600098 0x00001302 ;# MEMCTL_GP_10
- mww 0xfc60009c 0x00001c1c ;# MEMCTL_DLL_SET_01
- mww 0xfc6000a0 0x7c000000 ;# MEMCTL_DQS_OUT_SHIFT
- mww 0xfc6000a4 0x005c0000 ;# MEMCTL_WR_DQS_SHIFT
- mww 0xfc6000a8 0x2b050e00 ;# MEMCTL_TIME_SET_03
- mww 0xfc6000ac 0x00640064 ;# MEMCTL_AHB_PRRLX_00
- mww 0xfc6000b0 0x00640064 ;# MEMCTL_AHB_PRRLX_01
- mww 0xfc6000b4 0x00000064 ;# MEMCTL_AHB_PRRLX_02
- mww 0xfc6000b8 0x00000000 ;# MEMCTL_OUTRANGE_LGTH
- mww 0xfc6000bc 0x00200020 ;# MEMCTL_AHB_RW_SET_00
- mww 0xfc6000c0 0x00200020 ;# MEMCTL_AHB_RW_SET_01
- mww 0xfc6000c4 0x00200020 ;# MEMCTL_AHB_RW_SET_02
- mww 0xfc6000c8 0x00200020 ;# MEMCTL_AHB_RW_SET_03
- mww 0xfc6000cc 0x00200020 ;# MEMCTL_AHB_RW_SET_04
- mww 0xfc6000d8 0x00000a24 ;# MEMCTL_TREF
- mww 0xfc6000dc 0x00000000 ;# MEMCTL_EMRS3_DATA
- mww 0xfc6000e0 0x5b1c00c8 ;# MEMCTL_TIME_SET_04
- mww 0xfc6000e4 0x00c8002e ;# MEMCTL_TIME_SET_05
- mww 0xfc6000e8 0x00000000 ;# MEMCTL_VERSION
- mww 0xfc6000ec 0x0001046b ;# MEMCTL_TINIT
- mww 0xfc6000f0 0x00000000 ;# MEMCTL_OUTRANGE_ADDR_01
- mww 0xfc6000f4 0x00000000 ;# MEMCTL_OUTRANGE_ADDR_02
- mww 0xfc600104 0x001c0000 ;# MEMCTL_DLL_DQS_DELAY_BYPASS_0
- mww 0xfc600108 0x0019001c ;# MEMCTL_DLL_SET_02
- mww 0xfc60010c 0x00100000 ;# MEMCTL_DLL_SET_03
- mww 0xfc600110 0x001e007a ;# MEMCTL_DQS_SET_2
- mww 0xfc600188 0x00000000 ;# MEMCTL_USER_DEF_REG_0
- mww 0xfc60018c 0x00000000 ;# MEMCTL_USER_DEF_REG_1
- mww 0xfc600190 0x01010001 ;# MEMCTL_GP_11
- mww 0xfc600194 0x01000000 ;# MEMCTL_GP_12
- mww 0xfc600198 0x00000001 ;# MEMCTL_GP_13
- mww 0xfc60019c 0x00400000 ;# MEMCTL_GP_14
- mww 0xfc6001a0 0x00000000 ;# MEMCTL_EMRS2_DATA_X
- mww 0xfc6001a4 0x00000000 ;# MEMCTL_LWPWR_CNT
- mww 0xfc6001a8 0x00000000 ;# MEMCTL_LWPWR_REG
- mww 0xfc6001ac 0x00860000 ;# MEMCTL_GP_15
- mww 0xfc6001b0 0x00000002 ;# MEMCTL_TPDEX
-}
diff --git a/openocd-0.10.0/scripts/chip/st/stm32/stm32.tcl b/openocd-0.10.0/scripts/chip/st/stm32/stm32.tcl
deleted file mode 100644
index 94b1935dde6a520e9a18ff1f65657ecbc1b11835..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/st/stm32/stm32.tcl
+++ /dev/null
@@ -1,7 +0,0 @@
-source [find bitsbytes.tcl]
-source [find cpu/arm/cortex_m3.tcl]
-source [find memory.tcl]
-source [find mmr_helpers.tcl]
-
-source [find chip/st/stm32/stm32_regs.tcl]
-source [find chip/st/stm32/stm32_rcc.tcl]
diff --git a/openocd-0.10.0/scripts/chip/st/stm32/stm32_rcc.tcl b/openocd-0.10.0/scripts/chip/st/stm32/stm32_rcc.tcl
deleted file mode 100644
index 07718b649398394787468efe2d15a5314fbccab0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/st/stm32/stm32_rcc.tcl
+++ /dev/null
@@ -1,290 +0,0 @@
-
-set RCC_CR [expr $RCC_BASE + 0x00]
-set RCC_CFGR [expr $RCC_BASE + 0x04]
-set RCC_CIR [expr $RCC_BASE + 0x08]
-set RCC_APB2RSTR [expr $RCC_BASE + 0x0c]
-set RCC_APB1RSTR [expr $RCC_BASE + 0x10]
-set RCC_AHBENR [expr $RCC_BASE + 0x14]
-set RCC_APB2ENR [expr $RCC_BASE + 0x18]
-set RCC_APB1ENR [expr $RCC_BASE + 0x1c]
-set RCC_BDCR [expr $RCC_BASE + 0x20]
-set RCC_CSR [expr $RCC_BASE + 0x24]
-
-
-proc show_RCC_CR { } {
- if [ catch { set val [show_mmr32_reg RCC_CR] } msg ] {
- error $msg
- }
-
- show_mmr_bitfield 0 0 $val HSI { OFF ON }
- show_mmr_bitfield 1 1 $val HSIRDY { NOTRDY RDY }
- show_mmr_bitfield 7 3 $val HSITRIM { _NUMBER_ }
- show_mmr_bitfield 15 8 $val HSICAL { _NUMBER_ }
- show_mmr_bitfield 16 16 $val HSEON { OFF ON }
- show_mmr_bitfield 17 17 $val HSERDY { NOTRDY RDY }
- show_mmr_bitfield 18 18 $val HSEBYP { NOTBYPASSED BYPASSED }
- show_mmr_bitfield 19 19 $val CSSON { OFF ON }
- show_mmr_bitfield 24 24 $val PLLON { OFF ON }
- show_mmr_bitfield 25 25 $val PLLRDY { NOTRDY RDY }
-}
-
-proc show_RCC_CFGR { } {
- if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] {
- error $msg
- }
-
-
- show_mmr_bitfield 1 0 $val SW { HSI HSE PLL ILLEGAL }
- show_mmr_bitfield 3 2 $val SWS { HSI HSE PLL ILLEGAL }
- show_mmr_bitfield 7 4 $val HPRE { sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_1 sysclk_div_2 sysclk_div_4 sysclk_div_8 sysclk_div_16 sysclk_div_64 sysclk_div_128 sysclk_div_256 sysclk_div_512 }
- show_mmr_bitfield 10 8 $val PPRE1 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }
- show_mmr_bitfield 13 11 $val PPRE2 { hclk_div1 hclk_div1 hclk_div1 hclk_div1 hclk_div2 hclk_div4 hclk_div8 hclk_div16 }
- show_mmr_bitfield 15 14 $val ADCPRE { pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16 }
- show_mmr_bitfield 16 16 $val PLLSRC { HSI_div_2 HSE }
- show_mmr_bitfield 17 17 $val PLLXTPRE { hse_div1 hse_div2 }
- show_mmr_bitfield 21 18 $val PLLMUL { x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 }
- show_mmr_bitfield 22 22 $val USBPRE { div1 div1_5 }
- show_mmr_bitfield 26 24 $val MCO { none none none none SysClk HSI HSE PLL_div2 }
-}
-
-
-proc show_RCC_CIR { } {
- if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] {
- error $msg
- }
-
-}
-
-proc show_RCC_APB2RSTR { } {
- if [ catch { set val [ show_mmr32_reg RCC_APB2RSTR] } msg ] {
- error $msg
- }
- for { set x 0 } { $x < 32 } { incr x } {
- set bits($x) xxx
- }
- set bits(15) adc3
- set bits(14) usart1
- set bits(13) tim8
- set bits(12) spi1
- set bits(11) tim1
- set bits(10) adc2
- set bits(9) adc1
- set bits(8) iopg
- set bits(7) iopf
- set bits(6) iope
- set bits(5) iopd
- set bits(4) iopc
- set bits(3) iopb
- set bits(2) iopa
- set bits(1) xxx
- set bits(0) afio
- show_mmr32_bits bits $val
-}
-
-proc show_RCC_APB1RSTR { } {
- if [ catch { set val [ show_mmr32_reg RCC_APB1RSTR] } msg ] {
- error $msg
- }
- set bits(31) xxx
- set bits(30) xxx
- set bits(29) dac
- set bits(28) pwr
- set bits(27) bkp
- set bits(26) xxx
- set bits(25) can
- set bits(24) xxx
- set bits(23) usb
- set bits(22) i2c2
- set bits(21) i2c1
- set bits(20) uart5
- set bits(19) uart4
- set bits(18) uart3
- set bits(17) uart2
- set bits(16) xxx
- set bits(15) spi3
- set bits(14) spi2
- set bits(13) xxx
- set bits(12) xxx
- set bits(11) wwdg
- set bits(10) xxx
- set bits(9) xxx
- set bits(8) xxx
- set bits(7) xxx
- set bits(6) xxx
- set bits(5) tim7
- set bits(4) tim6
- set bits(3) tim5
- set bits(2) tim4
- set bits(1) tim3
- set bits(0) tim2
- show_mmr32_bits bits $val
-
-}
-
-proc show_RCC_AHBENR { } {
- if [ catch { set val [ show_mmr32_reg RCC_AHBENR ] } msg ] {
- error $msg
- }
- set bits(31) xxx
- set bits(30) xxx
- set bits(29) xxx
- set bits(28) xxx
- set bits(27) xxx
- set bits(26) xxx
- set bits(25) xxx
- set bits(24) xxx
- set bits(23) xxx
- set bits(22) xxx
- set bits(21) xxx
- set bits(20) xxx
- set bits(19) xxx
- set bits(18) xxx
- set bits(17) xxx
- set bits(16) xxx
- set bits(15) xxx
- set bits(14) xxx
- set bits(13) xxx
- set bits(12) xxx
- set bits(11) xxx
- set bits(10) sdio
- set bits(9) xxx
- set bits(8) fsmc
- set bits(7) xxx
- set bits(6) crce
- set bits(5) xxx
- set bits(4) flitf
- set bits(3) xxx
- set bits(2) sram
- set bits(1) dma2
- set bits(0) dma1
- show_mmr32_bits bits $val
-}
-
-proc show_RCC_APB2ENR { } {
- if [ catch { set val [ show_mmr32_reg RCC_APB2ENR ] } msg ] {
- error $msg
- }
- set bits(31) xxx
- set bits(30) xxx
- set bits(29) xxx
- set bits(28) xxx
- set bits(27) xxx
- set bits(26) xxx
- set bits(25) xxx
- set bits(24) xxx
- set bits(23) xxx
- set bits(22) xxx
- set bits(21) xxx
- set bits(20) xxx
- set bits(19) xxx
- set bits(18) xxx
- set bits(17) xxx
- set bits(16) xxx
- set bits(15) adc3
- set bits(14) usart1
- set bits(13) tim8
- set bits(12) spi1
- set bits(11) tim1
- set bits(10) adc2
- set bits(9) adc1
- set bits(8) iopg
- set bits(7) iopf
- set bits(6) iope
- set bits(5) iopd
- set bits(4) iopc
- set bits(3) iopb
- set bits(2) iopa
- set bits(1) xxx
- set bits(0) afio
- show_mmr32_bits bits $val
-
-}
-
-proc show_RCC_APB1ENR { } {
- if [ catch { set val [ show_mmr32_reg RCC_APB1ENR ] } msg ] {
- error $msg
- }
- set bits(31) xxx
- set bits(30) xxx
- set bits(29) dac
- set bits(28) pwr
- set bits(27) bkp
- set bits(26) xxx
- set bits(25) can
- set bits(24) xxx
- set bits(23) usb
- set bits(22) i2c2
- set bits(21) i2c1
- set bits(20) usart5
- set bits(19) usart4
- set bits(18) usart3
- set bits(17) usart2
- set bits(16) xxx
- set bits(15) spi3
- set bits(14) spi2
- set bits(13) xxx
- set bits(12) xxx
- set bits(11) wwdg
- set bits(10) xxx
- set bits(9) xxx
- set bits(8) xxx
- set bits(7) xxx
- set bits(6) xxx
- set bits(5) tim7
- set bits(4) tim6
- set bits(3) tim5
- set bits(2) tim4
- set bits(1) tim3
- set bits(0) tim2
- show_mmr32_bits bits $val
-}
-
-proc show_RCC_BDCR { } {
- if [ catch { set val [ show_mmr32_reg RCC_BDCR ] } msg ] {
- error $msg
- }
- for { set x 0 } { $x < 32 } { incr x } {
- set bits($x) xxx
- }
- set bits(0) lseon
- set bits(1) lserdy
- set bits(2) lsebyp
- set bits(8) rtcsel0
- set bits(9) rtcsel1
- set bits(15) rtcen
- set bits(16) bdrst
- show_mmr32_bits bits $val
-}
-
-proc show_RCC_CSR { } {
- if [ catch { set val [ show_mmr32_reg RCC_CSR ] } msg ] {
- error $msg
- }
- for { set x 0 } { $x < 32 } { incr x } {
- set bits($x) xxx
- }
- set bits(0) lsion
- set bits(1) lsirdy
- set bits(24) rmvf
- set bits(26) pin
- set bits(27) por
- set bits(28) sft
- set bits(29) iwdg
- set bits(30) wwdg
- set bits(31) lpwr
- show_mmr32_bits bits $val
-}
-
-proc show_RCC { } {
-
- show_RCC_CR
- show_RCC_CFGR
- show_RCC_CIR
- show_RCC_APB2RSTR
- show_RCC_APB1RSTR
- show_RCC_AHBENR
- show_RCC_APB2ENR
- show_RCC_APB1ENR
- show_RCC_BDCR
- show_RCC_CSR
-}
diff --git a/openocd-0.10.0/scripts/chip/st/stm32/stm32_regs.tcl b/openocd-0.10.0/scripts/chip/st/stm32/stm32_regs.tcl
deleted file mode 100644
index 0c1f6257ce207d1b2452cb165c0fa5768180ab94..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/st/stm32/stm32_regs.tcl
+++ /dev/null
@@ -1,95 +0,0 @@
-# /* Peripheral and SRAM base address in the alias region */
-set PERIPH_BB_BASE 0x42000000
-set SRAM_BB_BASE 0x22000000
-
-# /*Peripheral and SRAM base address in the bit-band region */
-set SRAM_BASE 0x20000000
-set PERIPH_BASE 0x40000000
-
-# /*FSMC registers base address */
-set FSMC_R_BASE 0xA0000000
-
-# /*Peripheral memory map */
-set APB1PERIPH_BASE [set PERIPH_BASE]
-set APB2PERIPH_BASE [expr $PERIPH_BASE + 0x10000]
-set AHBPERIPH_BASE [expr $PERIPH_BASE + 0x20000]
-
-set TIM2_BASE [expr $APB1PERIPH_BASE + 0x0000]
-set TIM3_BASE [expr $APB1PERIPH_BASE + 0x0400]
-set TIM4_BASE [expr $APB1PERIPH_BASE + 0x0800]
-set TIM5_BASE [expr $APB1PERIPH_BASE + 0x0C00]
-set TIM6_BASE [expr $APB1PERIPH_BASE + 0x1000]
-set TIM7_BASE [expr $APB1PERIPH_BASE + 0x1400]
-set RTC_BASE [expr $APB1PERIPH_BASE + 0x2800]
-set WWDG_BASE [expr $APB1PERIPH_BASE + 0x2C00]
-set IWDG_BASE [expr $APB1PERIPH_BASE + 0x3000]
-set SPI2_BASE [expr $APB1PERIPH_BASE + 0x3800]
-set SPI3_BASE [expr $APB1PERIPH_BASE + 0x3C00]
-set USART2_BASE [expr $APB1PERIPH_BASE + 0x4400]
-set USART3_BASE [expr $APB1PERIPH_BASE + 0x4800]
-set UART4_BASE [expr $APB1PERIPH_BASE + 0x4C00]
-set UART5_BASE [expr $APB1PERIPH_BASE + 0x5000]
-set I2C1_BASE [expr $APB1PERIPH_BASE + 0x5400]
-set I2C2_BASE [expr $APB1PERIPH_BASE + 0x5800]
-set CAN_BASE [expr $APB1PERIPH_BASE + 0x6400]
-set BKP_BASE [expr $APB1PERIPH_BASE + 0x6C00]
-set PWR_BASE [expr $APB1PERIPH_BASE + 0x7000]
-set DAC_BASE [expr $APB1PERIPH_BASE + 0x7400]
-
-set AFIO_BASE [expr $APB2PERIPH_BASE + 0x0000]
-set EXTI_BASE [expr $APB2PERIPH_BASE + 0x0400]
-set GPIOA_BASE [expr $APB2PERIPH_BASE + 0x0800]
-set GPIOB_BASE [expr $APB2PERIPH_BASE + 0x0C00]
-set GPIOC_BASE [expr $APB2PERIPH_BASE + 0x1000]
-set GPIOD_BASE [expr $APB2PERIPH_BASE + 0x1400]
-set GPIOE_BASE [expr $APB2PERIPH_BASE + 0x1800]
-set GPIOF_BASE [expr $APB2PERIPH_BASE + 0x1C00]
-set GPIOG_BASE [expr $APB2PERIPH_BASE + 0x2000]
-set ADC1_BASE [expr $APB2PERIPH_BASE + 0x2400]
-set ADC2_BASE [expr $APB2PERIPH_BASE + 0x2800]
-set TIM1_BASE [expr $APB2PERIPH_BASE + 0x2C00]
-set SPI1_BASE [expr $APB2PERIPH_BASE + 0x3000]
-set TIM8_BASE [expr $APB2PERIPH_BASE + 0x3400]
-set USART1_BASE [expr $APB2PERIPH_BASE + 0x3800]
-set ADC3_BASE [expr $APB2PERIPH_BASE + 0x3C00]
-
-set SDIO_BASE [expr $PERIPH_BASE + 0x18000]
-
-set DMA1_BASE [expr $AHBPERIPH_BASE + 0x0000]
-set DMA1_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0008]
-set DMA1_Channel2_BASE [expr $AHBPERIPH_BASE + 0x001C]
-set DMA1_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0030]
-set DMA1_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0044]
-set DMA1_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0058]
-set DMA1_Channel6_BASE [expr $AHBPERIPH_BASE + 0x006C]
-set DMA1_Channel7_BASE [expr $AHBPERIPH_BASE + 0x0080]
-set DMA2_BASE [expr $AHBPERIPH_BASE + 0x0400]
-set DMA2_Channel1_BASE [expr $AHBPERIPH_BASE + 0x0408]
-set DMA2_Channel2_BASE [expr $AHBPERIPH_BASE + 0x041C]
-set DMA2_Channel3_BASE [expr $AHBPERIPH_BASE + 0x0430]
-set DMA2_Channel4_BASE [expr $AHBPERIPH_BASE + 0x0444]
-set DMA2_Channel5_BASE [expr $AHBPERIPH_BASE + 0x0458]
-set RCC_BASE [expr $AHBPERIPH_BASE + 0x1000]
-set CRC_BASE [expr $AHBPERIPH_BASE + 0x3000]
-
-# /*Flash registers base address */
-set FLASH_R_BASE [expr $AHBPERIPH_BASE + 0x2000]
-# /*Flash Option Bytes base address */
-set OB_BASE 0x1FFFF800
-
-# /*FSMC Bankx registers base address */
-set FSMC_Bank1_R_BASE [expr $FSMC_R_BASE + 0x0000]
-set FSMC_Bank1E_R_BASE [expr $FSMC_R_BASE + 0x0104]
-set FSMC_Bank2_R_BASE [expr $FSMC_R_BASE + 0x0060]
-set FSMC_Bank3_R_BASE [expr $FSMC_R_BASE + 0x0080]
-set FSMC_Bank4_R_BASE [expr $FSMC_R_BASE + 0x00A0]
-
-# /*Debug MCU registers base address */
-set DBGMCU_BASE 0xE0042000
-
-# /*System Control Space memory map */
-set SCS_BASE 0xE000E000
-
-set SysTick_BASE [expr $SCS_BASE + 0x0010]
-set NVIC_BASE [expr $SCS_BASE + 0x0100]
-set SCB_BASE [expr $SCS_BASE + 0x0D00]
diff --git a/openocd-0.10.0/scripts/chip/ti/lm3s/lm3s.tcl b/openocd-0.10.0/scripts/chip/ti/lm3s/lm3s.tcl
deleted file mode 100644
index 42da8c668ae01bd6866f78baca44ac0cda2dbf73..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/ti/lm3s/lm3s.tcl
+++ /dev/null
@@ -1 +0,0 @@
-source [find chip/ti/lm3s/lm3s_regs.tcl]
diff --git a/openocd-0.10.0/scripts/chip/ti/lm3s/lm3s_regs.tcl b/openocd-0.10.0/scripts/chip/ti/lm3s/lm3s_regs.tcl
deleted file mode 100644
index cb20812db8228dc520081be1481b0b9333b915d5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/chip/ti/lm3s/lm3s_regs.tcl
+++ /dev/null
@@ -1,84 +0,0 @@
-#*****************************************************************************
-#
-# The following are defines for the System Control register addresses.
-#
-#*****************************************************************************
-
-set SYSCTL_DID0 0x400FE000 ;# Device Identification 0
-set SYSCTL_DID1 0x400FE004 ;# Device Identification 1
-set SYSCTL_DC0 0x400FE008 ;# Device Capabilities 0
-set SYSCTL_DC1 0x400FE010 ;# Device Capabilities 1
-set SYSCTL_DC2 0x400FE014 ;# Device Capabilities 2
-set SYSCTL_DC3 0x400FE018 ;# Device Capabilities 3
-set SYSCTL_DC4 0x400FE01C ;# Device Capabilities 4
-set SYSCTL_DC5 0x400FE020 ;# Device Capabilities 5
-set SYSCTL_DC6 0x400FE024 ;# Device Capabilities 6
-set SYSCTL_DC7 0x400FE028 ;# Device Capabilities 7
-set SYSCTL_DC8 0x400FE02C ;# Device Capabilities 8 ADC
- ;# Channels
-set SYSCTL_PBORCTL 0x400FE030 ;# Brown-Out Reset Control
-set SYSCTL_LDOPCTL 0x400FE034 ;# LDO Power Control
-set SYSCTL_SRCR0 0x400FE040 ;# Software Reset Control 0
-set SYSCTL_SRCR1 0x400FE044 ;# Software Reset Control 1
-set SYSCTL_SRCR2 0x400FE048 ;# Software Reset Control 2
-set SYSCTL_RIS 0x400FE050 ;# Raw Interrupt Status
-set SYSCTL_IMC 0x400FE054 ;# Interrupt Mask Control
-set SYSCTL_MISC 0x400FE058 ;# Masked Interrupt Status and
- ;# Clear
-set SYSCTL_RESC 0x400FE05C ;# Reset Cause
-set SYSCTL_RCC 0x400FE060 ;# Run-Mode Clock Configuration
-set SYSCTL_PLLCFG 0x400FE064 ;# XTAL to PLL Translation
-set SYSCTL_GPIOHSCTL 0x400FE06C ;# GPIO High-Speed Control
-set SYSCTL_GPIOHBCTL 0x400FE06C ;# GPIO High-Performance Bus
- ;# Control
-set SYSCTL_RCC2 0x400FE070 ;# Run-Mode Clock Configuration 2
-set SYSCTL_MOSCCTL 0x400FE07C ;# Main Oscillator Control
-set SYSCTL_RCGC0 0x400FE100 ;# Run Mode Clock Gating Control
- ;# Register 0
-set SYSCTL_RCGC1 0x400FE104 ;# Run Mode Clock Gating Control
- ;# Register 1
-set SYSCTL_RCGC2 0x400FE108 ;# Run Mode Clock Gating Control
- ;# Register 2
-set SYSCTL_SCGC0 0x400FE110 ;# Sleep Mode Clock Gating Control
- ;# Register 0
-set SYSCTL_SCGC1 0x400FE114 ;# Sleep Mode Clock Gating Control
- ;# Register 1
-set SYSCTL_SCGC2 0x400FE118 ;# Sleep Mode Clock Gating Control
- ;# Register 2
-set SYSCTL_DCGC0 0x400FE120 ;# Deep Sleep Mode Clock Gating
- ;# Control Register 0
-set SYSCTL_DCGC1 0x400FE124 ;# Deep-Sleep Mode Clock Gating
- ;# Control Register 1
-set SYSCTL_DCGC2 0x400FE128 ;# Deep Sleep Mode Clock Gating
- ;# Control Register 2
-set SYSCTL_DSLPCLKCFG 0x400FE144 ;# Deep Sleep Clock Configuration
-set SYSCTL_CLKVCLR 0x400FE150 ;# Clock Verification Clear
-set SYSCTL_PIOSCCAL 0x400FE150 ;# Precision Internal Oscillator
- ;# Calibration
-set SYSCTL_PIOSCSTAT 0x400FE154 ;# Precision Internal Oscillator
- ;# Statistics
-set SYSCTL_LDOARST 0x400FE160 ;# Allow Unregulated LDO to Reset
- ;# the Part
-set SYSCTL_I2SMCLKCFG 0x400FE170 ;# I2S MCLK Configuration
-set SYSCTL_DC9 0x400FE190 ;# Device Capabilities 9 ADC
- ;# Digital Comparators
-set SYSCTL_NVMSTAT 0x400FE1A0 ;# Non-Volatile Memory Information
-
-set SYSCTL_RCC_USESYSDIV 0x00400000 ;# Enable System Clock Divider
-set SYSCTL_RCC2_BYPASS2 0x00000800 ;# PLL Bypass 2
-set SYSCTL_RCC_MOSCDIS 0x00000001 ;# Main Oscillator Disable
-
-set SYSCTL_SRCR0 0x400FE040 ;# Software Reset Control 0
-set SYSCTL_SRCR1 0x400FE044 ;# Software Reset Control 1
-set SYSCTL_SRCR2 0x400FE048 ;# Software Reset Control 2
-
-set SYSCTL_MISC 0x400FE058 ;# Masked Interrupt Status and Clear
-
-set FLASH_FMA 0x400FD000 ;# Flash Memory Address
-set FLASH_FMD 0x400FD004 ;# Flash Memory Data
-set FLASH_FMC 0x400FD008 ;# Flash Memory Control
-set FLASH_FCRIS 0x400FD00C ;# Flash Controller Raw Interrupt Status
-set FLASH_FCIM 0x400FD010 ;# Flash Controller Interrupt Mask
-set FLASH_FCMISC 0x400FD014 ;# Flash Controller Masked Interrupt Status and Clear
-set FLASH_FMC2 0x400FD020 ;# Flash Memory Control 2
-set FLASH_FWBVAL 0x400FD030 ;# Flash Write Buffer Valid
diff --git a/openocd-0.10.0/scripts/cpld/altera-epm240.cfg b/openocd-0.10.0/scripts/cpld/altera-epm240.cfg
deleted file mode 100644
index 62f2b73b7c862244accf2e1a49d0dbed52e336c4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/cpld/altera-epm240.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-# Altera MAXII EPM240T100C CPLD
-# see MAX II Device Handbook
-# Table 3-3: 32-Bit MAX II Device IDCODE
-# Version Part Number Manuf. ID LSB
-# 0000 0010 0000 1010 0001 000 0110 1110 1
-jtag newtap epm240 tap -expected-id 0x020a10dd -irlen 10
diff --git a/openocd-0.10.0/scripts/cpld/jtagspi.cfg b/openocd-0.10.0/scripts/cpld/jtagspi.cfg
deleted file mode 100644
index 60c3cb109469eaf365ec1e56c1a5a99c7bc5730d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/cpld/jtagspi.cfg
+++ /dev/null
@@ -1,43 +0,0 @@
-set _USER1 0x02
-
-if { [info exists JTAGSPI_IR] } {
- set _JTAGSPI_IR $JTAGSPI_IR
-} else {
- set _JTAGSPI_IR $_USER1
-}
-
-if { [info exists DR_LENGTH] } {
- set _DR_LENGTH $DR_LENGTH
-} else {
- set _DR_LENGTH 1
-}
-
-if { [info exists TARGETNAME] } {
- set _TARGETNAME $TARGETNAME
-} else {
- set _TARGETNAME $_CHIPNAME.proxy
-}
-
-if { [info exists FLASHNAME] } {
- set _FLASHNAME $FLASHNAME
-} else {
- set _FLASHNAME $_CHIPNAME.spi
-}
-
-target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
-flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR $_DR_LENGTH
-
-proc jtagspi_init {chain_id proxy_bit} {
- # load proxy bitstream $proxy_bit and probe spi flash
- global _FLASHNAME
- pld load $chain_id $proxy_bit
- reset halt
- flash probe $_FLASHNAME
-}
-
-proc jtagspi_program {bin addr} {
- # write and verify binary file $bin at offset $addr
- global _FLASHNAME
- flash write_image erase $bin $addr
- flash verify_bank $_FLASHNAME $bin $addr
-}
diff --git a/openocd-0.10.0/scripts/cpld/lattice-lc4032ze.cfg b/openocd-0.10.0/scripts/cpld/lattice-lc4032ze.cfg
deleted file mode 100644
index d4a85eb794039faa0958599ceff453c5d07f7651..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/cpld/lattice-lc4032ze.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-# Lattice ispMACH 4000ZE family, device LC4032ZE
-# just configure a tap
-jtag newtap LC4032ZE tap -irlen 8 -expected-id 0x01806043
diff --git a/openocd-0.10.0/scripts/cpld/xilinx-xc6s.cfg b/openocd-0.10.0/scripts/cpld/xilinx-xc6s.cfg
deleted file mode 100644
index 9ce7ad4918d43924bc0aa6316faf8bd53ab221cc..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/cpld/xilinx-xc6s.cfg
+++ /dev/null
@@ -1,90 +0,0 @@
-# xilinx spartan6
-# http://www.xilinx.com/support/documentation/user_guides/ug380.pdf
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME xc6s
-}
-
-# the 4 top bits (28:31) are the die stepping. ignore it.
-jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
- -expected-id 0x04000093 \
- -expected-id 0x04001093 \
- -expected-id 0x04002093 \
- -expected-id 0x04004093 \
- -expected-id 0x04024093 \
- -expected-id 0x04008093 \
- -expected-id 0x04028093 \
- -expected-id 0x0400E093 \
- -expected-id 0x0402E093 \
- -expected-id 0x04011093 \
- -expected-id 0x04031093 \
- -expected-id 0x0401D093 \
- -expected-id 0x0403D093
-
-pld device virtex2 $_CHIPNAME.tap
-
-set XC6S_CFG_IN 0x05
-set XC6S_JSHUTDOWN 0x0d
-set XC6S_JPROGRAM 0x0b
-set XC6S_JSTART 0x0c
-set XC6S_BYPASS 0x3f
-
-proc xc6s_program {tap} {
- global XC6S_JSHUTDOWN XC6S_JPROGRAM XC6S_JSTART XC6S_BYPASS
- irscan $tap $XC6S_JSHUTDOWN
- irscan $tap $XC6S_JPROGRAM
- irscan $tap $XC6S_JSTART
- irscan $tap $XC6S_BYPASS
-}
-
-#xtp038 and xc3sprog approach
-proc xc6s_program_iprog {tap} {
- global XC6S_JSHUTDOWN XC6S_JSTART XC6S_BYPASS XC6S_CFG_IN
- irscan $tap $XC6S_JSHUTDOWN
- runtest 16
- irscan $tap $XC6S_CFG_IN
- # xtp038 IPROG 16bit flipped
- drscan $tap 16 0xffff 16 0x9955 16 0x66aa 16 0x850c 16 0x7000 16 0x0004
- irscan $tap $XC6S_JSTART
- runtest 32
- irscan $tap $XC6S_BYPASS
- runtest 1
-}
-
-set XC6S_ISC_ENABLE 0x10
-set XC6S_ISC_DISABLE 0x16
-set XC6S_ISC_DNA 0x30
-
-# Get the "Device DNA" from the Spartan 6.
-# Most Xilinx FPGA devices contain an embedded, unique device identifier called
-# the "Device DNA". The identifier is nonvolatile, permanently programmed into
-# the FPGA, and is unchangeable providing a great serial / tracking number.
-proc xc6s_get_dna {tap} {
- global XC6S_ISC_ENABLE XC6S_ISC_DISABLE XC6S_ISC_DNA
- irscan $tap $XC6S_ISC_ENABLE
- runtest 64
- irscan $tap $XC6S_ISC_DNA
- # Device DNA is 57 bits long, but we can only read 32bits at a time
- # with OpenOCD.
- set dna [drscan $tap 16 0 16 0 16 0 9 0]
- runtest 64
- irscan $tap $XC6S_ISC_DISABLE
- runtest 64
-
- # Convert the binary data into the order impact uses
- scan $dna "%x %x %x %x" v1 v2 v3 v4
- set bin_dna [string reverse [concat [format "%09b" $v4][format "%016b" $v3][format "%016b" $v2][format "%016b" $v1]]]
-
- # Return a hex version of binary
- scan [format "0b%s" $bin_dna] "%i" hex_dna
- return $hex_dna
-}
-
-# Print out the "Device DNA" in the same format that impact uses.
-proc xc6s_print_dna {tap} {
- set hex_dna [xc6s_get_dna $tap]
-
- puts [format "DNA = %57b (0x%x)\n" $hex_dna $hex_dna]
-}
diff --git a/openocd-0.10.0/scripts/cpld/xilinx-xc7.cfg b/openocd-0.10.0/scripts/cpld/xilinx-xc7.cfg
deleted file mode 100644
index d5824f8a16005065cf574de7603bc786d6f4a10f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/cpld/xilinx-xc7.cfg
+++ /dev/null
@@ -1,57 +0,0 @@
-# xilinx series 7 (artix, kintex, virtex)
-# http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME xc7
-}
-
-# the 4 top bits (28:31) are the die stepping/revisions. ignore it.
-jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
- -expected-id 0x0362E093 \
- -expected-id 0x0362D093 \
- -expected-id 0x0362C093 \
- -expected-id 0x03632093 \
- -expected-id 0x03631093 \
- -expected-id 0x03636093 \
- -expected-id 0x03647093 \
- -expected-id 0x0364C093 \
- -expected-id 0x03651093 \
- -expected-id 0x03747093 \
- -expected-id 0x03656093 \
- -expected-id 0x03752093 \
- -expected-id 0x03751093 \
- -expected-id 0x03671093 \
- -expected-id 0x036B3093 \
- -expected-id 0x036B7093 \
- -expected-id 0x036BB093 \
- -expected-id 0x036BF093 \
- -expected-id 0x03667093 \
- -expected-id 0x03682093 \
- -expected-id 0x03687093 \
- -expected-id 0x03692093 \
- -expected-id 0x03691093 \
- -expected-id 0x03696093 \
- -expected-id 0x036D5093 \
- -expected-id 0x036D9093 \
- -expected-id 0x036DB093
-
-pld device virtex2 $_CHIPNAME.tap 1
-
-set XC7_JSHUTDOWN 0x0d
-set XC7_JPROGRAM 0x0b
-set XC7_JSTART 0x0c
-set XC7_BYPASS 0x3f
-
-proc xc7_program {tap} {
- global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
- irscan $tap $XC7_JSHUTDOWN
- irscan $tap $XC7_JPROGRAM
- runtest 60000
- #JSTART prevents this from working...
- #irscan $tap $XC7_JSTART
- runtest 2000
- irscan $tap $XC7_BYPASS
- runtest 2000
-}
diff --git a/openocd-0.10.0/scripts/cpld/xilinx-xcr3256.cfg b/openocd-0.10.0/scripts/cpld/xilinx-xcr3256.cfg
deleted file mode 100644
index e5611f1ec977ec4f0fc0ed98f855ed63f77128c2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/cpld/xilinx-xcr3256.cfg
+++ /dev/null
@@ -1,3 +0,0 @@
-#xilinx coolrunner xcr3256
-#simple device - just configure a tap
-jtag newtap xcr tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id 0x0494c093
diff --git a/openocd-0.10.0/scripts/cpu/arm/arm7tdmi.tcl b/openocd-0.10.0/scripts/cpu/arm/arm7tdmi.tcl
deleted file mode 100644
index 37db266189d3da380bcc160de7c653a10fc53f09..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/cpu/arm/arm7tdmi.tcl
+++ /dev/null
@@ -1,6 +0,0 @@
-set CPU_TYPE arm
-set CPU_NAME arm7tdmi
-set CPU_ARCH armv4t
-set CPU_MAX_ADDRESS 0xFFFFFFFF
-set CPU_NBITS 32
-
diff --git a/openocd-0.10.0/scripts/cpu/arm/arm920.tcl b/openocd-0.10.0/scripts/cpu/arm/arm920.tcl
deleted file mode 100644
index f19b20b3c4d054b299ab53d65acc6bf115d868a4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/cpu/arm/arm920.tcl
+++ /dev/null
@@ -1,6 +0,0 @@
-set CPU_TYPE arm
-set CPU_NAME arm920
-set CPU_ARCH armv4t
-set CPU_MAX_ADDRESS 0xFFFFFFFF
-set CPU_NBITS 32
-
diff --git a/openocd-0.10.0/scripts/cpu/arm/arm946.tcl b/openocd-0.10.0/scripts/cpu/arm/arm946.tcl
deleted file mode 100644
index 5204101789df7cea46f6ed92008c4bec44cd4777..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/cpu/arm/arm946.tcl
+++ /dev/null
@@ -1,6 +0,0 @@
-set CPU_TYPE arm
-set CPU_NAME arm946
-set CPU_ARCH armv5te
-set CPU_MAX_ADDRESS 0xFFFFFFFF
-set CPU_NBITS 32
-
diff --git a/openocd-0.10.0/scripts/cpu/arm/arm966.tcl b/openocd-0.10.0/scripts/cpu/arm/arm966.tcl
deleted file mode 100644
index 83ce0f67317e8c097826826eb41e131ac67fb350..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/cpu/arm/arm966.tcl
+++ /dev/null
@@ -1,6 +0,0 @@
-set CPU_TYPE arm
-set CPU_NAME arm966
-set CPU_ARCH armv5te
-set CPU_MAX_ADDRESS 0xFFFFFFFF
-set CPU_NBITS 32
-
diff --git a/openocd-0.10.0/scripts/cpu/arm/cortex_m3.tcl b/openocd-0.10.0/scripts/cpu/arm/cortex_m3.tcl
deleted file mode 100644
index 166af847db84122bce55524ee6372d3058cb52b5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/cpu/arm/cortex_m3.tcl
+++ /dev/null
@@ -1,6 +0,0 @@
-set CPU_TYPE arm
-set CPU_NAME cortex_m3
-set CPU_ARCH armv7
-set CPU_MAX_ADDRESS 0xFFFFFFFF
-set CPU_NBITS 32
-
diff --git a/openocd-0.10.0/scripts/fpga/altera-10m50.cfg b/openocd-0.10.0/scripts/fpga/altera-10m50.cfg
deleted file mode 100644
index 9d00daa832bdca57d51d686bc02c57e629556b3a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/fpga/altera-10m50.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-# Altera MAX10 10M50SAE144C8GES FPGA
-# see MAX 10 FPGA Device Architecture
-# Table 3-1: IDCODE Information for MAX 10 Devices
-# Version Part Number Manuf. ID LSB
-# 0000 0011 0001 1000 0101 000 0110 1110 1
-jtag newtap 10m50 tap -expected-id 0x031850dd -irlen 10
diff --git a/openocd-0.10.0/scripts/fpga/altera-ep3c10.cfg b/openocd-0.10.0/scripts/fpga/altera-ep3c10.cfg
deleted file mode 100644
index 6e8962a53ce3b3a099e48f08bceebc37c18eae43..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/fpga/altera-ep3c10.cfg
+++ /dev/null
@@ -1,4 +0,0 @@
-# Altera Cyclone III EP3C10
-# see Cyclone III Device Handbook, Volume 1;
-# Table 14–5. 32-Bit Cyclone III Device IDCODE
-jtag newtap ep3c10 tap -expected-id 0x020f10dd -irlen 10
diff --git a/openocd-0.10.0/scripts/interface/altera-usb-blaster.cfg b/openocd-0.10.0/scripts/interface/altera-usb-blaster.cfg
deleted file mode 100644
index f19abfebe42b7131b29359ee5af69e6e5774a8f1..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/altera-usb-blaster.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Altera USB-Blaster
-#
-# http://www.altera.com/literature/ug/ug_usb_blstr.pdf
-#
-
-interface usb_blaster
-# These are already the defaults.
-# usb_blaster_vid_pid 0x09FB 0x6001
-# usb_blaster_device_desc "USB-Blaster"
diff --git a/openocd-0.10.0/scripts/interface/altera-usb-blaster2.cfg b/openocd-0.10.0/scripts/interface/altera-usb-blaster2.cfg
deleted file mode 100644
index c35be19703859ea919cb4dd944afdafd528fa9bb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/altera-usb-blaster2.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Altera USB-Blaster II
-#
-
-interface usb_blaster
-usb_blaster_vid_pid 0x09fb 0x6010 0x09fb 0x6810
-usb_blaster_lowlevel_driver ublast2
-usb_blaster_firmware /path/to/quartus/blaster_6810.hex
diff --git a/openocd-0.10.0/scripts/interface/arm-jtag-ew.cfg b/openocd-0.10.0/scripts/interface/arm-jtag-ew.cfg
deleted file mode 100644
index 2e8b57e4ca1db3ce198f5c49f0456505e955ae1e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/arm-jtag-ew.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Olimex ARM-JTAG-EW
-#
-# http://www.olimex.com/dev/arm-jtag-ew.html
-#
-
-interface arm-jtag-ew
-
diff --git a/openocd-0.10.0/scripts/interface/at91rm9200.cfg b/openocd-0.10.0/scripts/interface/at91rm9200.cfg
deleted file mode 100644
index 20826478d873adc9b44407dc4ca0014e1af2bc92..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/at91rm9200.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Various Atmel AT91RM9200 boards
-#
-# TODO: URL?
-#
-
-interface at91rm9200
-at91rm9200_device rea_ecr
-
diff --git a/openocd-0.10.0/scripts/interface/buspirate.cfg b/openocd-0.10.0/scripts/interface/buspirate.cfg
deleted file mode 100644
index 2b68538bf622388311510266f7b27f8f8f289c8e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/buspirate.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# Buspirate with OpenOCD support
-#
-# http://dangerousprototypes.com/bus-pirate-manual/
-#
-
-interface buspirate
-
-# you need to specify port on which BP lives
-#buspirate_port /dev/ttyUSB0
-
-# communication speed setting
-buspirate_speed normal ;# or fast
-
-# voltage regulator Enabled = 1 Disabled = 0
-#buspirate_vreg 0
-
-# pin mode normal or open-drain
-#buspirate_mode normal
-
-# pullup state Enabled = 1 Disabled = 0
-#buspirate_pullup 0
-
-# this depends on the cable, you are safe with this option
-reset_config srst_only
-
diff --git a/openocd-0.10.0/scripts/interface/calao-usb-a9260.cfg b/openocd-0.10.0/scripts/interface/calao-usb-a9260.cfg
deleted file mode 100644
index 5fae2f3b38d885b950d22cb29cc180cda131d95c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/calao-usb-a9260.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# CALAO Systems USB-A9260 common -C01 -C02 setup
-#
-# http://www.calao-systems.com/
-#
-# See calao-usb-a9260-c01.cfg and calao-usb-a9260-c02.cfg.
-#
-
-adapter_nsrst_delay 200
-jtag_ntrst_delay 200
-
diff --git a/openocd-0.10.0/scripts/interface/chameleon.cfg b/openocd-0.10.0/scripts/interface/chameleon.cfg
deleted file mode 100644
index 2fb74681cff6e255e27f7abb67335cfcfbcea2c9..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/chameleon.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Amontec Chameleon POD
-#
-# http://www.amontec.com/chameleon.shtml
-#
-
-interface parport
-parport_cable chameleon
-
diff --git a/openocd-0.10.0/scripts/interface/cmsis-dap.cfg b/openocd-0.10.0/scripts/interface/cmsis-dap.cfg
deleted file mode 100644
index ab5c187eb8029be5981418d7557300833896f9c5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/cmsis-dap.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# ARM CMSIS-DAP compliant adapter
-#
-# http://www.keil.com/support/man/docs/dapdebug/
-#
-
-interface cmsis-dap
-
-# Optionally specify the serial number of CMSIS-DAP usb device.
-#cmsis_dap_serial 02200201E6661E601B98E3B9
diff --git a/openocd-0.10.0/scripts/interface/dummy.cfg b/openocd-0.10.0/scripts/interface/dummy.cfg
deleted file mode 100644
index 1c148c0cb9c326cfcd1a18cde4f08826ff9f1ad2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/dummy.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Dummy interface (for testing purposes)
-#
-
-interface dummy
-
diff --git a/openocd-0.10.0/scripts/interface/estick.cfg b/openocd-0.10.0/scripts/interface/estick.cfg
deleted file mode 100644
index adefcb73f4f58b08210aa25678dc65071a86bac6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/estick.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# eStick
-#
-# http://code.google.com/p/estick-jtag/
-#
-
-interface opendous
diff --git a/openocd-0.10.0/scripts/interface/flashlink.cfg b/openocd-0.10.0/scripts/interface/flashlink.cfg
deleted file mode 100644
index 56dc35e2051a7bdca4d5df242a2a45cbf627e0fd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/flashlink.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# ST FlashLINK JTAG parallel cable
-#
-# http://www.st.com/internet/evalboard/product/94023.jsp
-# http://www.st.com/stonline/products/literature/um/7889.pdf
-#
-
-if { [info exists PARPORTADDR] } {
- set _PARPORTADDR $PARPORTADDR
-} else {
- set _PARPORTADDR 0
-}
-
-interface parport
-parport_port $_PARPORTADDR
-parport_cable flashlink
diff --git a/openocd-0.10.0/scripts/interface/ftdi/100ask-openjtag.cfg b/openocd-0.10.0/scripts/interface/ftdi/100ask-openjtag.cfg
deleted file mode 100644
index 01ae2f7ea09d21cfe9e529a7e9f84cb8057b7622..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/100ask-openjtag.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# www.100ask.org OpenJTAG
-#
-# http://www.100ask.net/OpenJTAG.html
-#
-# Schematics are available from
-# https://blog.matthiasbock.net/wp-content/uploads/2015/04/100ask-JTAGv3.pdf
-#
-
-interface ftdi
-ftdi_device_desc "USB<=>JTAG&RS232"
-ftdi_vid_pid 0x1457 0x5118
-
-ftdi_layout_init 0x0f08 0x0f1b
-ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
-ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
diff --git a/openocd-0.10.0/scripts/interface/ftdi/axm0432.cfg b/openocd-0.10.0/scripts/interface/ftdi/axm0432.cfg
deleted file mode 100644
index 0c24a333ea89723a0836938d00ada59453c9eb66..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/axm0432.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Axiom axm0432
-#
-# http://www.axman.com
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "Symphony SoundBite"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0c08 0x0c2b
-ftdi_layout_signal nTRST -data 0x0800
-ftdi_layout_signal nSRST -data 0x0400
diff --git a/openocd-0.10.0/scripts/interface/ftdi/calao-usb-a9260-c01.cfg b/openocd-0.10.0/scripts/interface/ftdi/calao-usb-a9260-c01.cfg
deleted file mode 100644
index d3da6b7ec4fa27145507def698d2b3c8328d10c6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/calao-usb-a9260-c01.cfg
+++ /dev/null
@@ -1,22 +0,0 @@
-#
-# CALAO Systems USB-A9260-C01
-#
-# http://www.calao-systems.com/
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, but is assumed to work as this"
-echo "interface uses the same layout as configs that were verified. Please report your"
-echo "experience with this file to openocd-devel mailing list, so it could be marked"
-echo "as working or fixed."
-
-interface ftdi
-ftdi_device_desc "USB-A9260"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0c08 0x0f1b
-ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
-ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
-
-script interface/calao-usb-a9260.cfg
-script target/at91sam9260minimal.cfg
diff --git a/openocd-0.10.0/scripts/interface/ftdi/calao-usb-a9260-c02.cfg b/openocd-0.10.0/scripts/interface/ftdi/calao-usb-a9260-c02.cfg
deleted file mode 100644
index dc4dca8f74808c1a6b892d006ef8258ef8221f54..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/calao-usb-a9260-c02.cfg
+++ /dev/null
@@ -1,22 +0,0 @@
-#
-# CALAO Systems USB-A9260-C02
-#
-# http://www.calao-systems.com/
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, but is assumed to work as this"
-echo "interface uses the same layout as configs that were verified. Please report your"
-echo "experience with this file to openocd-devel mailing list, so it could be marked"
-echo "as working or fixed."
-
-interface ftdi
-ftdi_device_desc "USB-A9260"
-ftdi_vid_pid 0x0403 0x6001
-
-ftdi_layout_init 0x0c08 0x0f1b
-ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
-ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
-
-script interface/calao-usb-a9260.cfg
-script target/at91sam9260minimal.cfg
diff --git a/openocd-0.10.0/scripts/interface/ftdi/cortino.cfg b/openocd-0.10.0/scripts/interface/ftdi/cortino.cfg
deleted file mode 100644
index 16ede61298cea0114a60b4beb3fea0cd440c9c79..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/cortino.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Hitex Cortino
-#
-# http://www.hitex.com/index.php?id=cortino
-#
-
-interface ftdi
-ftdi_device_desc "Cortino"
-ftdi_vid_pid 0x0640 0x0032
-
-ftdi_layout_init 0x0108 0x010b
-ftdi_layout_signal nTRST -data 0x0100
-ftdi_layout_signal nSRST -data 0x0200 -oe 0x0200
diff --git a/openocd-0.10.0/scripts/interface/ftdi/digilent-hs1.cfg b/openocd-0.10.0/scripts/interface/ftdi/digilent-hs1.cfg
deleted file mode 100644
index e27249b3bbffb023de01b680ecd2170084fb5eee..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/digilent-hs1.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# this supports JTAG-HS1 and JTAG-SMT1
-# (the later being the OEM on-board version)
-
-interface ftdi
-ftdi_device_desc "Digilent Adept USB Device"
-ftdi_vid_pid 0x0403 0x6010
-# channel 1 does not have any functionality
-ftdi_channel 0
-# just TCK TDI TDO TMS, no reset
-ftdi_layout_init 0x0088 0x008b
-reset_config none
diff --git a/openocd-0.10.0/scripts/interface/ftdi/digilent-hs2.cfg b/openocd-0.10.0/scripts/interface/ftdi/digilent-hs2.cfg
deleted file mode 100644
index 2005b66af0a37cae1b538d20de91051e93bd258c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/digilent-hs2.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# this supports JTAG-HS2 (and apparently Nexys4 as well)
-
-interface ftdi
-ftdi_device_desc "Digilent Adept USB Device"
-ftdi_vid_pid 0x0403 0x6014
-
-ftdi_channel 0
-ftdi_layout_init 0x00e8 0x60eb
-
-reset_config none
diff --git a/openocd-0.10.0/scripts/interface/ftdi/digilent_jtag_hs3.cfg b/openocd-0.10.0/scripts/interface/ftdi/digilent_jtag_hs3.cfg
deleted file mode 100644
index f7b8e570cc2ca998aef402ca029aa409a6c74aa6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/digilent_jtag_hs3.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Digilent JTAG-HS3
-#
-
-interface ftdi
-ftdi_vid_pid 0x0403 0x6014
-ftdi_device_desc "Digilent USB Device"
-
-# From Digilent support:
-# The SRST pin is [...] 0x20 and 0x10 is the /OE (active low output enable)
-
-ftdi_layout_init 0x2088 0x308b
-ftdi_layout_signal nSRST -data 0x2000 -noe 0x1000
diff --git a/openocd-0.10.0/scripts/interface/ftdi/digilent_jtag_smt2.cfg b/openocd-0.10.0/scripts/interface/ftdi/digilent_jtag_smt2.cfg
deleted file mode 100644
index 014fe1475c0152fa9a42fb1c06438b022d2ee7da..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/digilent_jtag_smt2.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Digilent JTAG-SMT2
-#
-# http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,395,1053&Prod=JTAG-SMT2
-#
-# Config is based on data from
-# http://electronix.ru/forum/index.php?showtopic=114633&view=findpost&p=1215497 and ZedBoard schematics
-#
-
-interface ftdi
-ftdi_vid_pid 0x0403 0x6014
-
-ftdi_layout_init 0x2088 0x3f8b
-ftdi_layout_signal nSRST -data 0x2000
-ftdi_layout_signal GPIO2 -data 0x2000
-ftdi_layout_signal GPIO1 -data 0x0200
-ftdi_layout_signal GPIO0 -data 0x0100
diff --git a/openocd-0.10.0/scripts/interface/ftdi/dlp-usb1232h.cfg b/openocd-0.10.0/scripts/interface/ftdi/dlp-usb1232h.cfg
deleted file mode 100644
index f447771e378e6893b304b0c11e679ffdeb6c0dc8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/dlp-usb1232h.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# DLP Design DLP-USB1232H USB-to-UART/FIFO interface module
-#
-# http://www.dlpdesign.com/usb/usb1232h.shtml
-#
-# Schematics for OpenOCD usage:
-# http://randomprojects.org/wiki/DLP-USB1232H_and_OpenOCD_based_JTAG_adapter
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on schematics and code"
-echo "in ft2232.c. Please report your experience with this file to openocd-devel"
-echo "mailing list, so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0008 0x000b
-ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
-ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
diff --git a/openocd-0.10.0/scripts/interface/ftdi/dp_busblaster.cfg b/openocd-0.10.0/scripts/interface/ftdi/dp_busblaster.cfg
deleted file mode 100644
index 73827cfb8af7aa4e36500aeccdaf8ffe34f156b8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/dp_busblaster.cfg
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# Dangerous Prototypes - Bus Blaster
-#
-# The Bus Blaster has a configurable buffer between the FTDI FT2232H and the
-# JTAG header which allows it to emulate various debugger types. It comes
-# configured as a JTAGkey device.
-#
-# http://dangerousprototypes.com/docs/Bus_Blaster
-#
-
-echo "Info : If you need SWD support, flash KT-Link buffer from https://github.com/bharrisau/busblaster
-and use dp_busblaster_kt-link.cfg instead"
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0c08 0x0f1b
-ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
-ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/openocd-0.10.0/scripts/interface/ftdi/dp_busblaster_kt-link.cfg b/openocd-0.10.0/scripts/interface/ftdi/dp_busblaster_kt-link.cfg
deleted file mode 100644
index 2d27519d4f8f399aba665841e4ca54fd33715046..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/dp_busblaster_kt-link.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# Dangerous Prototypes - Bus Blaster (with KT-Link buffer)
-#
-# The Bus Blaster has a configurable buffer between the FTDI FT2232H
-# and the JTAG header which allows it to emulate various debugger
-# types. This config works with KT-Link compatible implementation from
-# https://github.com/bharrisau/busblaster and is SWD-enabled.
-#
-# http://dangerousprototypes.com/docs/Bus_Blaster
-#
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x8c28 0xff3b
-ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
-ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
-ftdi_layout_signal LED -ndata 0x8000
-ftdi_layout_signal SWD_EN -ndata 0x0020 -oe 0x2000
-ftdi_layout_signal SWDIO_OE -ndata 0x1000
diff --git a/openocd-0.10.0/scripts/interface/ftdi/flossjtag-noeeprom.cfg b/openocd-0.10.0/scripts/interface/ftdi/flossjtag-noeeprom.cfg
deleted file mode 100644
index 18046e7428a45666ba614aa9117db6a1ecfbea6e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/flossjtag-noeeprom.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# FlossJTAG
-#
-# http://github.com/esden/floss-jtag
-#
-# This is the pre v0.3 Floss-JTAG compatible config file. It can also be used
-# for newer versions of Floss-JTAG with empty or not populated EEPROM. If you
-# have several Floss-JTAG connected you have to use the USB ID to select a
-# specific one.
-#
-# If you have a Floss-JTAG WITH EEPROM that is programmed, use the
-# flossjtag.cfg file.
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0008 0x000b
-ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
-ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
diff --git a/openocd-0.10.0/scripts/interface/ftdi/flossjtag.cfg b/openocd-0.10.0/scripts/interface/ftdi/flossjtag.cfg
deleted file mode 100644
index 13e1f0bb70cd1775f34401a97636b1adb3d4fe4e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/flossjtag.cfg
+++ /dev/null
@@ -1,29 +0,0 @@
-#
-# FlossJTAG
-#
-# http://github.com/esden/floss-jtag
-#
-# This is the v0.3 and v1.0 Floss-JTAG compatible config file. It relies on the
-# existence of an EEPROM on Floss-JTAG containing a name. If you have several
-# Floss-JTAG adapters connected you can use the serial number to select a
-# specific device.
-#
-# If your Floss-JTAG does not have an EEPROM, or the EEPROM is empty, use the
-# flossjtag-noeeprom.cfg file.
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_vid_pid 0x0403 0x6010
-ftdi_device_desc "FLOSS-JTAG"
-#ftdi_serial "FJ000001"
-
-ftdi_layout_init 0x0008 0x180b
-ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
-ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
-ftdi_layout_signal LED -data 0x0800
-ftdi_layout_signal LED2 -data 0x1000
diff --git a/openocd-0.10.0/scripts/interface/ftdi/flyswatter.cfg b/openocd-0.10.0/scripts/interface/ftdi/flyswatter.cfg
deleted file mode 100644
index 56dab1f33e9a7159b2cdda4e6e04bc9fd7a76f19..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/flyswatter.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# TinCanTools Flyswatter
-#
-# http://www.tincantools.com/product.php?productid=16134
-#
-
-interface ftdi
-ftdi_device_desc "Flyswatter"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0818 0x0cfb
-ftdi_layout_signal nTRST -data 0x0010
-ftdi_layout_signal nSRST -oe 0x0020
-ftdi_layout_signal LED -data 0x0c00
diff --git a/openocd-0.10.0/scripts/interface/ftdi/flyswatter2.cfg b/openocd-0.10.0/scripts/interface/ftdi/flyswatter2.cfg
deleted file mode 100644
index 8bd4db4b727b54e0fa582307ca9b368613577159..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/flyswatter2.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# TinCanTools Flyswatter2
-#
-# http://www.tincantools.com/product.php?productid=16153
-#
-
-interface ftdi
-ftdi_device_desc "Flyswatter2"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0538 0x057b
-ftdi_layout_signal LED -ndata 0x0400
-ftdi_layout_signal nTRST -data 0x0010
-ftdi_layout_signal nSRST -data 0x0020 -noe 0x0100
diff --git a/openocd-0.10.0/scripts/interface/ftdi/gw16042.cfg b/openocd-0.10.0/scripts/interface/ftdi/gw16042.cfg
deleted file mode 100644
index 90c6f7c122b57dec60f6c45a3966748d2dccddf8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/gw16042.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# Gateworks GW16042 JTAG Dongle
-#
-# http://www.gateworks.com/
-#
-# Layout: FTDI FT2232H
-# ADBUS0 TCK
-# ADBUS1 TDI
-# ADBUS2 TDO (input)
-# ADBUS3 TMS
-# ADBUS4 nTRST
-# ADBUS5 nSRST
-# ADBUS6 OE (active high) for TRST, TDI, TMS, TCK
-# ADBUS7 NC
-# ACBUS0-7 NC
-# BDBUS0 RXD
-# BDBUS1 TXD (input)
-#
-
-interface ftdi
-ftdi_device_desc "USB-JTAG"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0058 0x007b
-ftdi_layout_signal nTRST -data 0x0010
-ftdi_layout_signal nSRST -oe 0x0020
diff --git a/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx10_etm.cfg b/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx10_etm.cfg
deleted file mode 100644
index b682333ed71a736421694669ad2e2014514da269..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx10_etm.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Hilscher NXHX 10-ETM
-#
-# http://de.hilscher.com/products_details_hardware.html?p_id=P_4ce145a5983e6
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "NXHX 10-ETM"
-ftdi_vid_pid 0x0640 0x0028
-
-ftdi_layout_init 0x0308 0x030b
-ftdi_layout_signal nTRST -data 0x0100
-ftdi_layout_signal nSRST -data 0x0200
diff --git a/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx500_etm.cfg b/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx500_etm.cfg
deleted file mode 100644
index 3483030c6a3e4785c33aa3fb7703185456e9a1e9..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx500_etm.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Hilscher NXHX 500-ETM
-#
-# http://de.hilscher.com/files_design/8/NXHX500-ETM_description_Rev01_EN.pdf
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "NXHX 500-ETM"
-ftdi_vid_pid 0x0640 0x0028
-
-ftdi_layout_init 0x0308 0x030b
-ftdi_layout_signal nTRST -data 0x0100
-ftdi_layout_signal nSRST -data 0x0200
diff --git a/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx500_re.cfg b/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx500_re.cfg
deleted file mode 100644
index b4cada0555e862bd43648cc713a928e543919bf2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx500_re.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Hilscher NXHX 500-RE
-#
-# http://de.hilscher.com/products_details_hardware.html?p_id=P_461ff2053bad1&bs=20
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "NXHX 500-RE"
-ftdi_vid_pid 0x0640 0x0028
-
-ftdi_layout_init 0x0308 0x030b
-ftdi_layout_signal nTRST -data 0x0100
-ftdi_layout_signal nSRST -data 0x0200
diff --git a/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx50_etm.cfg b/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx50_etm.cfg
deleted file mode 100644
index 67074a2639335c046d4e2f8991dc00c2c992a8b3..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx50_etm.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Hilscher NXHX 50-ETM
-#
-# http://de.hilscher.com/files_design/8/NXHX50-ETM_description_Rev01_EN.pdf
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "NXHX 50-ETM"
-ftdi_vid_pid 0x0640 0x0028
-
-ftdi_layout_init 0x0308 0x030b
-ftdi_layout_signal nTRST -data 0x0100
-ftdi_layout_signal nSRST -data 0x0200
diff --git a/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx50_re.cfg b/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx50_re.cfg
deleted file mode 100644
index 966dcd8126ab3b56302985d676d3394c6eabb126..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/hilscher_nxhx50_re.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Hilscher NXHX 50-RE
-#
-# http://de.hilscher.com/products_details_hardware.html?p_id=P_483c0f582ad36&bs=20
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "NXHX50-RE"
-ftdi_vid_pid 0x0640 0x0028
-
-ftdi_layout_init 0x0308 0x030b
-ftdi_layout_signal nTRST -data 0x0100
-ftdi_layout_signal nSRST -data 0x0200
diff --git a/openocd-0.10.0/scripts/interface/ftdi/hitex_lpc1768stick.cfg b/openocd-0.10.0/scripts/interface/ftdi/hitex_lpc1768stick.cfg
deleted file mode 100644
index f22d4f7b2c64d235a4ce7118367beb2ba73d91c6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/hitex_lpc1768stick.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Hitex LPC1768-Stick
-#
-# http://www.hitex.com/?id=1602
-#
-
-
-interface ftdi
-ftdi_device_desc "LPC1768-Stick"
-ftdi_vid_pid 0x0640 0x0026
-
-ftdi_layout_init 0x0388 0x038b
-ftdi_layout_signal nTRST -data 0x0100
-ftdi_layout_signal nSRST -data 0x0080 -noe 0x200
-
diff --git a/openocd-0.10.0/scripts/interface/ftdi/hitex_str9-comstick.cfg b/openocd-0.10.0/scripts/interface/ftdi/hitex_str9-comstick.cfg
deleted file mode 100644
index c46f0322cafd31b1bb7de6dfce62e00d771831d2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/hitex_str9-comstick.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Hitex STR9-comStick
-#
-# http://www.hitex.com/index.php?id=383
-#
-
-interface ftdi
-ftdi_device_desc "STR9-comStick"
-ftdi_vid_pid 0x0640 0x002c
-
-ftdi_layout_init 0x0108 0x010b
-ftdi_layout_signal nTRST -data 0x0100
-ftdi_layout_signal nSRST -data 0x0200 -oe 0x0200
diff --git a/openocd-0.10.0/scripts/interface/ftdi/icebear.cfg b/openocd-0.10.0/scripts/interface/ftdi/icebear.cfg
deleted file mode 100644
index 2c03d417bfdefbda6a135c0e9ab54013d228348f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/icebear.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Section5 ICEBear
-#
-# http://section5.ch/icebear
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "ICEbear JTAG adapter"
-ftdi_vid_pid 0x0403 0xc140
-
-ftdi_layout_init 0x0028 0x002b
-ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
-ftdi_layout_signal nSRST -data 0x0020
diff --git a/openocd-0.10.0/scripts/interface/ftdi/iotlab-usb.cfg b/openocd-0.10.0/scripts/interface/ftdi/iotlab-usb.cfg
deleted file mode 100644
index fbbad0c86a81f14113138623cdf6e708e8cfa4dc..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/iotlab-usb.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# This is the integrated adapter as found on the IoT-LAB boards
-# https://github.com/iot-lab/iot-lab/wiki
-#
-
-interface ftdi
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0008 0x000b
-ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
-ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
diff --git a/openocd-0.10.0/scripts/interface/ftdi/jtag-lock-pick_tiny_2.cfg b/openocd-0.10.0/scripts/interface/ftdi/jtag-lock-pick_tiny_2.cfg
deleted file mode 100644
index c5e5db42081fa8d54f9704e964d7addab7f948b1..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/jtag-lock-pick_tiny_2.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# DISTORTEC JTAG-lock-pick Tiny 2
-#
-# http://www.distortec.com
-#
-
-interface ftdi
-ftdi_device_desc "JTAG-lock-pick Tiny 2"
-ftdi_vid_pid 0x0403 0x8220
-
-ftdi_layout_init 0x8c28 0xff3b
-ftdi_layout_signal SWD_EN -ndata 0x0020 -oe 0x2000
-ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
-ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
-ftdi_layout_signal SWDIO_OE -ndata 0x1000
-ftdi_layout_signal LED -ndata 0x8000
diff --git a/openocd-0.10.0/scripts/interface/ftdi/jtagkey.cfg b/openocd-0.10.0/scripts/interface/ftdi/jtagkey.cfg
deleted file mode 100644
index 7b87e6df1de36687e63ed7071af9cc5a27f087c8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/jtagkey.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Amontec JTAGkey
-#
-# http://www.amontec.com/jtagkey.shtml
-#
-
-interface ftdi
-ftdi_device_desc "Amontec JTAGkey"
-ftdi_vid_pid 0x0403 0xcff8
-
-ftdi_layout_init 0x0c08 0x0f1b
-ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
-ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/openocd-0.10.0/scripts/interface/ftdi/jtagkey2.cfg b/openocd-0.10.0/scripts/interface/ftdi/jtagkey2.cfg
deleted file mode 100644
index c6c2b32f45e2fc281dfa5856071f4232613f60fa..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/jtagkey2.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Amontec JTAGkey2
-#
-# http://www.amontec.com/jtagkey2.shtml
-#
-
-interface ftdi
-ftdi_device_desc "Amontec JTAGkey-2"
-ftdi_vid_pid 0x0403 0xcff8
-
-ftdi_layout_init 0x0c08 0x0f1b
-ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
-ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/openocd-0.10.0/scripts/interface/ftdi/jtagkey2p.cfg b/openocd-0.10.0/scripts/interface/ftdi/jtagkey2p.cfg
deleted file mode 100644
index dc9c4565e47b4e1f428f5234636effdbc594931b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/jtagkey2p.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Amontec JTAGkey2P
-#
-# http://www.amontec.com/jtagkey2p.shtml
-#
-
-interface ftdi
-ftdi_device_desc "Amontec JTAGkey-2P"
-ftdi_vid_pid 0x0403 0xcff8
-
-ftdi_layout_init 0x0c08 0x0f1b
-ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
-ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/openocd-0.10.0/scripts/interface/ftdi/kt-link.cfg b/openocd-0.10.0/scripts/interface/ftdi/kt-link.cfg
deleted file mode 100644
index 1f28d3a107884e001e732d7504e4f5c87dfb77ce..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/kt-link.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# Kristech KT-Link
-#
-# http://www.kristech.eu
-#
-
-interface ftdi
-ftdi_device_desc "KT-LINK"
-ftdi_vid_pid 0x0403 0xbbe2
-
-ftdi_layout_init 0x8c28 0xff3b
-ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
-ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
-ftdi_layout_signal LED -data 0x8000
-ftdi_layout_signal SWD_EN -ndata 0x0020 -oe 0x2000
-ftdi_layout_signal SWDIO_OE -ndata 0x1000
diff --git a/openocd-0.10.0/scripts/interface/ftdi/lisa-l.cfg b/openocd-0.10.0/scripts/interface/ftdi/lisa-l.cfg
deleted file mode 100644
index 67002bb96d7ca07a47d0266541451c27d867b2d7..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/lisa-l.cfg
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# Lisa/L
-#
-# http://paparazzi.enac.fr/wiki/Lisa
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on schematics and code"
-echo "in ft2232.c. Please report your experience with this file to openocd-devel"
-echo "mailing list, so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "Lisa/L"
-ftdi_vid_pid 0x0403 0x6010
-ftdi_channel 1
-
-ftdi_layout_init 0x0008 0x180b
-ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
-ftdi_layout_signal nSRST -data 0x0040 -oe 0x0040
-ftdi_layout_signal LED -data 0x1800
diff --git a/openocd-0.10.0/scripts/interface/ftdi/luminary-icdi.cfg b/openocd-0.10.0/scripts/interface/ftdi/luminary-icdi.cfg
deleted file mode 100644
index 2eea806d6e6efdb47203fbf8e0ebb3648fe51039..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/luminary-icdi.cfg
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# Luminary Micro Stellaris LM3S9B9x Evaluation Kits
-# In-Circuit Debug Interface (ICDI) Board
-#
-# Essentially all Luminary debug hardware is the same, (with both
-# JTAG and SWD support compatible with ICDI boards. This ICDI adapter
-# configuration is JTAG-only, but the same hardware handles SWD too.
-#
-# This is a discrete ftdi based debug board which supports ARM's
-# JTAG/SWD connectors in both backwards-compatible 20-pin format and
-# in the new-style compact 10-pin. There's also an 8-pin connector
-# with serial port support. It's included with LM3S9B9x eval boards.
-#
-# http://www.luminarymicro.com/products/ek-lm3s9b90.html
-# http://www.luminarymicro.com/products/ek-lm3s9b92.html
-#
-
-interface ftdi
-ftdi_device_desc "Luminary Micro ICDI Board"
-ftdi_vid_pid 0x0403 0xbcda
-
-ftdi_layout_init 0x00a8 0x00eb
-ftdi_layout_signal nSRST -noe 0x0020
-ftdi_layout_signal SWD_EN -ndata 0x0080
-ftdi_layout_signal SWDIO_OE -data 0x0008
diff --git a/openocd-0.10.0/scripts/interface/ftdi/luminary-lm3s811.cfg b/openocd-0.10.0/scripts/interface/ftdi/luminary-lm3s811.cfg
deleted file mode 100644
index 543b1e08fcfaa7bbb2c6d14091dd041fb1d5a58f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/luminary-lm3s811.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# Luminary Micro Stellaris LM3S811 Evaluation Kit
-#
-# http://www.luminarymicro.com/products/stellaris_811_evaluation_kits.html
-#
-# NOTE: this is only for boards *before* Rev C, which adds support
-# for SWO tracing with ADBUS_6 DBG_ENn and BDBUS_4 SWO_EN signals.
-# The "evb_lm3s811" layout doesn't set up those signals.
-#
-# Rev C boards work more like the other Stellaris eval boards. They
-# need to use the "luminary_icdi" layout to work correctly.
-#
-
-interface ftdi
-ftdi_device_desc "LM3S811 Evaluation Board"
-ftdi_vid_pid 0x0403 0xbcd9
-
-ftdi_layout_init 0x0088 0x008b
-ftdi_layout_signal nSRST -data 0x0020 -oe 0x0020
-ftdi_layout_signal SWD_EN -ndata 0x0080
-ftdi_layout_signal SWDIO_OE -data 0x0008
diff --git a/openocd-0.10.0/scripts/interface/ftdi/luminary.cfg b/openocd-0.10.0/scripts/interface/ftdi/luminary.cfg
deleted file mode 100644
index 20b54220e73b68012a08b9c221d8fd993fab628d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/luminary.cfg
+++ /dev/null
@@ -1,34 +0,0 @@
-#
-# Luminary Micro Stellaris Evaluation Kits
-#
-# http://www.luminarymicro.com/products/evaluation_kits.html
-#
-# There are a number of evaluation kits for Stellaris Cortex-M3 chips.
-# Currently they all bundle ftdi based debug support. When that is
-# used (instead of an external adapter), use this config file in one
-# of these two modes:
-#
-# - Eval board debug ... debug of the Stellaris chip via port A.
-#
-# - Other board debug ... same thing, but the board acts as a debug
-# adapter for another board (using a standard ARM JTAG connector).
-# The Stellaris chip stays in reset.
-#
-# Those support both JTAG and SWD. SWD is an ARM-only two-wire debug
-# protocol; in 2009, OpenOCD does not support SWD.
-#
-# Port B of the ftdi chip is normally used as a serial link to the
-# Stellaris chip. On most boards (but not older LM3S811 eval boards),
-# when SWD is used Port B may instead be used to read low-bandwidth
-# "SWO trace" data, including so-called "printf style" output from
-# firmware via the ITM module as well as profile data.
-#
-
-interface ftdi
-ftdi_device_desc "Stellaris Evaluation Board"
-ftdi_vid_pid 0x0403 0xbcd9
-
-ftdi_layout_init 0x00a8 0x00eb
-ftdi_layout_signal nSRST -noe 0x0020
-ftdi_layout_signal SWD_EN -ndata 0x0080
-ftdi_layout_signal SWDIO_OE -data 0x0008
diff --git a/openocd-0.10.0/scripts/interface/ftdi/m53evk.cfg b/openocd-0.10.0/scripts/interface/ftdi/m53evk.cfg
deleted file mode 100644
index 2b972704980c10fb831a539212e7f20d4c3ba337..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/m53evk.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# DENX M53EVK
-#
-# http://www.denx-cs.de/?q=M53EVK
-#
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_channel 0
-ftdi_layout_init 0x0008 0x000b
-ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
-ftdi_layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/openocd-0.10.0/scripts/interface/ftdi/mbftdi.cfg b/openocd-0.10.0/scripts/interface/ftdi/mbftdi.cfg
deleted file mode 100644
index d051cccb067441624555cfc171f1da8bfea772da..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/mbftdi.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# MBFTDI
-#
-# http://www.marsohod.org/prodmbftdi
-#
-# Also the Marsohod2 and the Marsohod3 boards
-# include a built-in MBFTDI for FPGA programming.
-# See http://www.marsohod.org/prodmarsohod2
-# and http://www.marsohod.org/plata-marsokhod3 for details.
-#
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0008 0x000b
diff --git a/openocd-0.10.0/scripts/interface/ftdi/minimodule.cfg b/openocd-0.10.0/scripts/interface/ftdi/minimodule.cfg
deleted file mode 100644
index 57249dfc14bd6e89908f705c3bc2789800b24320..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/minimodule.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# FTDI MiniModule
-#
-# http://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_FT2232H_Mini_Module.pdf
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "FT2232H MiniModule"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0018 0x05fb
-ftdi_layout_signal nSRST -data 0x0020
diff --git a/openocd-0.10.0/scripts/interface/ftdi/minispartan6.cfg b/openocd-0.10.0/scripts/interface/ftdi/minispartan6.cfg
deleted file mode 100644
index 8f1601192b7c01057cb0f058a2d634c1876dc53c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/minispartan6.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-# https://www.scarabhardware.com/minispartan6/
-# https://github.com/scarabhardware/miniSpartan6-plus/raw/master/miniSpartan6%2B_Rev_B.pdf
-interface ftdi
-# The miniSpartan6+ sadly doesn't have a custom device description, so we just
-# have to hope you got it right.
-#ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-# interface 1 is the uart
-ftdi_channel 0
-# just TCK TDI TDO TMS, no reset
-ftdi_layout_init 0x0008 0x000b
-reset_config none
-# this generally works fast: the fpga can handle 30MHz, the spi flash can handle
-# 54MHz with simple read, no dummy cycles, and wait-for-write-completion
-adapter_khz 30000
diff --git a/openocd-0.10.0/scripts/interface/ftdi/neodb.cfg b/openocd-0.10.0/scripts/interface/ftdi/neodb.cfg
deleted file mode 100644
index 6cc8ccf718b157aa6712db1d0e3fc413b86db537..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/neodb.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Openmoko USB JTAG/RS232 adapter
-#
-# http://wiki.openmoko.org/wiki/Debug_Board_v3
-#
-
-interface ftdi
-ftdi_device_desc "Debug Board for Neo1973"
-ftdi_vid_pid 0x1457 0x5118
-
-ftdi_layout_init 0x0508 0x0f1b
-ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100
-ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400
-ftdi_layout_signal nNOR_WP -data 0x0010 -oe 0x0010
diff --git a/openocd-0.10.0/scripts/interface/ftdi/ngxtech.cfg b/openocd-0.10.0/scripts/interface/ftdi/ngxtech.cfg
deleted file mode 100644
index 9eaa3c5bc69d6fe4fa1c8f63080c9408c5df35ef..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/ngxtech.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# NGX ARM USB JTAG
-#
-# http://shop.ngxtechnologies.com/product_info.php?cPath=26&products_id=30
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, but is assumed to work as this"
-echo "interface uses the same layout as configs that were verified. Please report your"
-echo "experience with this file to openocd-devel mailing list, so it could be marked"
-echo "as working or fixed."
-
-interface ftdi
-ftdi_device_desc "NGX JTAG"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0508 0x0f1b
-ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100
-ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/openocd-0.10.0/scripts/interface/ftdi/olimex-arm-jtag-swd.cfg b/openocd-0.10.0/scripts/interface/ftdi/olimex-arm-jtag-swd.cfg
deleted file mode 100644
index 2153fd65f59c83f84bdfc7d23191819f0e0f3864..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/olimex-arm-jtag-swd.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Olimex ARM JTAG SWD adapter
-# https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-SWD/
-#
-
-transport select swd
-
-ftdi_layout_signal SWD_EN -nalias nTRST
-ftdi_layout_signal SWDIO_OE -alias TMS
diff --git a/openocd-0.10.0/scripts/interface/ftdi/olimex-arm-usb-ocd-h.cfg b/openocd-0.10.0/scripts/interface/ftdi/olimex-arm-usb-ocd-h.cfg
deleted file mode 100644
index 5b27d38ba10e19f767e64e45e829a1b8383902cf..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/olimex-arm-usb-ocd-h.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Olimex ARM-USB-OCD-H
-#
-# http://www.olimex.com/dev/arm-usb-ocd-h.html
-#
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-OCD-H"
-ftdi_vid_pid 0x15ba 0x002b
-
-ftdi_layout_init 0x0908 0x0b1b
-ftdi_layout_signal nSRST -oe 0x0200
-ftdi_layout_signal nTRST -data 0x0100
-ftdi_layout_signal LED -data 0x0800
diff --git a/openocd-0.10.0/scripts/interface/ftdi/olimex-arm-usb-ocd.cfg b/openocd-0.10.0/scripts/interface/ftdi/olimex-arm-usb-ocd.cfg
deleted file mode 100644
index e1aeeeab6fee418996cf09fedb77fcf481d41128..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/olimex-arm-usb-ocd.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Olimex ARM-USB-OCD
-#
-# http://www.olimex.com/dev/arm-usb-ocd.html
-#
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG"
-ftdi_vid_pid 0x15ba 0x0003
-
-ftdi_layout_init 0x0c08 0x0f1b
-ftdi_layout_signal nSRST -oe 0x0200
-ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
-ftdi_layout_signal LED -data 0x0800
diff --git a/openocd-0.10.0/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg b/openocd-0.10.0/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg
deleted file mode 100644
index f77c24b2c0f07a228c5253802fe7caf0c63dc32e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/olimex-arm-usb-tiny-h.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Olimex ARM-USB-TINY-H
-#
-# http://www.olimex.com/dev/arm-usb-tiny-h.html
-#
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
-ftdi_vid_pid 0x15ba 0x002a
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
diff --git a/openocd-0.10.0/scripts/interface/ftdi/olimex-jtag-tiny.cfg b/openocd-0.10.0/scripts/interface/ftdi/olimex-jtag-tiny.cfg
deleted file mode 100644
index b3c6a716eab886c88f9377c24164d3fcb5fd0005..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/olimex-jtag-tiny.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Olimex ARM-USB-TINY
-#
-# http://www.olimex.com/dev/arm-usb-tiny.html
-#
-
-interface ftdi
-ftdi_device_desc "Olimex OpenOCD JTAG TINY"
-ftdi_vid_pid 0x15ba 0x0004
-
-ftdi_layout_init 0x0808 0x0a1b
-ftdi_layout_signal nSRST -oe 0x0200
-ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal LED -data 0x0800
diff --git a/openocd-0.10.0/scripts/interface/ftdi/oocdlink.cfg b/openocd-0.10.0/scripts/interface/ftdi/oocdlink.cfg
deleted file mode 100644
index fc09a16360d20b5076159cc9c8fc8c12cb80de6e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/oocdlink.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Joern Kaipf's OOCDLink
-#
-# http://www.joernonline.de/contrexx2/cms/index.php?page=126
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, but is assumed to work as this"
-echo "interface uses the same layout as configs that were verified. Please report your"
-echo "experience with this file to openocd-devel mailing list, so it could be marked"
-echo "as working or fixed."
-
-interface ftdi
-ftdi_device_desc "OOCDLink"
-ftdi_vid_pid 0x0403 0xbaf8
-
-ftdi_layout_init 0x0508 0x0f1b
-ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100
-ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/openocd-0.10.0/scripts/interface/ftdi/opendous_ftdi.cfg b/openocd-0.10.0/scripts/interface/ftdi/opendous_ftdi.cfg
deleted file mode 100644
index 6a12d72125e60c50804eb4f9882fabc3d6bc376d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/opendous_ftdi.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Opendous
-#
-# http://code.google.com/p/opendous/wiki/JTAG
-#
-# According to the website, it is similar to jtagkey, but it uses channel B
-# (and it has a different pid number).
-#
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-ftdi_channel 1
-
-ftdi_layout_init 0x0c08 0x0f1b
-ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
-ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
diff --git a/openocd-0.10.0/scripts/interface/ftdi/openocd-usb-hs.cfg b/openocd-0.10.0/scripts/interface/ftdi/openocd-usb-hs.cfg
deleted file mode 100644
index 37a717dc590c1c093ab829ea0bdadcf91e2e76a4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/openocd-usb-hs.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# embedded projects openocd usb adapter v3
-#
-# http://shop.embedded-projects.net/index.php?module=artikel&action=artikel&id=14
-#
-
-interface ftdi
-ftdi_device_desc "Dual RS232-HS"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0508 0x0f1b
-ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100
-ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/openocd-0.10.0/scripts/interface/ftdi/openocd-usb.cfg b/openocd-0.10.0/scripts/interface/ftdi/openocd-usb.cfg
deleted file mode 100644
index ff537c7b66c7ac7cc97cd5996fa0dc68ee029500..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/openocd-usb.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Hubert Hoegl's USB to JTAG
-#
-# http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html
-#
-
-interface ftdi
-ftdi_device_desc "Dual RS232"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0508 0x0f1b
-ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100
-ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/openocd-0.10.0/scripts/interface/ftdi/openrd.cfg b/openocd-0.10.0/scripts/interface/ftdi/openrd.cfg
deleted file mode 100644
index 8c1a80596b766d4c28396160641965cfbe420749..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/openrd.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Marvell OpenRD
-#
-# http://www.marvell.com/products/embedded_processors/developer/kirkwood/openrd.jsp
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "OpenRD JTAGKey FT2232D"
-ftdi_vid_pid 0x0403 0x9e90
-ftdi_channel 1
-
-ftdi_layout_init 0x0608 0x0f1b
-ftdi_layout_signal nTRST -data 0x0200
-ftdi_layout_signal nSRST -noe 0x0400
diff --git a/openocd-0.10.0/scripts/interface/ftdi/pipistrello.cfg b/openocd-0.10.0/scripts/interface/ftdi/pipistrello.cfg
deleted file mode 100644
index b51405a2d8107e94920b116cf4eaabc42a212e4a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/pipistrello.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-# http://pipistrello.saanlima.com/
-# http://www.saanlima.com/download/pipistrello-v2.0/pipistrello_v2_schematic.pdf
-interface ftdi
-ftdi_device_desc "Pipistrello LX45"
-ftdi_vid_pid 0x0403 0x6010
-# interface 1 is the uart
-ftdi_channel 0
-# just TCK TDI TDO TMS, no reset
-ftdi_layout_init 0x0008 0x000b
-reset_config none
-# this generally works fast: the fpga can handle 30MHz, the spi flash can handle
-# 54MHz with simple read, no dummy cycles, and wait-for-write-completion
-adapter_khz 30000
diff --git a/openocd-0.10.0/scripts/interface/ftdi/redbee-econotag.cfg b/openocd-0.10.0/scripts/interface/ftdi/redbee-econotag.cfg
deleted file mode 100644
index 70c30d658b0c2dd0db44b6b17aeb3320badd599d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/redbee-econotag.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# Redwire Redbee-Econotag
-#
-# http://www.redwirellc.com/store/node/1
-#
-# The Redbee-Econotag has an onboard FT2232H with:
-# - FT2232H channel A wired to mc13224v JTAG
-# - FT2232H channel B wired to mc13224v UART1
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0c08 0x0c2b
-ftdi_layout_signal nTRST -data 0x0800
-ftdi_layout_signal nSRST -data 0x0400
diff --git a/openocd-0.10.0/scripts/interface/ftdi/redbee-usb.cfg b/openocd-0.10.0/scripts/interface/ftdi/redbee-usb.cfg
deleted file mode 100644
index b79300d53bc3c359f5c869f5429604dfb611870a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/redbee-usb.cfg
+++ /dev/null
@@ -1,22 +0,0 @@
-#
-# Redwire Redbee-USB
-#
-# http://www.redwirellc.com
-#
-# The Redbee-USB has an onboard FT2232H with:
-# - FT2232H channel B wired to mc13224v JTAG
-# - FT2232H channel A wired to mc13224v UART1
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_vid_pid 0x0403 0x6010
-ftdi_channel 1
-
-ftdi_layout_init 0x0c08 0x0c2b
-ftdi_layout_signal nTRST -data 0x0800
-ftdi_layout_signal nSRST -data 0x0400
diff --git a/openocd-0.10.0/scripts/interface/ftdi/rowley-cc-arm-swd.cfg b/openocd-0.10.0/scripts/interface/ftdi/rowley-cc-arm-swd.cfg
deleted file mode 100644
index 9a96dbd9250e2b1551c1a1b8f0e15e32b042c33b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/rowley-cc-arm-swd.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Rowley ARM SWD Adapter
-# http://sites.fastspring.com/rowley/product/armswdadapter
-# https://drive.google.com/file/d/0Bzv7UpKpOQhnTUNNdzI5OUR4WGs/edit?usp=sharing
-#
-
-transport select swd
-
-ftdi_layout_signal SWD_EN -nalias nTRST
-ftdi_layout_signal SWDIO_OE -alias TMS
diff --git a/openocd-0.10.0/scripts/interface/ftdi/sheevaplug.cfg b/openocd-0.10.0/scripts/interface/ftdi/sheevaplug.cfg
deleted file mode 100644
index f299f27a90e7183f2d6b81841fe9c9661bc6c617..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/sheevaplug.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Marvel SheevaPlug Development Kit
-#
-# http://www.marvell.com/products/embedded_processors/developer/kirkwood/sheevaplug.jsp
-#
-
-interface ftdi
-ftdi_device_desc "SheevaPlug JTAGKey FT2232D B"
-ftdi_vid_pid 0x9e88 0x9e8f
-ftdi_channel 1
-
-ftdi_layout_init 0x0608 0x0f1b
-ftdi_layout_signal nTRST -data 0x0200
-ftdi_layout_signal nSRST -noe 0x0400
diff --git a/openocd-0.10.0/scripts/interface/ftdi/signalyzer-lite.cfg b/openocd-0.10.0/scripts/interface/ftdi/signalyzer-lite.cfg
deleted file mode 100644
index 4988a3bfd447fbb7d5cb78e0e404ee7d39ce22fb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/signalyzer-lite.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Xverve Signalyzer LITE (DT-USB-SLITE)
-#
-# http://www.signalyzer.com
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "Signalyzer LITE"
-ftdi_vid_pid 0x0403 0xbca1
-
-ftdi_layout_init 0x0008 0x000b
-ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
-ftdi_layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/openocd-0.10.0/scripts/interface/ftdi/signalyzer.cfg b/openocd-0.10.0/scripts/interface/ftdi/signalyzer.cfg
deleted file mode 100644
index e2629beec9a03de32e3483391678fcf9f69c7e3a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/signalyzer.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Xverve Signalyzer Tool (DT-USB-ST)
-#
-# http://www.signalyzer.com
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on code in ft2232.c."
-echo "Please report your experience with this file to openocd-devel mailing list,"
-echo "so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "Signalyzer"
-ftdi_vid_pid 0x0403 0xbca0
-
-ftdi_layout_init 0x0008 0x000b
-ftdi_layout_signal nTRST -data 0x0010 -oe 0x0010
-ftdi_layout_signal nSRST -data 0x0020 -oe 0x0020
diff --git a/openocd-0.10.0/scripts/interface/ftdi/stm32-stick.cfg b/openocd-0.10.0/scripts/interface/ftdi/stm32-stick.cfg
deleted file mode 100644
index 2aff1fe8fd9b080166c7f8596e5569f055155e86..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/stm32-stick.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Hitex STM32-PerformanceStick
-#
-# http://www.hitex.com/index.php?id=340
-#
-
-interface ftdi
-ftdi_device_desc "STM32-PerformanceStick"
-ftdi_vid_pid 0x0640 0x002d
-
-ftdi_layout_init 0x0388 0x038b
-ftdi_layout_signal nTRST -data 0x0100
-ftdi_layout_signal nSRST -data 0x0080 -noe 0x200
diff --git a/openocd-0.10.0/scripts/interface/ftdi/swd-resistor-hack.cfg b/openocd-0.10.0/scripts/interface/ftdi/swd-resistor-hack.cfg
deleted file mode 100644
index 04f3a73975782174f0e218c3ab528809348b0885..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/swd-resistor-hack.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# Connect TDI to SWDIO via a suitable series resistor (220-470 Ohm or
-# so depending on the drive capability of the target and adapter);
-# connect TDO directly to SWDIO.
-#
-# You also need to have reliable GND connection between the target and
-# adapter. Vref of the adapter should be supplied with a voltage equal
-# to the target's (preferrably connect it to Vcc). You can also
-# optionally connect nSRST. Leave everything else unconnected.
-#
-# FTDI Target
-# ---- ------
-# 1 - Vref ----------------- Vcc
-# 3 - nTRST -
-# 4 - GND ----------------- GND
-# 5 - TDI ---/\470 Ohm/\--- SWDIO
-# 7 - TMS -
-# 9 - TCK ----------------- SWCLK
-# 11 - RTCK -
-# 13 - TDO ----------------- SWDIO
-# 15 - nSRST - - - - - - - - - nRESET
-#
-
-transport select swd
-
-ftdi_layout_signal SWD_EN -data 0
diff --git a/openocd-0.10.0/scripts/interface/ftdi/ti-icdi.cfg b/openocd-0.10.0/scripts/interface/ftdi/ti-icdi.cfg
deleted file mode 100644
index 6af809cd96f8f724e9a2d1c78341464e0fc95ff0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/ti-icdi.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# This is an FTDI-based debugging solution as found on some TI boards,
-# e.g. CC3200 LaunchPad.
-#
-# The schematics are identical to luminary-icdi (including SWD
-# support) but the USB IDs are different.
-#
-
-interface ftdi
-ftdi_vid_pid 0x0451 0xc32a
-
-ftdi_layout_init 0x00a8 0x00eb
-ftdi_layout_signal nSRST -noe 0x0020
-ftdi_layout_signal SWD_EN -ndata 0x0080
-ftdi_layout_signal SWDIO_OE -data 0x0008
diff --git a/openocd-0.10.0/scripts/interface/ftdi/tumpa-lite.cfg b/openocd-0.10.0/scripts/interface/ftdi/tumpa-lite.cfg
deleted file mode 100644
index 657515a91f2f42f55298e29749299b7b094a393c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/tumpa-lite.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# TIAO USB Multi-Protocol Adapter (TUMPA) Lite
-#
-# http://www.diygadget.com/tiao-usb-multi-protocol-adapter-lite-jtag-spi-i2c-serial.html
-#
-
-interface ftdi
-ftdi_vid_pid 0x0403 0x8a99
-
-ftdi_layout_init 0x0038 0x087b
-ftdi_layout_signal nTRST -data 0x0020 -oe 0x0020
-ftdi_layout_signal nSRST -data 0x0010 -oe 0x0010
diff --git a/openocd-0.10.0/scripts/interface/ftdi/tumpa.cfg b/openocd-0.10.0/scripts/interface/ftdi/tumpa.cfg
deleted file mode 100644
index e4b59b118b6e7ca9d9b338b0f2847a3d93172b5c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/tumpa.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# TIAO USB Multi-Protocol Adapter (TUMPA)
-#
-# http://www.diygadget.com/tiao-usb-multi-protocol-adapter-jtag-spi-i2c-serial.html
-#
-
-interface ftdi
-ftdi_vid_pid 0x0403 0x8a98 0x0403 0x6010
-
-ftdi_layout_init 0x0038 0x087b
-ftdi_layout_signal nTRST -data 0x0020
-ftdi_layout_signal nSRST -data 0x0010
-
-reset_config srst_push_pull
diff --git a/openocd-0.10.0/scripts/interface/ftdi/turtelizer2-revB.cfg b/openocd-0.10.0/scripts/interface/ftdi/turtelizer2-revB.cfg
deleted file mode 100644
index 45840402acf9eb9674e811b580862ad0b07fbd70..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/turtelizer2-revB.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# egnite Turtelizer 2 rev B (with SRST only)
-#
-# http://www.ethernut.de/en/hardware/turtelizer/index.html
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, it is based on schematics and code"
-echo "in ft2232.c. Please report your experience with this file to openocd-devel"
-echo "mailing list, so it could be marked as working or fixed."
-
-interface ftdi
-ftdi_device_desc "Turtelizer JTAG/RS232 Adapter"
-ftdi_vid_pid 0x0403 0xbdc8
-
-ftdi_layout_init 0x0008 0x0c5b
-ftdi_layout_signal nSRST -oe 0x0040
-ftdi_layout_signal LED -data 0x0c00
diff --git a/openocd-0.10.0/scripts/interface/ftdi/turtelizer2-revC.cfg b/openocd-0.10.0/scripts/interface/ftdi/turtelizer2-revC.cfg
deleted file mode 100644
index 918ac497b76722719faf9f281cfca9f596de7766..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/turtelizer2-revC.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# egnite Turtelizer 2 revC (with TRST and SRST)
-#
-# http://www.ethernut.de/en/hardware/turtelizer/index.html
-#
-
-interface ftdi
-ftdi_device_desc "Turtelizer JTAG/RS232 Adapter"
-ftdi_vid_pid 0x0403 0xbdc8
-
-ftdi_layout_init 0x0008 0x0c7b
-ftdi_layout_signal nTRST -oe 0x0020
-ftdi_layout_signal nSRST -oe 0x0040
-ftdi_layout_signal LED -ndata 0x0c00
diff --git a/openocd-0.10.0/scripts/interface/ftdi/um232h.cfg b/openocd-0.10.0/scripts/interface/ftdi/um232h.cfg
deleted file mode 100644
index 6ba6f43b2aec0c00fcf3521f8e12445ce7a2b85b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/um232h.cfg
+++ /dev/null
@@ -1,35 +0,0 @@
-#
-# FTDI UM232H as a JTAG interface
-#
-# http://www.ftdichip.com/Products/Modules/DevelopmentModules.htm#UM232H
-#
-# This should also work with a UM232H-B, but that has not been tested.
-# Note that UM232H and UM232H-B are 3.3V only.
-#
-
-interface ftdi
-#ftdi_device_desc "UM232H"
-ftdi_vid_pid 0x0403 0x6014
-
-ftdi_layout_init 0xfff8 0xfffb
-ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
-ftdi_layout_signal nSRST -data 0x0200 -oe 0x0200
-
-# UM232H FT232H JTAG
-# Name Pin Name Func
-# AD0 J2-6 ADBUS0 TCK
-# AD1 J2-7 ADBUS1 TDI
-# AD2 J2-8 ADBUS2 TDO
-# AD3 J2-9 ADBUS3 TMS
-# AD4 J2-10 ADBUS4 (GPIOL0)
-# AD5 J2-11 ADBUS5 (GPIOL1)
-# AD6 J2-12 ADBUS6 (GPIOL2)
-# AD7 J2-13 ADBUS7 (GPIOL3)
-# AD0 J1-14 ACBUS0 /TRST
-# AD1 J1-13 ACBUS1 /SRST
-# AD2 J1-12 ACBUS2 (GPIOH2)
-# AD3 J1-11 ACBUS3 (GPIOH3)
-# AD4 J1-10 ACBUS4 (GPIOH4)
-# AD5 J1-9 ACBUS5 (GPIOH5)
-# AD6 J1-8 ACBUS6 (GPIOH6)
-# AD7 J1-7 ACBUS7 (GPIOH7)
diff --git a/openocd-0.10.0/scripts/interface/ftdi/vpaclink.cfg b/openocd-0.10.0/scripts/interface/ftdi/vpaclink.cfg
deleted file mode 100644
index 20576196405c8c6e0af94849cc20595048209247..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/vpaclink.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Voipac VPACLink
-#
-# http://voipac.com/27M-JTG-000
-#
-
-echo "WARNING!"
-echo "This file was not tested with real interface, but is assumed to work as this"
-echo "interface uses the same layout as configs that were verified. Please report your"
-echo "experience with this file to openocd-devel mailing list, so it could be marked"
-echo "as working or fixed."
-
-interface ftdi
-ftdi_device_desc "VPACLink"
-ftdi_vid_pid 0x0403 0x6010
-
-ftdi_layout_init 0x0508 0x0f1b
-ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100
-ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400
diff --git a/openocd-0.10.0/scripts/interface/ftdi/xds100v2.cfg b/openocd-0.10.0/scripts/interface/ftdi/xds100v2.cfg
deleted file mode 100644
index 2628aa0869599587a39ed343a6f66aaefaa1e718..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/xds100v2.cfg
+++ /dev/null
@@ -1,58 +0,0 @@
-#
-# Texas Instruments XDS100v2
-#
-# http://processors.wiki.ti.com/index.php/XDS100#XDS100v2_Features
-#
-# Detailed documentation is available only as CPLD verilog source code
-# to the registered TI users.
-#
-
-interface ftdi
-ftdi_vid_pid 0x0403 0xa6d0 0x0403 0x6010
-
-ftdi_layout_init 0x0038 0x597b
-
-# 8000 z - unused
-# 4000 0 > CPLD loopback (all target side pins high-Z)
-# 2000 z < !( cable connected ) (open drain on CPLD side for $reasons)
-# 1000 0 > EMU1_oe
-#
-# 800 0 > PWR_RST = clear power-loss flag on rising edge
-# 400 z < !( power-loss flag )
-# 200 z < nSRST
-# 100 0 > nSRST_oe
-#
-# 80 z < RTCK
-# 40 0 > EMU0_oe
-# 20 1 > EMU_EN
-# 10 1 > nTRST
-#
-# 8 1 > TMS
-# 4 z < TDO
-# 2 0 > TDI
-# 1 0 > TCK
-#
-# As long as the power-loss flag is set, all target-side pins are
-# high-Z except the EMU-pins for which the opposite holds unless
-# EMU_EN is high.
-#
-# To use wait-in-reset, drive EMU0 low at power-on reset. If the
-# target normally reuses EMU0 for other purposes, clear EMU_EN to
-# keep the EMU pins high-Z until the target is power-cycled.
-#
-# The LED only turns off at USB suspend, which is also the only way to
-# set the power-loss flag manually. (Can be done in software e.g. by
-# changing the USB configuration to zero.)
-#
-
-ftdi_layout_signal nTRST -data 0x0010
-ftdi_layout_signal nSRST -oe 0x0100
-ftdi_layout_signal EMU_EN -data 0x0020
-ftdi_layout_signal EMU0 -oe 0x0040
-ftdi_layout_signal EMU1 -oe 0x1000
-ftdi_layout_signal PWR_RST -data 0x0800
-ftdi_layout_signal LOOPBACK -data 0x4000
-
-echo "\nInfo : to use this adapter you MUST add ``init; ftdi_set_signal PWR_RST 1; jtag arp_init'' to the end of your config file!\n"
-# note: rising edge on PWR_RST is also needed after power-cycling the
-# target
diff --git a/openocd-0.10.0/scripts/interface/ftdi/xds100v3.cfg b/openocd-0.10.0/scripts/interface/ftdi/xds100v3.cfg
deleted file mode 100644
index 6c705823ad4c524fd7dd64c840800460da7052c7..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ftdi/xds100v3.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Texas Instruments XDS100 ver 3.0
-#
-# http://processors.wiki.ti.com/index.php/XDS100
-#
-
-# Version 3.0 is the same as 2.0 as far as OpenOCD is concerned
-source [find interface/ftdi/xds100v2.cfg]
-
-# The USB ids are different.
-ftdi_vid_pid 0x0403 0xa6d1
diff --git a/openocd-0.10.0/scripts/interface/jlink.cfg b/openocd-0.10.0/scripts/interface/jlink.cfg
deleted file mode 100644
index a4f9dddd76557ec660406e7292bb26b771740ebf..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/jlink.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# SEGGER J-Link
-#
-# http://www.segger.com/jlink.html
-#
-
-interface jlink
-
-# The serial number can be used to select a specific device in case more than
-# one is connected to the host.
-#
-# Example: Select J-Link with serial number 123456789
-#
-# jlink serial 123456789
diff --git a/openocd-0.10.0/scripts/interface/jtag_vpi.cfg b/openocd-0.10.0/scripts/interface/jtag_vpi.cfg
deleted file mode 100644
index a37a11ed058fb10bb7e71e8cd157bc44611362d3..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/jtag_vpi.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-interface jtag_vpi
-
-# Set the VPI JTAG server port
-if { [info exists VPI_PORT] } {
- set _VPI_PORT $VPI_PORT
-} else {
- set _VPI_PORT 5555
-}
-
-# Set the VPI JTAG server address
-if { [info exists VPI_ADDRESS] } {
- set _VPI_ADDRESS $VPI_ADDRESS
-} else {
- set _VPI_ADDRESS "127.0.0.1"
-}
-
-jtag_vpi_set_port $_VPI_PORT
-jtag_vpi_set_address $_VPI_ADDRESS
diff --git a/openocd-0.10.0/scripts/interface/nds32-aice.cfg b/openocd-0.10.0/scripts/interface/nds32-aice.cfg
deleted file mode 100644
index 5363b4c1db518651cf6cc1ad5fef70f86b73f9a4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/nds32-aice.cfg
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Andes AICE
-#
-# http://www.andestech.com
-#
-
-interface aice
-aice desc "Andes AICE adapter"
-aice serial "C001-42163"
-aice vid_pid 0x1CFC 0x0000
-aice port aice_usb
-reset_config trst_and_srst
-adapter_khz 24000
-aice retry_times 50
-aice count_to_check_dbger 30
diff --git a/openocd-0.10.0/scripts/interface/opendous.cfg b/openocd-0.10.0/scripts/interface/opendous.cfg
deleted file mode 100644
index 21ced6fbe7603e8edc7b325f2e6b89415adaa2d7..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/opendous.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# opendous-jtag
-#
-# http://code.google.com/p/opendous-jtag/
-#
-
-interface opendous
diff --git a/openocd-0.10.0/scripts/interface/openjtag.cfg b/openocd-0.10.0/scripts/interface/openjtag.cfg
deleted file mode 100644
index b20c22b6c624ffaf4905c5aa175b9c3a87ec62a0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/openjtag.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# OpenJTAG
-#
-# www.openjtag.org
-#
-
-interface openjtag
-openjtag_device_desc "Open JTAG Project"
\ No newline at end of file
diff --git a/openocd-0.10.0/scripts/interface/osbdm.cfg b/openocd-0.10.0/scripts/interface/osbdm.cfg
deleted file mode 100644
index e88ce50b594681ede42096edf942cb01e60d19d7..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/osbdm.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# P&E Micro OSBDM (aka OSJTAG) interface
-#
-# http://pemicro.com/osbdm/
-#
-interface osbdm
-reset_config srst_only
diff --git a/openocd-0.10.0/scripts/interface/parport.cfg b/openocd-0.10.0/scripts/interface/parport.cfg
deleted file mode 100644
index ae3f8f15874e71d1ad6fabbc52bedb9c44dfdd6f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/parport.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Parallel port wiggler (many clones available) on port 0x378
-#
-# Addresses: 0x378/LPT1 or 0x278/LPT2 ...
-#
-
-if { [info exists PARPORTADDR] } {
- set _PARPORTADDR $PARPORTADDR
-} else {
- if {$tcl_platform(platform) eq "windows"} {
- set _PARPORTADDR 0x378
- } {
- set _PARPORTADDR 0
- }
-}
-
-interface parport
-parport_port $_PARPORTADDR
-parport_cable wiggler
diff --git a/openocd-0.10.0/scripts/interface/parport_dlc5.cfg b/openocd-0.10.0/scripts/interface/parport_dlc5.cfg
deleted file mode 100644
index 98345808eb76f0a9c76fdadae02dd1872a231f6c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/parport_dlc5.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# Xilinx Parallel Cable III 'DLC 5' (and various clones)
-#
-# http://www.xilinx.com/itp/xilinx4/data/docs/pac/appendixb.html
-#
-
-if { [info exists PARPORTADDR] } {
- set _PARPORTADDR $PARPORTADDR
-} else {
- set _PARPORTADDR 0
-}
-
-interface parport
-parport_port $_PARPORTADDR
-parport_cable dlc5
-
diff --git a/openocd-0.10.0/scripts/interface/raspberrypi-native.cfg b/openocd-0.10.0/scripts/interface/raspberrypi-native.cfg
deleted file mode 100644
index 6b73f3541eec9d782644d17f30fd2a6b6f421675..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/raspberrypi-native.cfg
+++ /dev/null
@@ -1,35 +0,0 @@
-#
-# Config for using Raspberry Pi's expansion header
-#
-# This is best used with a fast enough buffer but also
-# is suitable for direct connection if the target voltage
-# matches RPi's 3.3V and the cable is short enough.
-#
-# Do not forget the GND connection, pin 6 of the expansion header.
-#
-
-interface bcm2835gpio
-
-bcm2835gpio_peripheral_base 0x20000000
-
-# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
-# These depend on system clock, calibrated for stock 700MHz
-# bcm2835gpio_speed SPEED_COEFF SPEED_OFFSET
-bcm2835gpio_speed_coeffs 113714 28
-
-# Each of the JTAG lines need a gpio number set: tck tms tdi tdo
-# Header pin numbers: 23 22 19 21
-bcm2835gpio_jtag_nums 11 25 10 9
-
-# If you define trst or srst, use appropriate reset_config
-# Header pin numbers: TRST - 26, SRST - 18
-
-# bcm2835gpio_trst_num 7
-# reset_config trst_only
-
-# bcm2835gpio_srst_num 24
-# reset_config srst_only srst_push_pull
-
-# or if you have both connected,
-# reset_config trst_and_srst srst_push_pull
-
diff --git a/openocd-0.10.0/scripts/interface/raspberrypi2-native.cfg b/openocd-0.10.0/scripts/interface/raspberrypi2-native.cfg
deleted file mode 100644
index f846fa25dfe923569f01fd2a3e0c81cf33539b94..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/raspberrypi2-native.cfg
+++ /dev/null
@@ -1,42 +0,0 @@
-#
-# Config for using Raspberry Pi's expansion header
-#
-# This is best used with a fast enough buffer but also
-# is suitable for direct connection if the target voltage
-# matches RPi's 3.3V and the cable is short enough.
-#
-# Do not forget the GND connection, pin 6 of the expansion header.
-#
-
-interface bcm2835gpio
-
-bcm2835gpio_peripheral_base 0x3F000000
-
-# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
-# These depend on system clock, calibrated for stock 700MHz
-# bcm2835gpio_speed SPEED_COEFF SPEED_OFFSET
-bcm2835gpio_speed_coeffs 146203 36
-
-# Each of the JTAG lines need a gpio number set: tck tms tdi tdo
-# Header pin numbers: 23 22 19 21
-# bcm2835gpio_jtag_nums 11 25 10 9
-
-# or if you have both connected,
-# reset_config trst_and_srst srst_push_pull
-
-# Each of the SWD lines need a gpio number set: swclk swdio
-# Header pin numbers: 22 18
-bcm2835gpio_swd_nums 25 24
-
-# If you define trst or srst, use appropriate reset_config
-# Header pin numbers: TRST - 26, SRST - 18
-
-# bcm2835gpio_trst_num 7
-# reset_config trst_only
-
-bcm2835gpio_srst_num 18
-reset_config srst_only srst_push_pull
-
-# or if you have both connected,
-# reset_config trst_and_srst srst_push_pull
-
diff --git a/openocd-0.10.0/scripts/interface/rlink.cfg b/openocd-0.10.0/scripts/interface/rlink.cfg
deleted file mode 100644
index 2f13cc4893ff4aabacec12724c6ba6524b45dfca..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/rlink.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Raisonance RLink
-#
-# http://www.mcu-raisonance.com/~rlink-debugger-programmer__microcontrollers__tool~tool__T018:4cn9ziz4bnx6.html
-#
-
-interface rlink
-
diff --git a/openocd-0.10.0/scripts/interface/stlink-v1.cfg b/openocd-0.10.0/scripts/interface/stlink-v1.cfg
deleted file mode 100644
index 13f207dc6b467f76ec8e3df342a75d04a25598ce..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/stlink-v1.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# STMicroelectronics ST-LINK/V1 in-circuit debugger/programmer
-#
-
-interface hla
-hla_layout stlink
-hla_device_desc "ST-LINK/V1"
-hla_vid_pid 0x0483 0x3744
-
diff --git a/openocd-0.10.0/scripts/interface/stlink-v2-1.cfg b/openocd-0.10.0/scripts/interface/stlink-v2-1.cfg
deleted file mode 100644
index 093e80177078667dbc03e166ac5d7e997086b4f2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/stlink-v2-1.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# STMicroelectronics ST-LINK/V2-1 in-circuit debugger/programmer
-#
-
-interface hla
-hla_layout stlink
-hla_device_desc "ST-LINK/V2-1"
-hla_vid_pid 0x0483 0x374b
-
-# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2
-# devices seem to have serial numbers with unreadable characters. ST-LINK/V2
-# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
-# number reset issues.
-# eg.
-#hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
-
diff --git a/openocd-0.10.0/scripts/interface/stlink-v2.cfg b/openocd-0.10.0/scripts/interface/stlink-v2.cfg
deleted file mode 100644
index ae545a1187762bbdbb80e24913dbe746421310f5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/stlink-v2.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# STMicroelectronics ST-LINK/V2 in-circuit debugger/programmer
-#
-
-interface hla
-hla_layout stlink
-hla_device_desc "ST-LINK/V2"
-hla_vid_pid 0x0483 0x3748
-
-# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2
-# devices seem to have serial numbers with unreadable characters. ST-LINK/V2
-# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
-# number reset issues.
-# eg.
-#hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
-
diff --git a/openocd-0.10.0/scripts/interface/sysfsgpio-raspberrypi.cfg b/openocd-0.10.0/scripts/interface/sysfsgpio-raspberrypi.cfg
deleted file mode 100644
index 36364228478c6f2377aec7960f5db4e711264857..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/sysfsgpio-raspberrypi.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# Config for using RaspberryPi's expansion header
-#
-# This is best used with a fast enough buffer but also
-# is suitable for direct connection if the target voltage
-# matches RPi's 3.3V
-#
-# Do not forget the GND connection, pin 6 of the expansion header.
-#
-
-interface sysfsgpio
-
-# Each of the JTAG lines need a gpio number set: tck tms tdi tdo
-# Header pin numbers: 23 22 19 21
-sysfsgpio_jtag_nums 11 25 10 9
-
-# At least one of srst or trst needs to be specified
-# Header pin numbers: TRST - 26, SRST - 18
-sysfsgpio_trst_num 7
-# sysfsgpio_srst_num 24
-
diff --git a/openocd-0.10.0/scripts/interface/ti-icdi.cfg b/openocd-0.10.0/scripts/interface/ti-icdi.cfg
deleted file mode 100644
index 0fc3a9b6755181bb351f7b32833752c9bb151c5d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ti-icdi.cfg
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# TI Stellaris In-Circuit Debug Interface (ICDI) Board
-#
-# This is the propriety ICDI interface used on newer boards such as
-# LM4F232 Evaluation Kit - http://www.ti.com/tool/ek-lm4f232
-# Stellaris Launchpad - http://www.ti.com/stellaris-launchpad
-# http://www.ti.com/tool/ek-lm4f232
-#
-
-interface hla
-hla_layout ti-icdi
-hla_vid_pid 0x1cbe 0x00fd
-
diff --git a/openocd-0.10.0/scripts/interface/ulink.cfg b/openocd-0.10.0/scripts/interface/ulink.cfg
deleted file mode 100644
index 3b1fad071c3cd88207901c02af9fa49dbd1e8130..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/ulink.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Keil ULINK running OpenULINK firmware.
-#
-# http://www.keil.com/ulink1/
-# http://article.gmane.org/gmane.comp.debugging.openocd.devel/17362
-#
-
-interface ulink
diff --git a/openocd-0.10.0/scripts/interface/usb-jtag.cfg b/openocd-0.10.0/scripts/interface/usb-jtag.cfg
deleted file mode 100644
index cb4d29bbc93f58e44438de443bd6fc547a9eab8d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/usb-jtag.cfg
+++ /dev/null
@@ -1,37 +0,0 @@
-# ixo-usb-jtag - Emulation of a Altera Bus Blaster I on a Cypress FX2 IC.
-#
-# The ixo-usb-jtag firmware can be loaded onto a bunch of different hardware
-# including;
-# * Xilinx USB Platform Cable
-# * Many Digilent boards such as the Nexys, Nexys 2 and Atlys boards
-# * Many fpga4fun.com boards from such as the Saxo and Xylo boards
-# * The Numato Opsis
-#
-# Original version - http://www.ixo.de/info/usb_jtag/
-# Updated version - http://ixo-jtag.sourceforge.net/
-# Newest version - http://github.com/mithro/ixo-usb-jtag
-#
-# Procedure for using is;
-# * Get the ixo-usb-jtag firmware for your hardware (or build it yourself).
-# * Load the firmware using the fxload tool.
-# * Use openocd.
-#
-# Unless you burn the firmware into the EEPROM on your device, power cycling
-# will require you to reload the firmware using the fxload tool. This can be
-# automated by using udev rules (which can be found in the firmware
-# repository).
-#
-# Ubuntu packages built from mithro's version (with prebuilt firmware and udev
-# rules) can be found at
-# https://launchpad.net/~timvideos/+archive/ubuntu/fpga-support
-#
-# TODO: Refactor the usb_blaster driver to allow loading firmware using any low
-# level driver. Loading firmware is currently only supported on the ublast2
-# driver but ixo-usb-jtag requires the ftdi driver.
-
-interface usb_blaster
-usb_blaster_vid_pid 0x16C0 0x06AD
-usb_blaster_device_desc "Van Ooijen Technische Informatica"
-# ixo-usb-jtag is only compatible with the ublast1 protocol implemented via the
-# ftdi modes, using ublast2 will cause openocd to hang.
-usb_blaster_lowlevel_driver ftdi
diff --git a/openocd-0.10.0/scripts/interface/usbprog.cfg b/openocd-0.10.0/scripts/interface/usbprog.cfg
deleted file mode 100644
index b4f0da328399634f209b87c05f007f1cc4be0d28..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/usbprog.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Embedded Projects USBprog
-#
-# http://embedded-projects.net/index.php?page_id=135
-#
-
-interface usbprog
-# USBprog is broken w/short TMS sequences, this is a workaround
-# until the C code can be fixed.
-tms_sequence long
diff --git a/openocd-0.10.0/scripts/interface/vsllink.cfg b/openocd-0.10.0/scripts/interface/vsllink.cfg
deleted file mode 100644
index fad7934904c664c2a29d1086dd524832f0806c31..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/interface/vsllink.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Versaloon Link -- VSLLink
-#
-# http://www.versaloon.com/
-#
-
-interface vsllink
-
diff --git a/openocd-0.10.0/scripts/mem_helper.tcl b/openocd-0.10.0/scripts/mem_helper.tcl
deleted file mode 100644
index 86ad00f7ebb91672ff730c967d815d59eea75fd1..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/mem_helper.tcl
+++ /dev/null
@@ -1,31 +0,0 @@
-# Helper for common memory read/modify/write procedures
-
-# mrw: "memory read word", returns value of $reg
-proc mrw {reg} {
- set value ""
- mem2array value 32 $reg 1
- return $value(0)
-}
-
-add_usage_text mrw "address"
-add_help_text mrw "Returns value of word in memory."
-
-proc mrb {reg} {
- set value ""
- mem2array value 8 $reg 1
- return $value(0)
-}
-
-add_usage_text mrb "address"
-add_help_text mrb "Returns value of byte in memory."
-
-# mmw: "memory modify word", updates value of $reg
-# $reg <== ((value & ~$clearbits) | $setbits)
-proc mmw {reg setbits clearbits} {
- set old [mrw $reg]
- set new [expr ($old & ~$clearbits) | $setbits]
- mww $reg $new
-}
-
-add_usage_text mmw "address setbits clearbits"
-add_help_text mmw "Modify word in memory. new_val = (old_val & ~clearbits) | setbits;"
diff --git a/openocd-0.10.0/scripts/memory.tcl b/openocd-0.10.0/scripts/memory.tcl
deleted file mode 100644
index 83c96d6c9deacd0cad754d86acc06f4ae73823fa..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/memory.tcl
+++ /dev/null
@@ -1,187 +0,0 @@
-# MEMORY
-#
-# All Memory regions have two components.
-# (1) A count of regions, in the form N_NAME
-# (2) An array within info about each region.
-#
-# The ARRAY
-#
-# <NAME>( RegionNumber , ATTRIBUTE )
-#
-# Where <NAME> is one of:
-#
-# N_FLASH & FLASH (internal memory)
-# N_RAM & RAM (internal memory)
-# N_MMREGS & MMREGS (for memory mapped registers)
-# N_XMEM & XMEM (off chip memory, ie: flash on cs0, sdram on cs2)
-# or N_UNKNOWN & UNKNOWN for things that do not exist.
-#
-# We have 1 unknown region.
-set N_UNKNOWN 1
-# All MEMORY regions must have these attributes
-# CS - chip select (if internal, use -1)
-set UNKNOWN(0,CHIPSELECT) -1
-# BASE - base address in memory
-set UNKNOWN(0,BASE) 0
-# LEN - length in bytes
-set UNKNOWN(0,LEN) $CPU_MAX_ADDRESS
-# HUMAN - human name of the region
-set UNKNOWN(0,HUMAN) "unknown"
-# TYPE - one of:
-# flash, ram, mmr, unknown
-# For harvard arch:
-# iflash, dflash, iram, dram
-set UNKNOWN(0,TYPE) "unknown"
-# RWX - access ablity
-# unix style chmod bits
-# 0 - no access
-# 1 - execute
-# 2 - write
-# 4 - read
-# hence: 7 - readwrite execute
-set RWX_NO_ACCESS 0
-set RWX_X_ONLY $BIT0
-set RWX_W_ONLY $BIT1
-set RWX_R_ONLY $BIT2
-set RWX_RW [expr $RWX_R_ONLY + $RWX_W_ONLY]
-set RWX_R_X [expr $RWX_R_ONLY + $RWX_X_ONLY]
-set RWX_RWX [expr $RWX_R_ONLY + $RWX_W_ONLY + $RWX_X_ONLY]
-set UNKNOWN(0,RWX) $RWX_NO_ACCESS
-
-# WIDTH - access width
-# 8,16,32 [0 means ANY]
-set ACCESS_WIDTH_NONE 0
-set ACCESS_WIDTH_8 $BIT0
-set ACCESS_WIDTH_16 $BIT1
-set ACCESS_WIDTH_32 $BIT2
-set ACCESS_WIDTH_ANY [expr $ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_32]
-set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE
-
-proc iswithin { ADDRESS BASE LEN } {
- return [expr ((($ADDRESS - $BASE) > 0) && (($ADDRESS - $BASE + $LEN) > 0))]
-}
-
-proc address_info { ADDRESS } {
-
- foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } {
- if { info exists $WHERE } {
- set lmt [set N_[set WHERE]]
- for { set region 0 } { $region < $lmt } { incr region } {
- if { iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN) } {
- return "$WHERE $region";
- }
- }
- }
- }
-
- # Return the 'unknown'
- return "UNKNOWN 0"
-}
-
-proc memread32 {ADDR} {
- set foo(0) 0
- if ![ catch { mem2array foo 32 $ADDR 1 } msg ] {
- return $foo(0)
- } else {
- error "memread32: $msg"
- }
-}
-
-proc memread16 {ADDR} {
- set foo(0) 0
- if ![ catch { mem2array foo 16 $ADDR 1 } msg ] {
- return $foo(0)
- } else {
- error "memread16: $msg"
- }
-}
-
-proc memread8 {ADDR} {
- set foo(0) 0
- if ![ catch { mem2array foo 8 $ADDR 1 } msg ] {
- return $foo(0)
- } else {
- error "memread8: $msg"
- }
-}
-
-proc memwrite32 {ADDR DATA} {
- set foo(0) $DATA
- if ![ catch { array2mem foo 32 $ADDR 1 } msg ] {
- return $foo(0)
- } else {
- error "memwrite32: $msg"
- }
-}
-
-proc memwrite16 {ADDR DATA} {
- set foo(0) $DATA
- if ![ catch { array2mem foo 16 $ADDR 1 } msg ] {
- return $foo(0)
- } else {
- error "memwrite16: $msg"
- }
-}
-
-proc memwrite8 {ADDR DATA} {
- set foo(0) $DATA
- if ![ catch { array2mem foo 8 $ADDR 1 } msg ] {
- return $foo(0)
- } else {
- error "memwrite8: $msg"
- }
-}
-
-proc memread32_phys {ADDR} {
- set foo(0) 0
- if ![ catch { mem2array foo 32 $ADDR 1 phys } msg ] {
- return $foo(0)
- } else {
- error "memread32: $msg"
- }
-}
-
-proc memread16_phys {ADDR} {
- set foo(0) 0
- if ![ catch { mem2array foo 16 $ADDR 1 phys } msg ] {
- return $foo(0)
- } else {
- error "memread16: $msg"
- }
-}
-
-proc memread8_phys {ADDR} {
- set foo(0) 0
- if ![ catch { mem2array foo 8 $ADDR 1 phys } msg ] {
- return $foo(0)
- } else {
- error "memread8: $msg"
- }
-}
-
-proc memwrite32_phys {ADDR DATA} {
- set foo(0) $DATA
- if ![ catch { array2mem foo 32 $ADDR 1 phys } msg ] {
- return $foo(0)
- } else {
- error "memwrite32: $msg"
- }
-}
-
-proc memwrite16_phys {ADDR DATA} {
- set foo(0) $DATA
- if ![ catch { array2mem foo 16 $ADDR 1 phys } msg ] {
- return $foo(0)
- } else {
- error "memwrite16: $msg"
- }
-}
-
-proc memwrite8_phys {ADDR DATA} {
- set foo(0) $DATA
- if ![ catch { array2mem foo 8 $ADDR 1 phys } msg ] {
- return $foo(0)
- } else {
- error "memwrite8: $msg"
- }
-}
diff --git a/openocd-0.10.0/scripts/mmr_helpers.tcl b/openocd-0.10.0/scripts/mmr_helpers.tcl
deleted file mode 100644
index ce116e4598fb5cc1c33b5552849faa6ca75c0cf9..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/mmr_helpers.tcl
+++ /dev/null
@@ -1,72 +0,0 @@
-
-proc proc_exists { NAME } {
- set n [info commands $NAME]
- set l [string length $n]
- return [expr $l != 0]
-}
-
-# Give: REGISTER name - must be a global variable.
-proc show_mmr32_reg { NAME } {
-
- global $NAME
- # we want $($NAME)
- set a [set [set NAME]]
-
- if ![catch { set v [memread32 $a] } msg ] {
- echo [format "%15s: (0x%08x): 0x%08x" $NAME $a $v]
-
- # Was a helper defined?
- set fn show_${NAME}_helper
- if [ proc_exists $fn ] {
- # Then call it
- $fn $NAME $a $v
- }
- return $v;
- } else {
- error [format "%s (%s)" $msg $NAME ]
- }
-}
-
-
-# Give: NAMES - an array of names accessable
-# in the callers symbol-scope.
-# VAL - the bits to display.
-
-proc show_mmr32_bits { NAMES VAL } {
-
- upvar $NAMES MYNAMES
-
- set w 5
- foreach {IDX N} $MYNAMES {
- set l [string length $N]
- if { $l > $w } { set w $l }
- }
-
- for { set x 24 } { $x >= 0 } { incr x -8 } {
- echo -n " "
- for { set y 7 } { $y >= 0 } { incr y -1 } {
- set s $MYNAMES([expr $x + $y])
- echo -n [format "%2d: %-*s | " [expr $x + $y] $w $s ]
- }
- echo ""
-
- echo -n " "
- for { set y 7 } { $y >= 0 } { incr y -1 } {
- echo -n [format " %d%*s | " [expr !!($VAL & (1 << ($x + $y)))] [expr $w -1] ""]
- }
- echo ""
- }
-}
-
-
-proc show_mmr_bitfield { MSB LSB VAL FIELDNAME FIELDVALUES } {
- set width [expr (($MSB - $LSB + 1) + 7) / 4]
- set nval [show_normalize_bitfield $VAL $MSB $LSB ]
- set name0 [lindex $FIELDVALUES 0 ]
- if [ string compare $name0 _NUMBER_ ] {
- set sval [lindex $FIELDVALUES $nval]
- } else {
- set sval ""
- }
- echo [format "%-15s: %d (0x%0*x) %s" $FIELDNAME $nval $width $nval $sval ]
-}
diff --git "a/openocd-0.10.0/scripts/target/1986\320\262\320\2651\321\202.cfg" "b/openocd-0.10.0/scripts/target/1986\320\262\320\2651\321\202.cfg"
deleted file mode 100644
index 7b0c35f08f38d558ff185f0ec7f43a127e169b07..0000000000000000000000000000000000000000
--- "a/openocd-0.10.0/scripts/target/1986\320\262\320\2651\321\202.cfg"
+++ /dev/null
@@ -1,63 +0,0 @@
-# 1986ВЕ1Т
-# http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=236&cntnt01returnid=68
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME 1986ве1т
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x4000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- set _CPUTAPID 0x4ba00477
- } {
- # SWD IDCODE
- set _CPUTAPID 0x2ba01477
- }
-}
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# use AHB-Lite SRAM for work area
-$_TARGETNAME configure -work-area-phys 0x20100000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# can't handle overlapping memory regions
-if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
- flash bank ${_CHIPNAME}_info.flash mdr 0x00000000 0x01000 0 0 $_TARGETNAME 1 1 4
-} else {
- flash bank $_CHIPNAME.flash mdr 0x00000000 0x20000 0 0 $_TARGETNAME 0 32 4
-}
-
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/adsp-sc58x.cfg b/openocd-0.10.0/scripts/target/adsp-sc58x.cfg
deleted file mode 100644
index 369137ed94574a472c2ea37ea88bac088eb181ab..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/adsp-sc58x.cfg
+++ /dev/null
@@ -1,45 +0,0 @@
-# Analog Devices ADSP-SC58x (ARM Cortex-A5 plus one or two SHARC+ DSPs)
-
-# evaluation boards by Analog Devices (and designs derived from them) use a non-standard 10-pin 0.05" ARM Cortex Debug Connector
-# pin 9 (GND or GNDDetect) has been usurped with JTAG /TRST
-# as a result, a standards-compliant debug pod will only force the processor's debug interface into reset, preventing usage
-# so, a connector adapter must be employed on these boards to isolate or otherwise prevent /TRST from being asserted
-
-transport select swd
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME ADSP-SC58x
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x3BA02477
-}
-
-swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -event examine-end {
- global _TARGETNAME
- sc58x_enabledebug $_TARGETNAME
-}
-
-proc sc58x_enabledebug {target} {
- # Enable debugging functionality by setting relevant bits in the TAPC_DBGCTL register
- # the "phys" option is critical; the OpenOCD Cortex-A target code prevents normal mww when the target is not halted
- # however, it is not possible to halt the target unless these register bits have been set
- $target mww phys 0x31131000 0xFFFF
-}
-
diff --git a/openocd-0.10.0/scripts/target/aduc702x.cfg b/openocd-0.10.0/scripts/target/aduc702x.cfg
deleted file mode 100644
index fca0a7f969fb9ddc78d9703d8cd4c2a4764bb0d2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/aduc702x.cfg
+++ /dev/null
@@ -1,53 +0,0 @@
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME aduc702x
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # This config file was defaulting to big endian..
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x3f0f0f0f
-}
-
-adapter_nsrst_delay 200
-jtag_ntrst_delay 200
-
-## JTAG scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-##
-## Target configuration
-##
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# allocate the entire SRAM as working area
-$_TARGETNAME configure -work-area-phys 0x10000 -work-area-size 0x2000
-
-## flash configuration
-# only target number is needed
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
-
-## If you use the watchdog, the following code makes sure that the board
-## doesn't reboot when halted via JTAG. Yes, on the older generation
-## AdUC702x, timer3 continues running even when the CPU is halted.
-
-proc watchdog_service {} {
- global watchdog_hdl
- mww 0xffff036c 0
-# echo "watchdog!!"
- set watchdog_hdl [after 500 watchdog_service]
-}
-
-$_TARGETNAME configure -event reset-halt-post { watchdog_service }
-$_TARGETNAME configure -event resume-start { global watchdog_hdl; after cancel $watchdog_hdl }
diff --git a/openocd-0.10.0/scripts/target/aducm360.cfg b/openocd-0.10.0/scripts/target/aducm360.cfg
deleted file mode 100644
index 785c18c595e3ec31633d8bcabe8641bfe2e59f87..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/aducm360.cfg
+++ /dev/null
@@ -1,55 +0,0 @@
-#
-# This file was created using as references the stm32f1x.cfg and aduc702x.cfg
-#
-source [find target/swj-dp.tcl]
-
-# Chip name
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME aducm360
-}
-
-# Endianess
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-# Eventually, the whole SRAM of ADuCM360 will be used (8kB)
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x2000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x2ba01477
-}
-
-swd newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# SWD/JTAG speed
-adapter_khz 1000
-
-##
-## Target configuration
-##
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# allocate the working area
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# flash size will be probed
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME aducm360 0x00 0 0 0 $_TARGETNAME
-
-adapter_nsrst_delay 100
-
-cortex_m reset_config sysresetreq
diff --git a/openocd-0.10.0/scripts/target/alphascale_asm9260t.cfg b/openocd-0.10.0/scripts/target/alphascale_asm9260t.cfg
deleted file mode 100644
index 7892ea2655480119ae493b7fbff6b33cc7d3804e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/alphascale_asm9260t.cfg
+++ /dev/null
@@ -1,25 +0,0 @@
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $_CHIPNAME
-} else {
- set _CHIPNAME asm9260t
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x079264F3
-}
-
-# And srst_pulls_trst by chip design.
-reset_config srst_pulls_trst
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/altera_fpgasoc.cfg b/openocd-0.10.0/scripts/target/altera_fpgasoc.cfg
deleted file mode 100644
index 25fe1f49329c4bd0376d62bd6e38ad8b480b8ed1..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/altera_fpgasoc.cfg
+++ /dev/null
@@ -1,64 +0,0 @@
-#
-# Altera cyclone V SoC family, 5Cxxx
-#
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME fpgasoc
-}
-
-# CoreSight Debug Access Port
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x4ba00477
-}
-
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
- -expected-id $_DAP_TAPID
-
-# Subsidiary TAP: fpga
-if { [info exists FPGA_TAPID] } {
- set _FPGA_TAPID $FPGA_TAPID
-} else {
- set _FPGA_TAPID 0x02d020dd
-}
-jtag newtap $_CHIPNAME.fpga tap -irlen 10 -ircapture 0x01 -irmask 0x3 -expected-id $_FPGA_TAPID
-
-
-#
-# Cortex-A9 target
-#
-
-# GDB target: Cortex-A9, using DAP, configuring only one core
-# Base addresses of cores:
-# core 0 - 0x80110000
-# core 1 - 0x80112000
-
-# Slow speed to be sure it will work
-adapter_khz 1000
-
-set _TARGETNAME1 $_CHIPNAME.cpu.0
-set _TARGETNAME2 $_CHIPNAME.cpu.1
-
-# A9 core 0
-target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \
- -coreid 0 -dbgbase 0x80110000
-
-$_TARGETNAME1 configure -event reset-start { adapter_khz 1000 }
-$_TARGETNAME1 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME1"
-$_TARGETNAME1 configure -event gdb-attach { halt }
-
-
-# A9 core 1
-#target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \
-# -coreid 1 -dbgbase 0x80112000
-
-#$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }
-#$_TARGETNAME2 configure -event reset-assert-post "cycv_dbginit $_TARGETNAME2"
-#$_TARGETNAME2 configure -event gdb-attach { halt }
-
-proc cycv_dbginit {target} {
- # General Cortex-A8/A9 debug initialisation
- cortex_a dbginit
-}
diff --git a/openocd-0.10.0/scripts/target/am335x.cfg b/openocd-0.10.0/scripts/target/am335x.cfg
deleted file mode 100644
index 3ca196b11977a98e52deeb91db2c016afa955213..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/am335x.cfg
+++ /dev/null
@@ -1,110 +0,0 @@
-source [find target/icepick.cfg]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME am335x
-}
-
-# set the taps to be enabled by default. this can be overridden
-# by setting DEFAULT_TAPS in a separate configuration file
-# or directly on the command line.
-if { [info exists DEFAULT_TAPS] } {
- set _DEFAULT_TAPS "$DEFAULT_TAPS"
-} else {
- set _DEFAULT_TAPS "$_CHIPNAME.dap"
-}
-
-#
-# Main DAP
-#
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x4b6b902f
-}
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0"
-
-#
-# M3 DAP
-#
-if { [info exists M3_DAP_TAPID] } {
- set _M3_DAP_TAPID $M3_DAP_TAPID
-} else {
- set _M3_DAP_TAPID 0x4b6b902f
-}
-jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0"
-
-#
-# ICEpick-D (JTAG route controller)
-#
-if { [info exists JRC_TAPID] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x0b94402f
-}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
-jtag configure $_CHIPNAME.jrc -event setup {
- global _DEFAULT_TAPS
- enable_default_taps $_DEFAULT_TAPS
-}
-# some TCK tycles are required to activate the DEBUG power domain
-jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
-
-#
-# helper function that enables all taps passed as argument
-#
-proc enable_default_taps { taps } {
- foreach tap $taps {
- jtag tapenable $tap
- }
-}
-
-#
-# Cortex-M3 target
-#
-set _TARGETNAME_2 $_CHIPNAME.m3
-target create $_TARGETNAME_2 cortex_m -chain-position $_CHIPNAME.m3_dap
-
-#
-# Cortex-A8 target
-#
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
-
-# SRAM: 64K at 0x4030.0000; use the first 16K
-$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
-
-
-# when putting the target into 'reset halt', we need to disable the watchdog as
-# it would otherwise trigger while we're in JTAG
-# FIXME: unify with target/am437x.cfg
-source [find mem_helper.tcl]
-set WDT1_BASE_ADDR 0x44e35000
-set WDT1_W_PEND_WSPR [expr $WDT1_BASE_ADDR + 0x0034]
-set WDT1_WSPR [expr $WDT1_BASE_ADDR + 0x0048]
-proc disable_watchdog { } {
- global WDT1_WSPR
- global WDT1_W_PEND_WSPR
- global _TARGETNAME
-
- set curstate [$_TARGETNAME curstate]
-
- if { [string compare $curstate halted] == 0 } {
- set WDT_DISABLE_SEQ1 0xaaaa
- set WDT_DISABLE_SEQ2 0x5555
-
- mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1
-
- # Empty body to make sure this executes as fast as possible.
- # We don't want any delays here otherwise romcode might start
- # executing and end up changing state of certain IPs.
- while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
-
- mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
- while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
- }
-}
-$_TARGETNAME configure -event reset-end { disable_watchdog }
diff --git a/openocd-0.10.0/scripts/target/am437x.cfg b/openocd-0.10.0/scripts/target/am437x.cfg
deleted file mode 100644
index fe0ffff292a46d8ce65e2d5ff8642476a93ca5f1..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/am437x.cfg
+++ /dev/null
@@ -1,999 +0,0 @@
-source [find target/icepick.cfg]
-source [find mem_helper.tcl]
-
-###############################################################################
-## AM437x Registers ##
-###############################################################################
-set PRCM_BASE_ADDR 0x44df0000
-set REVISION_PRM [expr $PRCM_BASE_ADDR + 0x0000]
-set PRM_IRQSTATUS_MPU [expr $PRCM_BASE_ADDR + 0x0004]
-set PRM_IRQENABLE_MPU [expr $PRCM_BASE_ADDR + 0x0008]
-set PRM_IRQSTATUS_M3 [expr $PRCM_BASE_ADDR + 0x000c]
-set PRM_IRQENABLE_M3 [expr $PRCM_BASE_ADDR + 0x0010]
-set PM_MPU_PWRSTCTRL [expr $PRCM_BASE_ADDR + 0x0300]
-set PM_MPU_PWRSTST [expr $PRCM_BASE_ADDR + 0x0304]
-set RM_MPU_RSTST [expr $PRCM_BASE_ADDR + 0x0314]
-set RM_MPU_CONTEXT [expr $PRCM_BASE_ADDR + 0x0324]
-set PM_GFX_PWRSTCTRL [expr $PRCM_BASE_ADDR + 0x0400]
-set PM_GFX_PWRSTST [expr $PRCM_BASE_ADDR + 0x0404]
-set RM_GFX_RSTCTRL [expr $PRCM_BASE_ADDR + 0x0410]
-set RM_GFX_RSTST [expr $PRCM_BASE_ADDR + 0x0414]
-set RM_GFX_CONTEXT [expr $PRCM_BASE_ADDR + 0x0424]
-set RM_RTC_CONTEXT [expr $PRCM_BASE_ADDR + 0x0524]
-set RM_WKUP_RSTCTRL [expr $PRCM_BASE_ADDR + 0x2010]
-set RM_WKUP_RSTST [expr $PRCM_BASE_ADDR + 0x2014]
-set CM_L3_AON_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2800]
-set CM_WKUP_DEBUGSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2820]
-set CM_L3S_TSC_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2900]
-set CM_WKUP_ADC_TSC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2920]
-set CM_L4_WKUP_AON_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2a00]
-set CM_WKUP_L4WKUP_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a20]
-set CM_WKUP_WKUP_M3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a28]
-set CM_WKUP_SYNCTIMER_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a30]
-set CM_WKUP_CLKDIV32K_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a38]
-set CM_WKUP_USBPHY0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a40]
-set CM_WKUP_USBPHY1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2a48]
-set CM_WKUP_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x2b00]
-set CM_WKUP_TIMER0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b20]
-set CM_WKUP_TIMER1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b28]
-set CM_WKUP_WDT0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b30]
-set CM_WKUP_WDT1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b38]
-set CM_WKUP_I2C0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b40]
-set CM_WKUP_UART0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b48]
-set CM_WKUP_SMARTREFLEX0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b50]
-set CM_WKUP_SMARTREFLEX1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b58]
-set CM_WKUP_CONTROL_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b60]
-set CM_WKUP_GPIO0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x2b68]
-set CM_CLKMODE_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d20]
-set CM_IDLEST_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d24]
-set CM_CLKSEL_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d2c]
-set CM_DIV_M4_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d38]
-set CM_DIV_M5_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d3c]
-set CM_DIV_M6_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d40]
-set CM_SSC_DELTAMSTEP_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d48]
-set CM_SSC_MODFREQDIV_DPLL_CORE [expr $PRCM_BASE_ADDR + 0x2d4c]
-set CM_CLKMODE_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d60]
-set CM_IDLEST_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d64]
-set CM_CLKSEL_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d6c]
-set CM_DIV_M2_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d70]
-set CM_SSC_DELTAMSTEP_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d88]
-set CM_SSC_MODFREQDIV_DPLL_MPU [expr $PRCM_BASE_ADDR + 0x2d8c]
-set CM_CLKMODE_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2da0]
-set CM_IDLEST_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2da4]
-set CM_CLKSEL_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dac]
-set CM_DIV_M2_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2db0]
-set CM_DIV_M4_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2db8]
-set CM_SSC_DELTAMSTEP_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dc8]
-set CM_SSC_MODFREQDIV_DPLL_DDR [expr $PRCM_BASE_ADDR + 0x2dcc]
-set CM_CLKMODE_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2de0]
-set CM_IDLEST_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2de4]
-set CM_CLKSEL_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2dec]
-set CM_DIV_M2_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2df0]
-set CM_CLKSEL2_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e04]
-set CM_SSC_DELTAMSTEP_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e08]
-set CM_SSC_MODFREQDIV_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e0c]
-set CM_CLKDCOLDO_DPLL_PER [expr $PRCM_BASE_ADDR + 0x2e14]
-set CM_CLKMODE_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e20]
-set CM_IDLEST_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e24]
-set CM_CLKSEL_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e2c]
-set CM_DIV_M2_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e30]
-set CM_SSC_DELTAMSTEP_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e48]
-set CM_SSC_MODFREQDIV_DPLL_DISP [expr $PRCM_BASE_ADDR + 0x2e4c]
-set CM_CLKMODE_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e60]
-set CM_IDLEST_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e64]
-set CM_CLKSEL_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e6c]
-set CM_DIV_M2_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e70]
-set CM_CLKSEL2_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e84]
-set CM_SSC_DELTAMSTEP_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e88]
-set CM_SSC_MODFREQDIV_DPLL_EXTDEV [expr $PRCM_BASE_ADDR + 0x2e8c]
-set CM_SHADOW_FREQ_CONFIG1 [expr $PRCM_BASE_ADDR + 0x2fa0]
-set CM_SHADOW_FREQ_CONFIG2 [expr $PRCM_BASE_ADDR + 0x2fa4]
-set CM_CLKOUT1_CTRL [expr $PRCM_BASE_ADDR + 0x4100]
-set CM_DLL_CTRL [expr $PRCM_BASE_ADDR + 0x4104]
-set CM_CLKOUT2_CTRL [expr $PRCM_BASE_ADDR + 0x4108]
-set CLKSEL_TIMER1MS_CLK [expr $PRCM_BASE_ADDR + 0x4200]
-set CLKSEL_TIMER2_CLK [expr $PRCM_BASE_ADDR + 0x4204]
-set CLKSEL_TIMER3_CLK [expr $PRCM_BASE_ADDR + 0x4208]
-set CLKSEL_TIMER4_CLK [expr $PRCM_BASE_ADDR + 0x420c]
-set CLKSEL_TIMER5_CLK [expr $PRCM_BASE_ADDR + 0x4210]
-set CLKSEL_TIMER6_CLK [expr $PRCM_BASE_ADDR + 0x4214]
-set CLKSEL_TIMER7_CLK [expr $PRCM_BASE_ADDR + 0x4218]
-set CLKSEL_TIMER8_CLK [expr $PRCM_BASE_ADDR + 0x421c]
-set CLKSEL_TIMER9_CLK [expr $PRCM_BASE_ADDR + 0x4220]
-set CLKSEL_TIMER10_CLK [expr $PRCM_BASE_ADDR + 0x4224]
-set CLKSEL_TIMER11_CLK [expr $PRCM_BASE_ADDR + 0x4228]
-set CLKSEL_WDT1_CLK [expr $PRCM_BASE_ADDR + 0x422c]
-set CLKSEL_SYNCTIMER_CLK [expr $PRCM_BASE_ADDR + 0x4230]
-set CLKSEL_MAC_CLK [expr $PRCM_BASE_ADDR + 0x4234]
-set CLKSEL_CPTS_RFT_CLK [expr $PRCM_BASE_ADDR + 0x4238]
-set CLKSEL_GFX_FCLK [expr $PRCM_BASE_ADDR + 0x423c]
-set CLKSEL_GPIO0_DBCLK [expr $PRCM_BASE_ADDR + 0x4240]
-set CLKSEL_LCDC_PIXEL_CLK [expr $PRCM_BASE_ADDR + 0x4244]
-set CLKSEL_ICSS_OCP_CLK [expr $PRCM_BASE_ADDR + 0x4248]
-set CLKSEL_DLL_AGING_CLK [expr $PRCM_BASE_ADDR + 0x4250]
-set CLKSEL_USBPHY32KHZ_GCLK [expr $PRCM_BASE_ADDR + 0x4260]
-set CM_MPU_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8300]
-set CM_MPU_MPU_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8320]
-set CM_GFX_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8400]
-set CM_GFX_GFX_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8420]
-set CM_RTC_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8500]
-set CM_RTC_RTC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8520]
-set CM_PER_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8800]
-set CM_PER_L3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8820]
-set CM_PER_AES0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8828]
-set CM_PER_DES_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8830]
-set CM_PER_CRYPTODMA_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8838]
-set CM_PER_L3_INSTR_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8840]
-set CM_PER_MSTR_EXPS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8848]
-set CM_PER_OCMCRAM_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8850]
-set CM_PER_SHA0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8858]
-set CM_PER_SLV_EXPS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8860]
-set CM_PER_VPFE0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8868]
-set CM_PER_VPFE1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8870]
-set CM_PER_TPCC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8878]
-set CM_PER_TPTC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8880]
-set CM_PER_TPTC1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8888]
-set CM_PER_TPTC2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8890]
-set CM_PER_DLL_AGING_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8898]
-set CM_PER_L4HS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x88a0]
-set CM_PER_L4FW_CLKCTRL [expr $PRCM_BASE_ADDR + 0x88a8]
-set CM_PER_L3S_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8a00]
-set CM_PER_GPMC_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a20]
-set CM_PER_IEEE5000_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a28]
-set CM_PER_MCASP0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a38]
-set CM_PER_MCASP1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a40]
-set CM_PER_MMC2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a48]
-set CM_PER_QSPI_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a58]
-set CM_PER_USB_OTG_SS0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a60]
-set CM_PER_USB_OTG_SS1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8a68]
-set CM_PER_ICSS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8b00]
-set CM_PER_ICSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8b20]
-set CM_PER_L4LS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8c00]
-set CM_PER_L4LS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c20]
-set CM_PER_DCAN0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c28]
-set CM_PER_DCAN1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c30]
-set CM_PER_EPWMSS0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c38]
-set CM_PER_EPWMSS1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c40]
-set CM_PER_EPWMSS2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c48]
-set CM_PER_EPWMSS3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c50]
-set CM_PER_EPWMSS4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c58]
-set CM_PER_EPWMSS5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c60]
-set CM_PER_ELM_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c68]
-set CM_PER_GPIO1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c78]
-set CM_PER_GPIO2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c80]
-set CM_PER_GPIO3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c88]
-set CM_PER_GPIO4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c90]
-set CM_PER_GPIO5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8c98]
-set CM_PER_HDQ1W_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ca0]
-set CM_PER_I2C1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ca8]
-set CM_PER_I2C2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cb0]
-set CM_PER_MAILBOX0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cb8]
-set CM_PER_MMC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cc0]
-set CM_PER_MMC1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cc8]
-set CM_PER_PKA_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cd0]
-set CM_PER_RNG_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ce0]
-set CM_PER_SPARE0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8ce8]
-set CM_PER_SPARE1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8cf0]
-set CM_PER_SPI0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d00]
-set CM_PER_SPI1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d08]
-set CM_PER_SPI2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d10]
-set CM_PER_SPI3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d18]
-set CM_PER_SPI4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d20]
-set CM_PER_SPINLOCK_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d28]
-set CM_PER_TIMER2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d30]
-set CM_PER_TIMER3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d38]
-set CM_PER_TIMER4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d40]
-set CM_PER_TIMER5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d48]
-set CM_PER_TIMER6_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d50]
-set CM_PER_TIMER7_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d58]
-set CM_PER_TIMER8_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d60]
-set CM_PER_TIMER9_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d68]
-set CM_PER_TIMER10_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d70]
-set CM_PER_TIMER11_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d78]
-set CM_PER_UART1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d80]
-set CM_PER_UART2_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d88]
-set CM_PER_UART3_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d90]
-set CM_PER_UART4_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8d98]
-set CM_PER_UART5_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8da0]
-set CM_PER_USBPHYOCP2SCP0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8db8]
-set CM_PER_USBPHYOCP2SCP1_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8dc0]
-set CM_PER_EMIF_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x8f00]
-set CM_PER_EMIF_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f20]
-set CM_PER_DLL_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f28]
-set CM_PER_EMIF_FW_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f30]
-set CM_PER_OTFA_EMIF_CLKCTRL [expr $PRCM_BASE_ADDR + 0x8f38]
-set CM_PER_DSS_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9200]
-set CM_PER_DSS_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9220]
-set CM_PER_CPSW_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9300]
-set CM_PER_CPGMAC0_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9320]
-set CM_PER_OCPWP_L3_CLKSTCTRL [expr $PRCM_BASE_ADDR + 0x9400]
-set CM_PER_OCPWP_CLKCTRL [expr $PRCM_BASE_ADDR + 0x9420]
-
-set CONTROL_BASE_ADDR 0x44e10000
-set CONTROL_STATUS [expr $CONTROL_BASE_ADDR + 0x0040]
-set DEVICE_ID [expr $CONTROL_BASE_ADDR + 0x0600]
-set DEV_FEATURE [expr $CONTROL_BASE_ADDR + 0x0604]
-set DEV_ATTRIBUTE [expr $CONTROL_BASE_ADDR + 0x0610]
-set MAC_ID0_LO [expr $CONTROL_BASE_ADDR + 0x0630]
-set MAC_ID0_HI [expr $CONTROL_BASE_ADDR + 0x0634]
-set MAC_ID1_LO [expr $CONTROL_BASE_ADDR + 0x0638]
-set MAC_ID1_HI [expr $CONTROL_BASE_ADDR + 0x063c]
-set USB_VID_PID [expr $CONTROL_BASE_ADDR + 0x07f4]
-set CONTROL_CONF_ECAP0_IN_PWM0_OUT [expr $CONTROL_BASE_ADDR + 0x0964]
-set CONTROL_CONF_SPI4_CS0 [expr $CONTROL_BASE_ADDR + 0x0a5c]
-set CONTROL_CONF_SPI2_SCLK [expr $CONTROL_BASE_ADDR + 0x0a60]
-set CONTROL_CONF_SPI2_D0 [expr $CONTROL_BASE_ADDR + 0x0a64]
-set CONTROL_CONF_XDMA_EVENT_INTR0 [expr $CONTROL_BASE_ADDR + 0x0a70]
-set CONTROL_CONF_XDMA_EVENT_INTR1 [expr $CONTROL_BASE_ADDR + 0x0a74]
-set CONTROL_CONF_GPMC_A0 [expr $CONTROL_BASE_ADDR + 0x0840]
-set DDR_IO_CTRL [expr $CONTROL_BASE_ADDR + 0x0e04]
-set VTP_CTRL_REG [expr $CONTROL_BASE_ADDR + 0x0e0c]
-set VREF_CTRL [expr $CONTROL_BASE_ADDR + 0x0e14]
-set DDR_CKE_CTRL [expr $CONTROL_BASE_ADDR + 0x131c]
-set DDR_ADDRCTRL_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1404]
-set DDR_ADDRCTRL_WD0_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1408]
-set DDR_ADDRCTRL_WD1_IOCTRL [expr $CONTROL_BASE_ADDR + 0x140c]
-set DDR_DATA0_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1440]
-set DDR_DATA1_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1444]
-set DDR_DATA2_IOCTRL [expr $CONTROL_BASE_ADDR + 0x1448]
-set DDR_DATA3_IOCTRL [expr $CONTROL_BASE_ADDR + 0x144c]
-set EMIF_SDRAM_CONFIG_EXT [expr $CONTROL_BASE_ADDR + 0x1460]
-set EMIF_SDRAM_STATUS_EXT [expr $CONTROL_BASE_ADDR + 0x1464]
-
-set GPIO0_BASE_ADDR 0x44e07000
-set GPIO0_SYSCONFIG [expr $GPIO0_BASE_ADDR + 0x0010]
-set GPIO0_SYSSTATUS [expr $GPIO0_BASE_ADDR + 0x0114]
-set GPIO0_CTRL [expr $GPIO0_BASE_ADDR + 0x0130]
-set GPIO0_OE [expr $GPIO0_BASE_ADDR + 0x0134]
-set GPIO0_CLEARDATAOUT [expr $GPIO0_BASE_ADDR + 0x0190]
-set GPIO0_SETDATAOUT [expr $GPIO0_BASE_ADDR + 0x0194]
-
-set GPIO5_BASE_ADDR 0x48322000
-set GPIO5_SYSCONFIG [expr $GPIO5_BASE_ADDR + 0x0010]
-set GPIO5_SYSSTATUS [expr $GPIO5_BASE_ADDR + 0x0114]
-set GPIO5_CTRL [expr $GPIO5_BASE_ADDR + 0x0130]
-set GPIO5_OE [expr $GPIO5_BASE_ADDR + 0x0134]
-set GPIO5_CLEARDATAOUT [expr $GPIO5_BASE_ADDR + 0x0190]
-set GPIO5_SETDATAOUT [expr $GPIO5_BASE_ADDR + 0x0194]
-
-set GPIO1_BASE_ADDR 0x4804c000
-set GPIO1_SYSCONFIG [expr $GPIO1_BASE_ADDR + 0x0010]
-set GPIO1_SYSSTATUS [expr $GPIO1_BASE_ADDR + 0x0114]
-set GPIO1_CTRL [expr $GPIO1_BASE_ADDR + 0x0130]
-set GPIO1_OE [expr $GPIO1_BASE_ADDR + 0x0134]
-set GPIO1_CLEARDATAOUT [expr $GPIO1_BASE_ADDR + 0x0190]
-set GPIO1_SETDATAOUT [expr $GPIO1_BASE_ADDR + 0x0194]
-
-set EMIF_BASE_ADDR 0x4c000000
-set EMIF_STATUS [expr $EMIF_BASE_ADDR + 0x0004]
-set EMIF_SDRAM_CONFIG [expr $EMIF_BASE_ADDR + 0x0008]
-set EMIF_SDRAM_CONFIG_2 [expr $EMIF_BASE_ADDR + 0x000c]
-set EMIF_SDRAM_REF_CTRL [expr $EMIF_BASE_ADDR + 0x0010]
-set EMIF_SDRAM_REF_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x0014]
-set EMIF_SDRAM_TIM_1 [expr $EMIF_BASE_ADDR + 0x0018]
-set EMIF_SDRAM_TIM_1_SHDW [expr $EMIF_BASE_ADDR + 0x001c]
-set EMIF_SDRAM_TIM_2 [expr $EMIF_BASE_ADDR + 0x0020]
-set EMIF_SDRAM_TIM_2_SHDW [expr $EMIF_BASE_ADDR + 0x0024]
-set EMIF_SDRAM_TIM_3 [expr $EMIF_BASE_ADDR + 0x0028]
-set EMIF_SDRAM_TIM_3_SHDW [expr $EMIF_BASE_ADDR + 0x002c]
-set EMIF_LPDDR2_NVM_TIM [expr $EMIF_BASE_ADDR + 0x0030]
-set EMIF_LPDDR2_NVM_TIM_SHDW [expr $EMIF_BASE_ADDR + 0x0034]
-set EMIF_PWR_MGMT_CTRL [expr $EMIF_BASE_ADDR + 0x0038]
-set EMIF_PWR_MGMT_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x003c]
-set EMIF_LPDDR2_MODE_REG_DATA [expr $EMIF_BASE_ADDR + 0x0040]
-set EMIF_LPDDR2_MODE_REG_CFG [expr $EMIF_BASE_ADDR + 0x0050]
-set EMIF_OCP_CONFIG [expr $EMIF_BASE_ADDR + 0x0054]
-set EMIF_OCP_CFG_VAL_1 [expr $EMIF_BASE_ADDR + 0x0058]
-set EMIF_OCP_CFG_VAL_2 [expr $EMIF_BASE_ADDR + 0x005c]
-set EMIF_IODFT_TLGC [expr $EMIF_BASE_ADDR + 0x0060]
-set EMIF_IODFT_CTRL_MISR_RSLT [expr $EMIF_BASE_ADDR + 0x0064]
-set EMIF_IODFT_ADDR_MISR_RSLT [expr $EMIF_BASE_ADDR + 0x0068]
-set EMIF_IODFT_DATA_MISR_RSLT_1 [expr $EMIF_BASE_ADDR + 0x006c]
-set EMIF_IODFT_DATA_MISR_RSLT_2 [expr $EMIF_BASE_ADDR + 0x0070]
-set EMIF_IODFT_DATA_MISR_RSLT_3 [expr $EMIF_BASE_ADDR + 0x0074]
-set EMIF_PERF_CNT_1 [expr $EMIF_BASE_ADDR + 0x0080]
-set EMIF_PERF_CNT_2 [expr $EMIF_BASE_ADDR + 0x0084]
-set EMIF_PERF_CNT_CFG [expr $EMIF_BASE_ADDR + 0x0088]
-set EMIF_PERF_CNT_SEL [expr $EMIF_BASE_ADDR + 0x008c]
-set EMIF_PERF_CNT_TIM [expr $EMIF_BASE_ADDR + 0x0090]
-set EMIF_MISC_REG [expr $EMIF_BASE_ADDR + 0x0094]
-set EMIF_DLL_CALIB_CTRL [expr $EMIF_BASE_ADDR + 0x0098]
-set EMIF_DLL_CALIB_CTRL_SHDW [expr $EMIF_BASE_ADDR + 0x009c]
-set EMIF_IRQ_EOI [expr $EMIF_BASE_ADDR + 0x00a0]
-set EMIF_IRQSTATUS_RAW_SYS [expr $EMIF_BASE_ADDR + 0x00a4]
-set EMIF_IRQSTATUS_SYS [expr $EMIF_BASE_ADDR + 0x00ac]
-set EMIF_IRQENABLE_SET_SYS [expr $EMIF_BASE_ADDR + 0x00b4]
-set EMIF_IRQENABLE_CLR_SYS [expr $EMIF_BASE_ADDR + 0x00bc]
-set EMIF_ZQ_CONFIG [expr $EMIF_BASE_ADDR + 0x00c8]
-set EMIF_TEMP_ALERT_CONFIG [expr $EMIF_BASE_ADDR + 0x00cc]
-set EMIF_OCP_ERR_LOG [expr $EMIF_BASE_ADDR + 0x00d0]
-set EMIF_RDWR_LVL_RMP_WIN [expr $EMIF_BASE_ADDR + 0x00d4]
-set EMIF_RDWR_LVL_RMP_CTRL [expr $EMIF_BASE_ADDR + 0x00d8]
-set EMIF_RDWR_LVL_CTRL [expr $EMIF_BASE_ADDR + 0x00dc]
-set EMIF_DDR_PHY_CTRL_1 [expr $EMIF_BASE_ADDR + 0x00e4]
-set EMIF_DDR_PHY_CTRL_1_SHDW [expr $EMIF_BASE_ADDR + 0x00e8]
-set EMIF_DDR_PHY_CTRL_2 [expr $EMIF_BASE_ADDR + 0x00ec]
-set EMIF_PRI_COS_MAP [expr $EMIF_BASE_ADDR + 0x0100]
-set EMIF_CONNID_COS_1_MAP [expr $EMIF_BASE_ADDR + 0x0104]
-set EMIF_CONNID_COS_2_MAP [expr $EMIF_BASE_ADDR + 0x0108]
-set ECC_CTRL [expr $EMIF_BASE_ADDR + 0x0110]
-set ECC_ADDR_RNG_1 [expr $EMIF_BASE_ADDR + 0x0114]
-set ECC_ADDR_RNG_2 [expr $EMIF_BASE_ADDR + 0x0118]
-set EMIF_RD_WR_EXEC_THRSH [expr $EMIF_BASE_ADDR + 0x0120]
-set COS_CONFIG [expr $EMIF_BASE_ADDR + 0x0124]
-
-set PHY_STATUS_1 [expr $EMIF_BASE_ADDR + 0x0144]
-set PHY_STATUS_2 [expr $EMIF_BASE_ADDR + 0x0148]
-set PHY_STATUS_3 [expr $EMIF_BASE_ADDR + 0x014c]
-set PHY_STATUS_4 [expr $EMIF_BASE_ADDR + 0x0150]
-set PHY_STATUS_5 [expr $EMIF_BASE_ADDR + 0x0154]
-set PHY_STATUS_6 [expr $EMIF_BASE_ADDR + 0x0158]
-set PHY_STATUS_7 [expr $EMIF_BASE_ADDR + 0x015c]
-set PHY_STATUS_8 [expr $EMIF_BASE_ADDR + 0x0160]
-set PHY_STATUS_9 [expr $EMIF_BASE_ADDR + 0x0164]
-set PHY_STATUS_10 [expr $EMIF_BASE_ADDR + 0x0168]
-set PHY_STATUS_11 [expr $EMIF_BASE_ADDR + 0x016c]
-set PHY_STATUS_12 [expr $EMIF_BASE_ADDR + 0x0170]
-set PHY_STATUS_13 [expr $EMIF_BASE_ADDR + 0x0174]
-set PHY_STATUS_14 [expr $EMIF_BASE_ADDR + 0x0178]
-set PHY_STATUS_15 [expr $EMIF_BASE_ADDR + 0x017c]
-set PHY_STATUS_16 [expr $EMIF_BASE_ADDR + 0x0180]
-set PHY_STATUS_17 [expr $EMIF_BASE_ADDR + 0x0184]
-set PHY_STATUS_18 [expr $EMIF_BASE_ADDR + 0x0188]
-set PHY_STATUS_19 [expr $EMIF_BASE_ADDR + 0x018c]
-set PHY_STATUS_20 [expr $EMIF_BASE_ADDR + 0x0190]
-set PHY_STATUS_21 [expr $EMIF_BASE_ADDR + 0x0194]
-set PHY_STATUS_22 [expr $EMIF_BASE_ADDR + 0x0198]
-set PHY_STATUS_23 [expr $EMIF_BASE_ADDR + 0x019c]
-set PHY_STATUS_24 [expr $EMIF_BASE_ADDR + 0x01a0]
-set PHY_STATUS_25 [expr $EMIF_BASE_ADDR + 0x01a4]
-set PHY_STATUS_26 [expr $EMIF_BASE_ADDR + 0x01a8]
-set PHY_STATUS_27 [expr $EMIF_BASE_ADDR + 0x01ac]
-set PHY_STATUS_28 [expr $EMIF_BASE_ADDR + 0x01b0]
-
-set EXT_PHY_CTRL_1 [expr $EMIF_BASE_ADDR + 0x0200]
-set EXT_PHY_CTRL_1_SHDW [expr $EMIF_BASE_ADDR + 0x0204]
-set EXT_PHY_CTRL_2 [expr $EMIF_BASE_ADDR + 0x0208]
-set EXT_PHY_CTRL_2_SHDW [expr $EMIF_BASE_ADDR + 0x020c]
-set EXT_PHY_CTRL_3 [expr $EMIF_BASE_ADDR + 0x0210]
-set EXT_PHY_CTRL_3_SHDW [expr $EMIF_BASE_ADDR + 0x0214]
-set EXT_PHY_CTRL_4 [expr $EMIF_BASE_ADDR + 0x0218]
-set EXT_PHY_CTRL_4_SHDW [expr $EMIF_BASE_ADDR + 0x021c]
-set EXT_PHY_CTRL_5 [expr $EMIF_BASE_ADDR + 0x0220]
-set EXT_PHY_CTRL_5_SHDW [expr $EMIF_BASE_ADDR + 0x0224]
-set EXT_PHY_CTRL_6 [expr $EMIF_BASE_ADDR + 0x0228]
-set EXT_PHY_CTRL_6_SHDW [expr $EMIF_BASE_ADDR + 0x022c]
-set EXT_PHY_CTRL_7 [expr $EMIF_BASE_ADDR + 0x0230]
-set EXT_PHY_CTRL_7_SHDW [expr $EMIF_BASE_ADDR + 0x0234]
-set EXT_PHY_CTRL_8 [expr $EMIF_BASE_ADDR + 0x0238]
-set EXT_PHY_CTRL_8_SHDW [expr $EMIF_BASE_ADDR + 0x023c]
-set EXT_PHY_CTRL_9 [expr $EMIF_BASE_ADDR + 0x0240]
-set EXT_PHY_CTRL_9_SHDW [expr $EMIF_BASE_ADDR + 0x0244]
-set EXT_PHY_CTRL_10 [expr $EMIF_BASE_ADDR + 0x0248]
-set EXT_PHY_CTRL_10_SHDW [expr $EMIF_BASE_ADDR + 0x024c]
-set EXT_PHY_CTRL_11 [expr $EMIF_BASE_ADDR + 0x0250]
-set EXT_PHY_CTRL_11_SHDW [expr $EMIF_BASE_ADDR + 0x0254]
-set EXT_PHY_CTRL_12 [expr $EMIF_BASE_ADDR + 0x0258]
-set EXT_PHY_CTRL_12_SHDW [expr $EMIF_BASE_ADDR + 0x025c]
-set EXT_PHY_CTRL_13 [expr $EMIF_BASE_ADDR + 0x0260]
-set EXT_PHY_CTRL_13_SHDW [expr $EMIF_BASE_ADDR + 0x0264]
-set EXT_PHY_CTRL_14 [expr $EMIF_BASE_ADDR + 0x0268]
-set EXT_PHY_CTRL_14_SHDW [expr $EMIF_BASE_ADDR + 0x026c]
-set EXT_PHY_CTRL_15 [expr $EMIF_BASE_ADDR + 0x0270]
-set EXT_PHY_CTRL_15_SHDW [expr $EMIF_BASE_ADDR + 0x0274]
-set EXT_PHY_CTRL_16 [expr $EMIF_BASE_ADDR + 0x0278]
-set EXT_PHY_CTRL_16_SHDW [expr $EMIF_BASE_ADDR + 0x027c]
-set EXT_PHY_CTRL_17 [expr $EMIF_BASE_ADDR + 0x0280]
-set EXT_PHY_CTRL_17_SHDW [expr $EMIF_BASE_ADDR + 0x0284]
-set EXT_PHY_CTRL_18 [expr $EMIF_BASE_ADDR + 0x0288]
-set EXT_PHY_CTRL_18_SHDW [expr $EMIF_BASE_ADDR + 0x028c]
-set EXT_PHY_CTRL_19 [expr $EMIF_BASE_ADDR + 0x0290]
-set EXT_PHY_CTRL_19_SHDW [expr $EMIF_BASE_ADDR + 0x0294]
-set EXT_PHY_CTRL_20 [expr $EMIF_BASE_ADDR + 0x0298]
-set EXT_PHY_CTRL_20_SHDW [expr $EMIF_BASE_ADDR + 0x029c]
-set EXT_PHY_CTRL_21 [expr $EMIF_BASE_ADDR + 0x02a0]
-set EXT_PHY_CTRL_21_SHDW [expr $EMIF_BASE_ADDR + 0x02a4]
-set EXT_PHY_CTRL_22 [expr $EMIF_BASE_ADDR + 0x02a8]
-set EXT_PHY_CTRL_22_SHDW [expr $EMIF_BASE_ADDR + 0x02ac]
-set EXT_PHY_CTRL_23 [expr $EMIF_BASE_ADDR + 0x02b0]
-set EXT_PHY_CTRL_23_SHDW [expr $EMIF_BASE_ADDR + 0x02b4]
-set EXT_PHY_CTRL_24 [expr $EMIF_BASE_ADDR + 0x02b8]
-set EXT_PHY_CTRL_24_SHDW [expr $EMIF_BASE_ADDR + 0x02bc]
-set EXT_PHY_CTRL_25 [expr $EMIF_BASE_ADDR + 0x02c0]
-set EXT_PHY_CTRL_25_SHDW [expr $EMIF_BASE_ADDR + 0x02c4]
-set EXT_PHY_CTRL_26 [expr $EMIF_BASE_ADDR + 0x02c8]
-set EXT_PHY_CTRL_26_SHDW [expr $EMIF_BASE_ADDR + 0x02cc]
-set EXT_PHY_CTRL_27 [expr $EMIF_BASE_ADDR + 0x02d0]
-set EXT_PHY_CTRL_27_SHDW [expr $EMIF_BASE_ADDR + 0x02d4]
-set EXT_PHY_CTRL_28 [expr $EMIF_BASE_ADDR + 0x02d8]
-set EXT_PHY_CTRL_28_SHDW [expr $EMIF_BASE_ADDR + 0x02dc]
-set EXT_PHY_CTRL_29 [expr $EMIF_BASE_ADDR + 0x02e0]
-set EXT_PHY_CTRL_29_SHDW [expr $EMIF_BASE_ADDR + 0x02e4]
-set EXT_PHY_CTRL_30 [expr $EMIF_BASE_ADDR + 0x02e8]
-set EXT_PHY_CTRL_30_SHDW [expr $EMIF_BASE_ADDR + 0x02ec]
-set EXT_PHY_CTRL_31 [expr $EMIF_BASE_ADDR + 0x02f0]
-set EXT_PHY_CTRL_31_SHDW [expr $EMIF_BASE_ADDR + 0x02f4]
-set EXT_PHY_CTRL_32 [expr $EMIF_BASE_ADDR + 0x02f8]
-set EXT_PHY_CTRL_32_SHDW [expr $EMIF_BASE_ADDR + 0x02fc]
-set EXT_PHY_CTRL_33 [expr $EMIF_BASE_ADDR + 0x0300]
-set EXT_PHY_CTRL_33_SHDW [expr $EMIF_BASE_ADDR + 0x0304]
-set EXT_PHY_CTRL_34 [expr $EMIF_BASE_ADDR + 0x0308]
-set EXT_PHY_CTRL_34_SHDW [expr $EMIF_BASE_ADDR + 0x030c]
-set EXT_PHY_CTRL_35 [expr $EMIF_BASE_ADDR + 0x0310]
-set EXT_PHY_CTRL_35_SHDW [expr $EMIF_BASE_ADDR + 0x0314]
-set EXT_PHY_CTRL_36 [expr $EMIF_BASE_ADDR + 0x0318]
-set EXT_PHY_CTRL_36_SHDW [expr $EMIF_BASE_ADDR + 0x031c]
-
-set WDT1_BASE_ADDR 0x44e35000
-set WDT1_W_PEND_WSPR [expr $WDT1_BASE_ADDR + 0x0034]
-set WDT1_WSPR [expr $WDT1_BASE_ADDR + 0x0048]
-
-set RTC_BASE_ADDR 0x44e3e000
-set RTC_KICK0R [expr $RTC_BASE_ADDR + 0x6c]
-set RTC_KICK1R [expr $RTC_BASE_ADDR + 0x70]
-
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME am437x
-}
-
-set JRC_MODULE icepick_d
-set DEBUGSS_MODULE debugss
-set M3_MODULE m3_wakeupss
-
-set JRC_NAME $_CHIPNAME.$JRC_MODULE
-set DEBUGSS_NAME $_CHIPNAME.$DEBUGSS_MODULE
-set M3_NAME $_CHIPNAME.$M3_MODULE
-set _TARGETNAME $_CHIPNAME.mpuss
-
-#
-# M3 WakeupSS DAP
-#
-if { [info exists M3_DAP_TAPID] } {
- set _M3_DAP_TAPID $M3_DAP_TAPID
-} else {
- set _M3_DAP_TAPID 0x4b6b902f
-}
-jtag newtap $_CHIPNAME $M3_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
-jtag configure $M3_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 11 0"
-
-#
-# DebugSS DAP
-#
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x46b6902f
-}
-jtag newtap $_CHIPNAME $DEBUGSS_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
-jtag configure $DEBUGSS_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 12 0"
-
-#
-# ICEpick-D (JTAG route controller)
-#
-if { [info exists JRC_TAPID] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x0b98c02f
-}
-jtag newtap $_CHIPNAME $JRC_MODULE -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
-jtag configure $JRC_NAME -event setup "jtag tapenable $DEBUGSS_NAME"
- # some TCK tycles are required to activate the DEBUG power domain
-jtag configure $JRC_NAME -event post-reset "runtest 100"
-
-#
-# Cortex-A9 target
-#
-target create $_TARGETNAME cortex_a -chain-position $DEBUGSS_NAME -coreid 0 -dbgbase 0x80000000
-
-
-# SRAM: 256K at 0x4030.0000
-$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x40000
-
-# Disables watchdog timer after reset otherwise board won't stay in
-# halted state.
-proc disable_watchdog { } {
- global WDT1_WSPR
- global WDT1_W_PEND_WSPR
- global _TARGETNAME
-
- set curstate [$_TARGETNAME curstate]
-
- if { [string compare $curstate halted] == 0 } {
- set WDT_DISABLE_SEQ1 0xaaaa
- set WDT_DISABLE_SEQ2 0x5555
-
- mww phys $WDT1_WSPR $WDT_DISABLE_SEQ1
-
- # Empty body to make sure this executes as fast as possible.
- # We don't want any delays here otherwise romcode might start
- # executing and end up changing state of certain IPs.
- while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
-
- mww phys $WDT1_WSPR $WDT_DISABLE_SEQ2
- while { [expr [mrw $WDT1_W_PEND_WSPR] & 0x10] } { }
- }
-}
-
-proc ceil { x y } {
- return [ expr ($x + $y - 1) / $y ]
-}
-
-proc device_type { } {
- global CONTROL_STATUS
-
- set tmp [ mrw $CONTROL_STATUS ]
- set tmp [ expr $tmp & 0x700 ]
- set tmp [ expr $tmp >> 8 ]
-
- return $tmp
-}
-
-proc get_input_clock_frequency { } {
- global CONTROL_STATUS
-
- if { [ device_type ] != 3 } {
- error "Unknown device type\n"
- return -1
- }
-
- set freq [ mrw $CONTROL_STATUS ]
- set freq [ expr $freq & 0x00c00000 ]
- set freq [ expr $freq >> 22 ]
-
- switch $freq {
- 0 {
- set CLKIN 19200000
- }
-
- 1 {
- set CLKIN 24000000
- }
-
- 2 {
- set CLKIN 25000000
- }
-
- 3 {
- set CLKIN 26000000
- }
- }
-
- return $CLKIN
-}
-
-proc mpu_pll_config { CLKIN N M M2 } {
- global CM_CLKMODE_DPLL_MPU
- global CM_CLKSEL_DPLL_MPU
- global CM_DIV_M2_DPLL_MPU
- global CM_IDLEST_DPLL_MPU
-
- set clksel [ mrw $CM_CLKSEL_DPLL_MPU ]
- set div_m2 [ mrw $CM_DIV_M2_DPLL_MPU ]
-
- mww $CM_CLKMODE_DPLL_MPU 0x4
- while { !([ mrw $CM_IDLEST_DPLL_MPU ] & 0x0100) } { }
-
- set clksel [ expr $clksel & (~0x7ffff) ]
- set clksel [ expr $clksel | ($M << 0x8) | $N ]
- mww $CM_CLKSEL_DPLL_MPU $clksel
-
- set div_m2 [ expr $div_m2 & (~0x1f) ]
- set div_m2 [ expr $div_m2 | $M2 ]
- mww $CM_DIV_M2_DPLL_MPU $div_m2
-
- mww $CM_CLKMODE_DPLL_MPU 0x7
- while { [ mrw $CM_IDLEST_DPLL_MPU ] != 1 } { }
-
- echo "MPU DPLL locked"
-}
-
-proc core_pll_config { CLKIN N M M4 M5 M6 } {
- global CM_CLKMODE_DPLL_CORE
- global CM_CLKSEL_DPLL_CORE
- global CM_DIV_M4_DPLL_CORE
- global CM_DIV_M5_DPLL_CORE
- global CM_DIV_M6_DPLL_CORE
- global CM_IDLEST_DPLL_CORE
-
- set clksel [ mrw $CM_CLKSEL_DPLL_CORE ]
-
- mww $CM_CLKMODE_DPLL_CORE 0x4
- while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x0100) } { }
-
- set clksel [ expr $clksel & (~0x7ffff) ]
- set clksel [ expr $clksel | ($M << 0x8) | $N ]
- mww $CM_CLKSEL_DPLL_CORE $clksel
- mww $CM_DIV_M4_DPLL_CORE $M4
- mww $CM_DIV_M5_DPLL_CORE $M5
- mww $CM_DIV_M6_DPLL_CORE $M6
-
- mww $CM_CLKMODE_DPLL_CORE 0x7
- while { !([ mrw $CM_IDLEST_DPLL_CORE ] & 0x01) } { }
-
- echo "CORE DPLL locked"
-}
-
-proc per_pll_config { CLKIN N M M2 } {
- global CM_CLKMODE_DPLL_PER
- global CM_CLKSEL_DPLL_PER
- global CM_DIV_M2_DPLL_PER
- global CM_IDLEST_DPLL_PER
-
- set x [ expr $M * $CLKIN / 1000000 ]
- set y [ expr ($N + 1) * 250 ]
- set sd [ ceil $x $y ]
-
- set clksel [ mrw $CM_CLKSEL_DPLL_PER ]
- set div_m2 [ mrw $CM_DIV_M2_DPLL_PER ]
-
- mww $CM_CLKMODE_DPLL_PER 0x4
- while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x0100) } { }
-
- set clksel [ expr $clksel & (~0xff0fffff) ]
- set clksel [ expr $clksel | ($M << 0x8) | $N ]
- set clksel [ expr $clksel | ($sd << 24) ]
- mww $CM_CLKSEL_DPLL_PER $clksel
-
- set div_m2 [ expr 0xffffff80 | $M2 ]
-
- mww $CM_CLKMODE_DPLL_PER 0x7
- while { !([ mrw $CM_IDLEST_DPLL_PER ] & 0x01) } { }
-
- echo "PER DPLL locked"
-}
-
-proc ddr_pll_config { CLKIN N M M2 M4 } {
- global CM_CLKMODE_DPLL_DDR
- global CM_CLKSEL_DPLL_DDR
- global CM_DIV_M2_DPLL_DDR
- global CM_DIV_M4_DPLL_DDR
- global CM_IDLEST_DPLL_DDR
-
- set clksel [ mrw $CM_CLKSEL_DPLL_DDR ]
- set div_m2 [ mrw $CM_DIV_M2_DPLL_DDR ]
-
- mww $CM_CLKMODE_DPLL_DDR 0x4
- while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x0100) } { }
-
- set clksel [ expr $clksel & (~0x7ffff) ]
- set clksel [ expr $clksel | ($M << 8) | $N ]
- mww $CM_CLKSEL_DPLL_DDR $clksel
-
- set div_m2 [ expr ($div_m2 & 0xffffffe0) | $M2 ]
- mww $CM_DIV_M2_DPLL_DDR $div_m2
- mww $CM_DIV_M4_DPLL_DDR $M4
-
- mww $CM_CLKMODE_DPLL_DDR 0x7
- while { !([ mrw $CM_IDLEST_DPLL_DDR ] & 0x01) } { }
-
- echo "DDR DPLL Locked"
-}
-
-proc config_opp100 { } {
- set CLKIN [ get_input_clock_frequency ]
-
- if { $CLKIN == -1 } {
- return -1
- }
-
- switch $CLKIN {
- 24000000 {
- mpu_pll_config $CLKIN 0 25 1
- core_pll_config $CLKIN 2 125 10 8 4
- per_pll_config $CLKIN 9 400 5
- ddr_pll_config $CLKIN 2 50 1 2
- }
-
- 25000000 {
- mpu_pll_config $CLKIN 0 24 1
- core_pll_config $CLKIN 0 40 10 8 4
- per_pll_config $CLKIN 9 384 5
- ddr_pll_config $CLKIN 0 16 1 2
- }
-
- 26000000 {
- mpu_pll_config $CLKIN 12 300 1
- core_pll_config $CLKIN 12 500 10 8 4
- per_pll_config $CLKIN 12 480 5
- ddr_pll_config $CLKIN 12 200 1 2
- }
-
- 19200000 {
- mpu_pll_config $CLKIN 3 125 1
- core_pll_config $CLKIN 11 625 10 8 4
- per_pll_config $CLKIN 7 400 5
- ddr_pll_config $CLKIN 2 125 1 2
- }
- }
-}
-
-proc emif_prcm_clk_enable { } {
- global CM_PER_EMIF_FW_CLKCTRL
- global CM_PER_EMIF_CLKCTRL
-
- mww $CM_PER_EMIF_FW_CLKCTRL 0x02
- mww $CM_PER_EMIF_CLKCTRL 0x02
-
- while { [ mrw $CM_PER_EMIF_CLKCTRL ] != 0x02 } { }
-}
-
-proc vtp_enable { } {
- global VTP_CTRL_REG
-
- set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x40 ]
- mww $VTP_CTRL_REG $vtp
-
- set vtp [ expr [ mrw $VTP_CTRL_REG ] & ~0x01 ]
- mww $VTP_CTRL_REG $vtp
-
- set vtp [ expr [ mrw $VTP_CTRL_REG ] | 0x01 ]
- mww $VTP_CTRL_REG $vtp
-
-}
-
-proc config_ddr_ioctrl { } {
- global DDR_ADDRCTRL_IOCTRL
- global DDR_ADDRCTRL_WD0_IOCTRL
- global DDR_ADDRCTRL_WD1_IOCTRL
- global DDR_CKE_CTRL
- global DDR_DATA0_IOCTRL
- global DDR_DATA1_IOCTRL
- global DDR_DATA2_IOCTRL
- global DDR_DATA3_IOCTRL
- global DDR_IO_CTRL
-
- mww $DDR_ADDRCTRL_IOCTRL 0x84
- mww $DDR_ADDRCTRL_WD0_IOCTRL 0x00
- mww $DDR_ADDRCTRL_WD1_IOCTRL 0x00
- mww $DDR_DATA0_IOCTRL 0x84
- mww $DDR_DATA1_IOCTRL 0x84
- mww $DDR_DATA2_IOCTRL 0x84
- mww $DDR_DATA3_IOCTRL 0x84
-
- mww $DDR_IO_CTRL 0x00
- mww $DDR_CKE_CTRL 0x03
-}
-
-proc config_ddr_phy { } {
- global EMIF_DDR_PHY_CTRL_1
- global EMIF_DDR_PHY_CTRL_1_SHDW
-
- global EXT_PHY_CTRL_1
- global EXT_PHY_CTRL_1_SHDW
- global EXT_PHY_CTRL_2
- global EXT_PHY_CTRL_2_SHDW
- global EXT_PHY_CTRL_3
- global EXT_PHY_CTRL_3_SHDW
- global EXT_PHY_CTRL_4
- global EXT_PHY_CTRL_4_SHDW
- global EXT_PHY_CTRL_5
- global EXT_PHY_CTRL_5_SHDW
- global EXT_PHY_CTRL_6
- global EXT_PHY_CTRL_6_SHDW
- global EXT_PHY_CTRL_7
- global EXT_PHY_CTRL_7_SHDW
- global EXT_PHY_CTRL_8
- global EXT_PHY_CTRL_8_SHDW
- global EXT_PHY_CTRL_9
- global EXT_PHY_CTRL_9_SHDW
- global EXT_PHY_CTRL_10
- global EXT_PHY_CTRL_10_SHDW
- global EXT_PHY_CTRL_11
- global EXT_PHY_CTRL_11_SHDW
- global EXT_PHY_CTRL_12
- global EXT_PHY_CTRL_12_SHDW
- global EXT_PHY_CTRL_13
- global EXT_PHY_CTRL_13_SHDW
- global EXT_PHY_CTRL_14
- global EXT_PHY_CTRL_14_SHDW
- global EXT_PHY_CTRL_15
- global EXT_PHY_CTRL_15_SHDW
- global EXT_PHY_CTRL_16
- global EXT_PHY_CTRL_16_SHDW
- global EXT_PHY_CTRL_17
- global EXT_PHY_CTRL_17_SHDW
- global EXT_PHY_CTRL_18
- global EXT_PHY_CTRL_18_SHDW
- global EXT_PHY_CTRL_19
- global EXT_PHY_CTRL_19_SHDW
- global EXT_PHY_CTRL_20
- global EXT_PHY_CTRL_20_SHDW
- global EXT_PHY_CTRL_21
- global EXT_PHY_CTRL_21_SHDW
- global EXT_PHY_CTRL_22
- global EXT_PHY_CTRL_22_SHDW
- global EXT_PHY_CTRL_23
- global EXT_PHY_CTRL_23_SHDW
- global EXT_PHY_CTRL_24
- global EXT_PHY_CTRL_24_SHDW
- global EXT_PHY_CTRL_25
- global EXT_PHY_CTRL_25_SHDW
- global EXT_PHY_CTRL_26
- global EXT_PHY_CTRL_26_SHDW
- global EXT_PHY_CTRL_27
- global EXT_PHY_CTRL_27_SHDW
- global EXT_PHY_CTRL_28
- global EXT_PHY_CTRL_28_SHDW
- global EXT_PHY_CTRL_29
- global EXT_PHY_CTRL_29_SHDW
- global EXT_PHY_CTRL_30
- global EXT_PHY_CTRL_30_SHDW
- global EXT_PHY_CTRL_31
- global EXT_PHY_CTRL_31_SHDW
- global EXT_PHY_CTRL_32
- global EXT_PHY_CTRL_32_SHDW
- global EXT_PHY_CTRL_33
- global EXT_PHY_CTRL_33_SHDW
- global EXT_PHY_CTRL_34
- global EXT_PHY_CTRL_34_SHDW
- global EXT_PHY_CTRL_35
- global EXT_PHY_CTRL_35_SHDW
- global EXT_PHY_CTRL_36
- global EXT_PHY_CTRL_36_SHDW
-
- mww $EMIF_DDR_PHY_CTRL_1 0x8009
- mww $EMIF_DDR_PHY_CTRL_1_SHDW 0x8009
-
- set slave_ratio 0x80
- set gatelvl_init_ratio 0x20
- set wr_dqs_slave_delay 0x60
- set rd_dqs_slave_delay 0x60
- set dq_offset 0x40
- set gatelvl_init_mode 0x01
- set wr_data_slave_delay 0x80
- set gatelvl_num_dq0 0x0f
- set wrlvl_num_dq0 0x0f
-
- mww $EXT_PHY_CTRL_1 [ expr ($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio ]
- mww $EXT_PHY_CTRL_1_SHDW [ expr ($slave_ratio << 20) | ($slave_ratio << 10) | $slave_ratio ]
- mww $EXT_PHY_CTRL_26 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
- mww $EXT_PHY_CTRL_26_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
- mww $EXT_PHY_CTRL_27 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
- mww $EXT_PHY_CTRL_27_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
- mww $EXT_PHY_CTRL_28 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
- mww $EXT_PHY_CTRL_28_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
- mww $EXT_PHY_CTRL_29 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
- mww $EXT_PHY_CTRL_29_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
- mww $EXT_PHY_CTRL_30 [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
- mww $EXT_PHY_CTRL_30_SHDW [ expr ($gatelvl_init_ratio << 16) | $gatelvl_init_ratio ]
- mww $EXT_PHY_CTRL_31 0x00
- mww $EXT_PHY_CTRL_31_SHDW 0x00
- mww $EXT_PHY_CTRL_32 0x00
- mww $EXT_PHY_CTRL_32_SHDW 0x00
- mww $EXT_PHY_CTRL_33 0x00
- mww $EXT_PHY_CTRL_33_SHDW 0x00
- mww $EXT_PHY_CTRL_34 0x00
- mww $EXT_PHY_CTRL_34_SHDW 0x00
- mww $EXT_PHY_CTRL_35 0x00
- mww $EXT_PHY_CTRL_35_SHDW 0x00
- mww $EXT_PHY_CTRL_22 0x00
- mww $EXT_PHY_CTRL_22_SHDW 0x00
- mww $EXT_PHY_CTRL_23 [ expr ($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay ]
- mww $EXT_PHY_CTRL_23_SHDW [ expr ($wr_dqs_slave_delay << 16) | $rd_dqs_slave_delay ]
- mww $EXT_PHY_CTRL_24 [ expr ($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay ]
- mww $EXT_PHY_CTRL_24_SHDW [ expr ($dq_offset << 24) | ($gatelvl_init_mode << 16) | $wr_data_slave_delay << 0 ]
- mww $EXT_PHY_CTRL_25 [ expr ($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset ]
- mww $EXT_PHY_CTRL_25_SHDW [ expr ($dq_offset << 21) | ($dq_offset << 14) | ($dq_offset << 7) | $dq_offset ]
- mww $EXT_PHY_CTRL_36 [ expr ($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0 ]
- mww $EXT_PHY_CTRL_36_SHDW [ expr ($wrlvl_num_dq0 << 4) | $gatelvl_num_dq0 ]
-}
-
-proc config_ddr_timing { } {
- global EMIF_SDRAM_TIM_1
- global EMIF_SDRAM_TIM_2
- global EMIF_SDRAM_TIM_3
- global EMIF_SDRAM_TIM_1_SHDW
- global EMIF_SDRAM_TIM_2_SHDW
- global EMIF_SDRAM_TIM_3_SHDW
- global EMIF_ZQ_CONFIG
-
- mww $EMIF_SDRAM_TIM_1 0xeaaad4db
- mww $EMIF_SDRAM_TIM_1_SHDW 0xeaaad4db
-
- mww $EMIF_SDRAM_TIM_2 0x266b7fda
- mww $EMIF_SDRAM_TIM_2_SHDW 0x266b7fda
-
- mww $EMIF_SDRAM_TIM_3 0x107f8678
- mww $EMIF_SDRAM_TIM_3_SHDW 0x107f8678
-
- mww $EMIF_ZQ_CONFIG 0x50074be4
-}
-
-proc config_ddr_pm { } {
- global EMIF_PWR_MGMT_CTRL
- global EMIF_PWR_MGMT_CTRL_SHDW
- global EMIF_DLL_CALIB_CTRL
- global EMIF_DLL_CALIB_CTRL_SHDW
- global EMIF_TEMP_ALERT_CONFIG
-
- mww $EMIF_PWR_MGMT_CTRL 0x00
- mww $EMIF_PWR_MGMT_CTRL_SHDW 0x00
- mww $EMIF_DLL_CALIB_CTRL 0x00050000
- mww $EMIF_DLL_CALIB_CTRL_SHDW 0x00050000
- mww $EMIF_TEMP_ALERT_CONFIG 0x00
-}
-
-proc config_ddr_priority { } {
- global EMIF_PRI_COS_MAP
- global EMIF_CONNID_COS_1_MAP
- global EMIF_CONNID_COS_2_MAP
- global EMIF_RD_WR_EXEC_THRSH
- global COS_CONFIG
-
- mww $EMIF_PRI_COS_MAP 0x00
- mww $EMIF_CONNID_COS_1_MAP 0x00
- mww $EMIF_CONNID_COS_2_MAP 0x0
- mww $EMIF_RD_WR_EXEC_THRSH 0x0405
- mww $COS_CONFIG 0x00ffffff
-}
-
-proc config_ddr3 { SDRAM_CONFIG } {
- global CM_DLL_CTRL
- global EMIF_IODFT_TLGC
- global EMIF_RDWR_LVL_CTRL
- global EMIF_RDWR_LVL_RMP_CTRL
- global EMIF_SDRAM_CONFIG
- global EMIF_SDRAM_CONFIG_EXT
- global EMIF_SDRAM_REF_CTRL
- global EMIF_SDRAM_REF_CTRL_SHDW
- global EMIF_STATUS
- global EXT_PHY_CTRL_36
- global EXT_PHY_CTRL_36_SHDW
-
- emif_prcm_clk_enable
- vtp_enable
-
- set dll [ expr [ mrw $CM_DLL_CTRL ] & ~0x01 ]
- mww $CM_DLL_CTRL $dll
- while { !([ mrw $CM_DLL_CTRL ] & 0x04) } { }
-
- config_ddr_ioctrl
-
- mww $EMIF_SDRAM_CONFIG_EXT 0xc163
- mww $EMIF_IODFT_TLGC 0x2011
- mww $EMIF_IODFT_TLGC 0x2411
- mww $EMIF_IODFT_TLGC 0x2011
- mww $EMIF_SDRAM_REF_CTRL 0x80003000
-
- config_ddr_phy
-
- mww $EMIF_IODFT_TLGC 0x2011
- mww $EMIF_IODFT_TLGC 0x2411
- mww $EMIF_IODFT_TLGC 0x2011
-
- config_ddr_timing
- config_ddr_pm
- config_ddr_priority
-
- mww $EMIF_SDRAM_REF_CTRL 0x3000
- mww $EMIF_SDRAM_CONFIG $SDRAM_CONFIG
-
- mww $EMIF_SDRAM_REF_CTRL 0x0c30
- mww $EMIF_SDRAM_REF_CTRL_SHDW 0x0c30
-
- sleep 10
-
- set tmp [ expr [ mrw $EXT_PHY_CTRL_36 ] | 0x0100 ]
- mww $EXT_PHY_CTRL_36 $tmp
- mww $EXT_PHY_CTRL_36_SHDW $tmp
-
- mww $EMIF_RDWR_LVL_RMP_CTRL 0x80000000
- mww $EMIF_RDWR_LVL_CTRL 0x80000000
-
- while { [ mrw $EMIF_RDWR_LVL_CTRL ] & 0x80000000 } { }
-
- if { [ mrw $EMIF_STATUS ] & 0x70 } {
- error "DDR3 Hardware Leveling incomplete!!!"
- }
-}
-
-proc init_platform { SDRAM_CONFIG } {
- config_opp100
- config_ddr3 $SDRAM_CONFIG
-}
-
-$_TARGETNAME configure -event reset-init { init_platform 0x61a013b2 }
-$_TARGETNAME configure -event reset-end { disable_watchdog }
diff --git a/openocd-0.10.0/scripts/target/amdm37x.cfg b/openocd-0.10.0/scripts/target/amdm37x.cfg
deleted file mode 100644
index c00dae921c49d79054691fede6f4d7450823e4e6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/amdm37x.cfg
+++ /dev/null
@@ -1,211 +0,0 @@
-#
-# Copyright (C) 2010-2011 by Karl Kurbjun
-# Copyright (C) 2009-2011 by Øyvind Harboe
-# Copyright (C) 2009 by David Brownell
-# Copyright (C) 2009 by Magnus Lundin
-#
-# TI AM/DM37x Technical Reference Manual (Version R)
-# http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf
-#
-# This script is based on the AM3517 initialization. It should be considered
-# preliminary since it needs more complete testing and only the basic
-# operations work.
-#
-
-###############################################################################
-# User modifiable parameters
-###############################################################################
-
-# This script uses the variable CHIPTYPE to determine whether this is an AM35x
-# or DM37x target. If CHIPTYPE is not set it will error out.
-if { [info exists CHIPTYPE] } {
-
- if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
- } else {
- set _CHIPNAME $CHIPTYPE
- }
-
- switch $CHIPTYPE {
- dm37x {
- # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan
- set _JRC_TAPID "-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f"
- }
- am35x {
- # Primary TAP: ICEPick-C (JTAG route controller) and boundary scan
- set _JRC_TAPID "-expected-id 0x0b7ae02f -expected-id 0x0b86802f"
- }
- default {
- error "ERROR: CHIPTYPE was set, but it was not set to a valid value. Acceptable values are \"dm37x\" or \"am35x\"."
- }
- }
-} else {
- error "ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \"am35x\" for the AM35x or \"dm37x\" for the DM37x series in the board configuration."
-}
-
-# Run the adapter at the fastest acceptable speed with the slowest possible
-# core clock.
-adapter_khz 10
-
-###############################################################################
-# JTAG setup
-# The OpenOCD commands are described in the TAP Declaration section
-# http://openocd.org/doc/html/TAP-Declaration.html
-###############################################################################
-
-# The AM/DM37x has an ICEPick module in it like many of TI's other devices. More
-# can be read about this module in sprugn4r in chapter 27: "Debug and
-# Emulation". The module is used to route the JTAG chain to the various
-# subsystems in the chip.
-source [find target/icepick.cfg]
-
-# The TAP order should be described from the TDO connection in OpenOCD to the
-# TDI pin. The OpenOCD FAQ describes this in more detail:
-# http://openocd.org/doc/html/FAQ.html
-
-# From SPRUGN4R CH27 the available secondary TAPs are in this order from TDO:
-#
-# Device | TAP number
-# ---------|------------
-# DAP | 3
-# Sequencer| 2 Note: The sequencer is an ARM968
-# DSP | 1
-# D2D | 0
-#
-# Right now the only secondary tap enabled is the DAP so the rest are left
-# undescribed.
-
-######
-# Start of Chain Description
-# The Secondary TAPs all have enable functions defined for use with the ICEPick
-# Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but
-# the TAP numbers for ICEPick do not change.
-#
-# TODO: A disable function should also be added.
-######
-
-# Secondary TAP: DAP is closest to the TDO output
-# The TAP enable event also needs to be described
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 3"
-
-# These taps are only present in the DM37x series.
-if { $CHIPTYPE == "dm37x" } {
- # Secondary TAP: Sequencer (ARM968) it is not in the chain by default
- # The ICEPick can be used to enable it in the chain.
- jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
- jtag configure $_CHIPNAME.arm2 -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 2"
-
- # Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable)
- # The ICEPick can be used to enable it in the chain.
- jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
- jtag configure $_CHIPNAME.dsp -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 1"
-}
-
-# Secondary TAP: D2D it is not in the chain by default (-disable)
-# The ICEPick can be used to enable it in the chain.
-# This IRLEN is probably incorrect - not sure where the documentation is.
-jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable
-jtag configure $_CHIPNAME.d2d -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 0"
-
-# Primary TAP: ICEPick - it is closest to TDI so last in the chain
-eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID"
-
-######
-# End of Chain Description
-######
-
-######
-# Start JTAG TAP events
-######
-
-# some TCK tycles are required to activate the DEBUG power domain
-jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
-
-# Enable the DAP TAP
-jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
-
-######
-# End JTAG TAP events
-######
-
-###############################################################################
-# Target Setup:
-# This section is described in the OpenOCD documentation under CPU Configuration
-# http://openocd.org/doc/html/CPU-Configuration.html
-###############################################################################
-
-# Create the CPU target to be used with GDB: Cortex-A8, using DAP
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
-
-# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first
-# 16K to be used as a scratchpad for OpenOCD.
-
-$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
-
-######
-# Start Target Reset Event Setup:
-######
-
-# Set the JTAG clock down to 10 kHz to be sure that it will work with the
-# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
-# *after* PLL and clock tree setup.
-
-$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
-
-# Describe the reset assert process for openocd - this is asserted with the
-# ICEPick
-$_TARGETNAME configure -event "reset-assert" {
-
- global _CHIPNAME
-
- # assert warm system reset through ICEPick
- icepick_c_wreset $_CHIPNAME.jrc
-}
-
-# After the reset is asserted we need to re-initialize debugging and speed up
-# the JTAG clock.
-
-$_TARGETNAME configure -event reset-assert-post {
-
- global _TARGETNAME
- amdm37x_dbginit $_TARGETNAME
- adapter_khz 1000
-}
-
-$_TARGETNAME configure -event gdb-attach {
-
- global _TARGETNAME
- amdm37x_dbginit $_TARGETNAME
-
- echo "Halting target"
- halt
-}
-
-######
-# End Target Reset Event Setup:
-######
-
-###############################################################################
-# Target Functions
-# Add any functions needed for the target here
-###############################################################################
-
-# Run this to enable invasive debugging. This is run automatically in the
-# reset sequence.
-proc amdm37x_dbginit {target} {
- # General Cortex-A8 debug initialisation
- cortex_a dbginit
-
- # Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
- # access to the signal appears to be implementation specific. TI does not
- # describe this register much except a quick line that states DBGEM (sic) is
- # at this address and this bit.
- $target mww phys 0x5401d030 0x00002000
-}
-
diff --git a/openocd-0.10.0/scripts/target/ar71xx.cfg b/openocd-0.10.0/scripts/target/ar71xx.cfg
deleted file mode 100644
index 196b048685c77df1f77007d00b95faaee33885d6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ar71xx.cfg
+++ /dev/null
@@ -1,57 +0,0 @@
-# Atheros AR71xx MIPS 24Kc SoC.
-# tested on PB44 refererence board
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
-reset_config trst_and_srst
-
-set CHIPNAME ar71xx
-
-jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
-
-set _TARGETNAME $CHIPNAME.cpu
-target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -event reset-halt-post {
- #setup PLL to lowest common denominator 300/300/150 setting
- mww 0xb8050000 0x000f40a3 ;# reset val + CPU:3 DDR:3 AHB:0
- mww 0xb8050000 0x800f40a3 ;# send to PLL
-
- #next command will reset for PLL changes to take effect
- mww 0xb8050008 3 ;# set reset_switch and clock_switch (resets SoC)
-}
-
-$_TARGETNAME configure -event reset-init {
- #complete pll initialization
- mww 0xb8050000 0x800f0080 ;# set sw_update bit
- mww 0xb8050008 0 ;# clear reset_switch bit
- mww 0xb8050000 0x800f00e8 ;# clr pwrdwn & bypass
- mww 0xb8050008 1 ;# set clock_switch bit
- sleep 1 ;# wait for lock
-
- # Setup DDR config and flash mapping
- mww 0xb8000000 0xefbc8cd0 ;# DDR cfg cdl val (rst: 0x5bfc8d0)
- mww 0xb8000004 0x8e7156a2 ;# DDR cfg2 cdl val (rst: 0x80d106a8)
-
- mww 0xb8000010 8 ;# force precharge all banks
- mww 0xb8000010 1 ;# force EMRS update cycle
- mww 0xb800000c 0 ;# clr ext. mode register
- mww 0xb8000010 2 ;# force auto refresh all banks
- mww 0xb8000010 8 ;# force precharge all banks
- mww 0xb8000008 0x31 ;# set DDR mode value CAS=3
- mww 0xb8000010 1 ;# force EMRS update cycle
- mww 0xb8000014 0x461b ;# DDR refresh value
- mww 0xb8000018 0xffff ;# DDR Read Data This Cycle value (16bit: 0xffff)
- mww 0xb800001c 0x7 ;# delay added to the DQS line (normal = 7)
- mww 0xb8000020 0
- mww 0xb8000024 0
- mww 0xb8000028 0
-}
-
-# setup working area somewhere in RAM
-$_TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
-
-# serial SPI capable flash
-# flash bank <driver> <base> <size> <chip_width> <bus_width>
-
diff --git a/openocd-0.10.0/scripts/target/armada370.cfg b/openocd-0.10.0/scripts/target/armada370.cfg
deleted file mode 100644
index 40c779bdc90e0cbdc1918ad74f377d9d24f3345a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/armada370.cfg
+++ /dev/null
@@ -1,33 +0,0 @@
-#
-# armada370 -- support for the Marvell Armada/370 CPU family
-#
-# gerg@uclinux.org, OCT-2013
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME armada370
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4ba00477
-}
-
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
-
-proc armada370_dbginit {target} {
- cortex_a dbginit
-}
-
-$_TARGETNAME configure -event reset-assert-post "armada370_dbginit $_TARGETNAME"
-
-# We need to init now, so we can run the apsel command.
-init
-dap apsel 1
-
diff --git a/openocd-0.10.0/scripts/target/at32ap7000.cfg b/openocd-0.10.0/scripts/target/at32ap7000.cfg
deleted file mode 100644
index 8573aa1c467dd56c186b8c7675c65113e37e40c7..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at32ap7000.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-# Atmel AT32AP7000
-#
-# This is the only core in the now-inactive high end AVR32 product line,
-# with MMU, Java Acceleration, and "pixel coprocessor". The AP7 line
-# is for "Application Processors" (AP) with 7-stage pipelines.
-#
-# Most current AVR32 parts are in the UC3 flash based microcontroller (UC)
-# product line with 3-stage pipelines and without those extras.
-#
-# All AVR32 parts provide the Nexus Class 3 on-chip debug interfaces
-# through their JTAG interfaces.
-
-jtag newtap ap7 nexus -irlen 5 -expected-id 0x21e8203f
-
-# REVISIT declare an avr32 target ... needs OpenOCD infrastructure
-# for both Nexus (generic) and AVR32 (Atmel-specific).
diff --git a/openocd-0.10.0/scripts/target/at91r40008.cfg b/openocd-0.10.0/scripts/target/at91r40008.cfg
deleted file mode 100644
index 912bd0ea2f8810790d8ff3928c7412b31aa61ff6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91r40008.cfg
+++ /dev/null
@@ -1,29 +0,0 @@
-# AT91R40008 target configuration file
-
-# TRST is tied to SRST on the AT91X40 family.
-reset_config srst_only srst_pulls_trst
-
-
-if {[info exists CHIPNAME]} {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME at91r40008
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# Setup the JTAG scan chain.
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x1f0f0f0f
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0
diff --git a/openocd-0.10.0/scripts/target/at91rm9200.cfg b/openocd-0.10.0/scripts/target/at91rm9200.cfg
deleted file mode 100644
index 2e8c1e091f7788dfa2abdda61ec61cae7888f2aa..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91rm9200.cfg
+++ /dev/null
@@ -1,47 +0,0 @@
-# Atmel AT91rm9200
-# http://atmel.com/products/at91/
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME at91rm9200
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x05b0203f
-}
-
-# Never allow the following!
-if { $_CPUTAPID == 0x15b0203f } {
- echo "-------------------------------------------------------"
- echo "- ERROR: -"
- echo "- ERROR: TapID 0x15b0203f is wrong for at91rm9200 -"
- echo "- ERROR: The chip/board has a JTAG select pin/jumper -"
- echo "- ERROR: -"
- echo "- ERROR: In one position (0x05b0203f) it selects the -"
- echo "- ERROR: ARM CPU, in the other position (0x1b0203f) -"
- echo "- ERROR: it selects boundry-scan not the ARM -"
- echo "- ERROR: -"
- echo "-------------------------------------------------------"
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# Create the GDB Target.
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# AT91RM9200 has a 16K block of sram @ 0x0020.0000
-$_TARGETNAME configure -work-area-phys 0x00200000 \
- -work-area-size 0x4000 -work-area-backup 1
-
-# This chip has a DCC ... use it
-arm7_9 dcc_downloads enable
diff --git a/openocd-0.10.0/scripts/target/at91sam3XXX.cfg b/openocd-0.10.0/scripts/target/at91sam3XXX.cfg
deleted file mode 100644
index fca655d2cbf90f2a2c7a723757197dedfd9dbeec..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam3XXX.cfg
+++ /dev/null
@@ -1,87 +0,0 @@
-# script for ATMEL sam3, a Cortex-M3 chip
-#
-# at91sam3u4e
-# at91sam3u2e
-# at91sam3u1e
-# at91sam3u4c
-# at91sam3u2c
-# at91sam3u1c
-#
-# at91sam3s4c
-# at91sam3s4b
-# at91sam3s4a
-# at91sam3s2c
-# at91sam3s2b
-# at91sam3s2a
-# at91sam3s1c
-# at91sam3s1b
-# at91sam3s1a
-#
-# at91sam3A4C
-# at91sam3A8C
-# at91sam3X4C
-# at91sam3X4E
-# at91sam3X8C
-# at91sam3X8E
-# at91sam3X8H
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME sam3
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 64kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x4000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4ba00477
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# 16K is plenty, the smallest chip has this much
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-$_TARGETNAME configure -event gdb-flash-erase-start {
- halt
-}
-
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz
-#
-# Since we may be running of an RC oscilator, we crank down the speed a
-# bit more to be on the safe side. Perhaps superstition, but if are
-# running off a crystal, we can run closer to the limit. Note
-# that there can be a pretty wide band where things are more or less stable.
-
-adapter_khz 500
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/at91sam3ax_4x.cfg b/openocd-0.10.0/scripts/target/at91sam3ax_4x.cfg
deleted file mode 100644
index 78ca79f694987892dc4fb9e67a1f365e45c8104e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam3ax_4x.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-# common stuff
-source [find target/at91sam3ax_xx.cfg]
-
-# size is automatically "calculated" by probing
-set _FLASHNAME $_CHIPNAME.flash0
-flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-# This is a 256K chip - it has the 2nd bank
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME at91sam3 0x0000A0000 0 1 1 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/at91sam3ax_8x.cfg b/openocd-0.10.0/scripts/target/at91sam3ax_8x.cfg
deleted file mode 100644
index e2493837d005927fc3a313750f051e71538b2abb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam3ax_8x.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# common stuff
-source [find target/at91sam3ax_xx.cfg]
-
-# size is automatically "calculated" by probing
-set _FLASHNAME $_CHIPNAME.flash0
-flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-# This is a 512K chip - it has the 2nd bank
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME at91sam3 0x0000C0000 0 1 1 $_TARGETNAME
-
-
diff --git a/openocd-0.10.0/scripts/target/at91sam3ax_xx.cfg b/openocd-0.10.0/scripts/target/at91sam3ax_xx.cfg
deleted file mode 100644
index e561771222b272a8ff681f6bc30533781eeed82f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam3ax_xx.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# script for ATMEL sam3, a Cortex-M3 chip
-#
-# at91sam3A4C
-# at91sam3A8C
-# at91sam3X4C
-# at91sam3X4E
-# at91sam3X8C
-# at91sam3X8E
-# at91sam3X8H
-source [find target/at91sam3XXX.cfg]
-
diff --git a/openocd-0.10.0/scripts/target/at91sam3nXX.cfg b/openocd-0.10.0/scripts/target/at91sam3nXX.cfg
deleted file mode 100644
index 19bd33a9e8f801a5e76e7a0089f65c024f95f88d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam3nXX.cfg
+++ /dev/null
@@ -1,32 +0,0 @@
-
-#
-# Configuration for Atmel's SAM3N series
-#
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME at91sam3n
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4ba00477
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/at91sam3sXX.cfg b/openocd-0.10.0/scripts/target/at91sam3sXX.cfg
deleted file mode 100644
index 09146bd0feda2fc5fec2ec502c6148b5f59a681c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam3sXX.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-# script for ATMEL sam3, a Cortex-M3 chip
-#
-# at91sam3s4c
-# at91sam3s4b
-# at91sam3s4a
-# at91sam3s2c
-# at91sam3s2b
-# at91sam3s2a
-# at91sam3s1c
-# at91sam3s1b
-# at91sam3s1a
-
-source [find target/at91sam3XXX.cfg]
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91sam3 0x00400000 0 1 1 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/at91sam3u1c.cfg b/openocd-0.10.0/scripts/target/at91sam3u1c.cfg
deleted file mode 100644
index 47c227b262cfb7eb8eef7c3ae4913498b6c48241..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam3u1c.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# common stuff
-source [find target/at91sam3uxx.cfg]
-
-# size is automatically "calculated" by probing
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-
-
diff --git a/openocd-0.10.0/scripts/target/at91sam3u1e.cfg b/openocd-0.10.0/scripts/target/at91sam3u1e.cfg
deleted file mode 100644
index 47c227b262cfb7eb8eef7c3ae4913498b6c48241..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam3u1e.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# common stuff
-source [find target/at91sam3uxx.cfg]
-
-# size is automatically "calculated" by probing
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-
-
diff --git a/openocd-0.10.0/scripts/target/at91sam3u2c.cfg b/openocd-0.10.0/scripts/target/at91sam3u2c.cfg
deleted file mode 100644
index 47c227b262cfb7eb8eef7c3ae4913498b6c48241..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam3u2c.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# common stuff
-source [find target/at91sam3uxx.cfg]
-
-# size is automatically "calculated" by probing
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-
-
diff --git a/openocd-0.10.0/scripts/target/at91sam3u2e.cfg b/openocd-0.10.0/scripts/target/at91sam3u2e.cfg
deleted file mode 100644
index 47c227b262cfb7eb8eef7c3ae4913498b6c48241..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam3u2e.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# common stuff
-source [find target/at91sam3uxx.cfg]
-
-# size is automatically "calculated" by probing
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-
-
diff --git a/openocd-0.10.0/scripts/target/at91sam3u4c.cfg b/openocd-0.10.0/scripts/target/at91sam3u4c.cfg
deleted file mode 100644
index 5cacbcbef6f1068aa30bbc59de558a9641c7c43c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam3u4c.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# common stuff
-source [find target/at91sam3uxx.cfg]
-
-# size is automatically "calculated" by probing
-set _FLASHNAME $_CHIPNAME.flash0
-flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-# This is a 256K chip, it has the 2nd bank
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
-
-
diff --git a/openocd-0.10.0/scripts/target/at91sam3u4e.cfg b/openocd-0.10.0/scripts/target/at91sam3u4e.cfg
deleted file mode 100644
index a48f99265912b0ac125686536664eda5dd4dbe7d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam3u4e.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# common stuff
-source [find target/at91sam3uxx.cfg]
-
-# size is automatically "calculated" by probing
-set _FLASHNAME $_CHIPNAME.flash0
-flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
-# This is a 256K chip - it has the 2nd bank
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
-
-
diff --git a/openocd-0.10.0/scripts/target/at91sam3uxx.cfg b/openocd-0.10.0/scripts/target/at91sam3uxx.cfg
deleted file mode 100644
index b42ae19cf3be07a42d5f10be31209939dee9c867..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam3uxx.cfg
+++ /dev/null
@@ -1,11 +0,0 @@
-# script for ATMEL sam3, a Cortex-M3 chip
-#
-# at91sam3u4e
-# at91sam3u2e
-# at91sam3u1e
-# at91sam3u4c
-# at91sam3u2c
-# at91sam3u1c
-
-source [find target/at91sam3XXX.cfg]
-
diff --git a/openocd-0.10.0/scripts/target/at91sam4XXX.cfg b/openocd-0.10.0/scripts/target/at91sam4XXX.cfg
deleted file mode 100644
index ca801431af1797f04ca07b2725645caa6fc71a7d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam4XXX.cfg
+++ /dev/null
@@ -1,63 +0,0 @@
-#
-# script for ATMEL sam4, a Cortex-M4 chip
-#
-
-#
-# sam4 devices can support both JTAG and SWD transports.
-#
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME sam4
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 64kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x4000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4ba00477
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# 16K is plenty, the smallest chip has this much
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 4 MHz, so use F_JTAG = 0.5MHz
-#
-# Since we may be running of an RC oscilator, we crank down the speed a
-# bit more to be on the safe side. Perhaps superstition, but if are
-# running off a crystal, we can run closer to the limit. Note
-# that there can be a pretty wide band where things are more or less stable.
-
-adapter_khz 500
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/at91sam4c32x.cfg b/openocd-0.10.0/scripts/target/at91sam4c32x.cfg
deleted file mode 100644
index 5344e0c54761b147c8c25a433bc026d58c8843e2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam4c32x.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-# script for ATMEL sam4c32, a Cortex-M4 chip
-#
-
-source [find target/at91sam4XXX.cfg]
-
-set _FLASHNAME $_CHIPNAME.flash0
-flash bank $_FLASHNAME at91sam4 0x01000000 0 1 1 $_TARGETNAME
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME at91sam4 0x01100000 0 1 1 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/at91sam4cXXX.cfg b/openocd-0.10.0/scripts/target/at91sam4cXXX.cfg
deleted file mode 100644
index 3f10c61d0fdcc3b6a51124cdc425d4d5836d5437..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam4cXXX.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-# script for ATMEL sam4c, a Cortex-M4 chip
-#
-
-source [find target/at91sam4XXX.cfg]
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91sam4 0x01000000 0 1 1 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/at91sam4lXX.cfg b/openocd-0.10.0/scripts/target/at91sam4lXX.cfg
deleted file mode 100644
index 4aee7d08145f7f290ae58467495eb4d708f3a46d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam4lXX.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-# script for ATMEL sam4l, a Cortex-M4 chip
-#
-
-source [find target/at91sam4XXX.cfg]
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91sam4l 0x00000000 0 1 1 $_TARGETNAME
-
-# SAM4L SMAP will hold the CPU in reset if TCK is low when RESET_N
-# deasserts (see datasheet 42023E-SAM-07/2013 sec 8.11.3).
-#
-# smap_reset_deassert configures whether we want to run or halt out of reset,
-# then instruct the SMAP to let us out of reset.
-$_TARGETNAME configure -event reset-deassert-post "at91sam4l smap_reset_deassert"
-
-# SRST (wired to RESET_N) resets debug circuitry
-# srst_pulls_trst is not configured here to avoid an error raised in reset halt
-reset_config srst_gates_jtag
-
-# SAM4L starts from POR with SYSCLK set to 115kHz RCSYS, needs slow JTAG speed.
-# Datasheet does not specify SYSCLK to JTAG/SWD clock ratio.
-# Usually used SYSCLK/6 is hell slow, testing shows that debugging can work @ SYSCLK/2
-# but your mileage may vary.
-adapter_khz 50
-
-# System RC oscillator RCSYS starts in 3 cycles
-adapter_nsrst_delay 0
diff --git a/openocd-0.10.0/scripts/target/at91sam4sXX.cfg b/openocd-0.10.0/scripts/target/at91sam4sXX.cfg
deleted file mode 100644
index 8883e23ca584f404e1c4a8cb589da914b4291536..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam4sXX.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-# script for ATMEL sam4, a Cortex-M4 chip
-#
-
-source [find target/at91sam4XXX.cfg]
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/at91sam4sd32x.cfg b/openocd-0.10.0/scripts/target/at91sam4sd32x.cfg
deleted file mode 100644
index 077b1f51f57e1f35e519dc3fbc5cc1e3f9906d31..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam4sd32x.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-# script for ATMEL sam4sd32, a Cortex-M4 chip
-#
-
-source [find target/at91sam4XXX.cfg]
-
-set _FLASHNAME $_CHIPNAME.flash0
-flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME at91sam4 0x00500000 0 1 1 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/at91sam7a2.cfg b/openocd-0.10.0/scripts/target/at91sam7a2.cfg
deleted file mode 100644
index f7a0de2d69350ec89965850218738e283ce3cc26..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam7a2.cfg
+++ /dev/null
@@ -1,23 +0,0 @@
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME at91sam7a2
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x1f0f0f0f
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/at91sam7se512.cfg b/openocd-0.10.0/scripts/target/at91sam7se512.cfg
deleted file mode 100644
index ab0970128d8806dcfa8ce42b9aff081218e67438..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam7se512.cfg
+++ /dev/null
@@ -1,39 +0,0 @@
-# ATMEL sam7se512
-# Example: the "Elektor Internet Radio" - EIR
-# http://www.ethernut.de/en/hardware/eir/index.html
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME sam7se512
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # Force an error until we get a good number.
- set _CPUTAPID 0xffffffff
-}
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only srst_pulls_trst
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# The target
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
-
diff --git a/openocd-0.10.0/scripts/target/at91sam7sx.cfg b/openocd-0.10.0/scripts/target/at91sam7sx.cfg
deleted file mode 100644
index a563ac0377e2af53dc992afa4e932fba9243fe9a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam7sx.cfg
+++ /dev/null
@@ -1,53 +0,0 @@
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only srst_pulls_trst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME at91sam7s
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x3f0f0f0f
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-$_TARGETNAME configure -event reset-init {
- soft_reset_halt
- # RSTC_CR : Reset peripherals
- mww 0xfffffd00 0xa5000004
- # disable watchdog
- mww 0xfffffd44 0x00008000
- # enable user reset
- mww 0xfffffd08 0xa5000001
- # CKGR_MOR : enable the main oscillator
- mww 0xfffffc20 0x00000601
- sleep 10
- # CKGR_PLLR: 96.1097 MHz
- mww 0xfffffc2c 0x00481c0e
- sleep 10
- # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
- mww 0xfffffc30 0x00000007
- sleep 10
- # MC_FMR: flash mode (FWS=1,FMCN=73)
- mww 0xffffff60 0x00490100
- sleep 100
-}
-
-$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
diff --git a/openocd-0.10.0/scripts/target/at91sam7x256.cfg b/openocd-0.10.0/scripts/target/at91sam7x256.cfg
deleted file mode 100644
index e1a243523fe7ad70708f5d796e135ec9f50ab422..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam7x256.cfg
+++ /dev/null
@@ -1,50 +0,0 @@
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only srst_pulls_trst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME sam7x256
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x3f0f0f0f
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -event reset-init {
- # disable watchdog
- mww 0xfffffd44 0x00008000
- # enable user reset
- mww 0xfffffd08 0xa5000001
- # CKGR_MOR : enable the main oscillator
- mww 0xfffffc20 0x00000601
- sleep 10
- # CKGR_PLLR: 96.1097 MHz
- mww 0xfffffc2c 0x00481c0e
- sleep 10
- # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
- mww 0xfffffc30 0x00000007
- sleep 10
- # MC_FMR: flash mode (FWS=1,FMCN=60)
- mww 0xffffff60 0x003c0100
- sleep 100
-}
-
-$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
diff --git a/openocd-0.10.0/scripts/target/at91sam7x512.cfg b/openocd-0.10.0/scripts/target/at91sam7x512.cfg
deleted file mode 100644
index 6910e8559d16b8d167420c15463873fe11c6630f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam7x512.cfg
+++ /dev/null
@@ -1,51 +0,0 @@
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only srst_pulls_trst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME sam7x512
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x3f0f0f0f
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -event reset-init {
- # disable watchdog
- mww 0xfffffd44 0x00008000
- # enable user reset
- mww 0xfffffd08 0xa5000001
- # CKGR_MOR : enable the main oscillator
- mww 0xfffffc20 0x00000601
- sleep 10
- # CKGR_PLLR: 96.1097 MHz
- mww 0xfffffc2c 0x00481c0e
- sleep 10
- # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
- mww 0xfffffc30 0x00000007
- sleep 10
- # MC_FMR: flash mode (FWS=1,FMCN=60)
- mww 0xffffff60 0x003c0100
- sleep 100
-}
-
-$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME.0 at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
-flash bank $_FLASHNAME.1 at91sam7 0 0 0 0 $_TARGETNAME 1 0 0 0 0 0 0 18432
diff --git a/openocd-0.10.0/scripts/target/at91sam9.cfg b/openocd-0.10.0/scripts/target/at91sam9.cfg
deleted file mode 100644
index bf99fb2fa604c026e84d3943e147bafaf75b072d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam9.cfg
+++ /dev/null
@@ -1,37 +0,0 @@
-######################################
-# Target: Atmel AT91SAM9
-######################################
-
-if { [info exists AT91_CHIPNAME] } {
- set _CHIPNAME $AT91_CHIPNAME
-} else {
- error "you must specify a chip name"
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x0792603f
-}
-
-reset_config trst_and_srst separate trst_push_pull srst_open_drain
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-adapter_nsrst_delay 300
-jtag_ntrst_delay 200
-
-adapter_khz 3
-
-######################
-# Target configuration
-######################
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/at91sam9260.cfg b/openocd-0.10.0/scripts/target/at91sam9260.cfg
deleted file mode 100644
index c5a07fdd995bda53322e10945e12e634f8479f25..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam9260.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-######################################
-# Target: Atmel AT91SAM9260
-######################################
-
-if { [info exists CHIPNAME] } {
- set AT91_CHIPNAME $CHIPNAME
-} else {
- set AT91_CHIPNAME at91sam9260
-}
-
-source [find target/at91sam9.cfg]
-
-
-# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
-# AT91SAM9260 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
-# Both areas are 4 kB long.
-
-#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x1000 -work-area-backup 1
-$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
diff --git a/openocd-0.10.0/scripts/target/at91sam9260_ext_RAM_ext_flash.cfg b/openocd-0.10.0/scripts/target/at91sam9260_ext_RAM_ext_flash.cfg
deleted file mode 100644
index 9ab7409048eb7aada94386feb62375d72874db3e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam9260_ext_RAM_ext_flash.cfg
+++ /dev/null
@@ -1,89 +0,0 @@
-######################################
-# Target: Atmel AT91SAM9260
-######################################
-
-source [find target/at91sam9261.cfg]
-
-reset_config trst_and_srst
-
-adapter_khz 4
-
-adapter_nsrst_delay 200
-jtag_ntrst_delay 200
-
-scan_chain
-$_TARGETNAME configure -event reset-start {
- # at reset chip runs at 32khz
- adapter_khz 8
-}
-
-$_TARGETNAME configure -event reset-init {at91sam_init}
-
-# Flash configuration
-#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
-
-# Faster memory downloads. This is disabled automatically during
-# reset init since all reset init sequences are too short for
-# fast memory access
-arm7_9 dcc_downloads enable
-arm7_9 fast_memory_access enable
-
-proc at91sam_init { } {
- mww 0xfffffd08 0xa5000501 ;# RSTC_MR : enable user reset
- mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
-
- mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
- sleep 20 ;# wait 20 ms
- mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
- sleep 10 ;# wait 10 ms
- mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198,656MHz
- sleep 20 ;# wait 20 ms
- mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler
- sleep 10 ;# wait 10 ms
- mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected
- sleep 10 ;# wait 10 ms
-
- # Now run at anything fast... ie: 10mhz!
- adapter_khz 10000 ;# Increase JTAG Speed to 6 MHz
-
- mww 0xffffec00 0x0a0a0a0a ;# SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
- mww 0xffffec04 0x0b0b0b0b ;# SMC_PULSE0
- mww 0xffffec08 0x00160016 ;# SMC_CYCLE0
- mww 0xffffec0c 0x00161003 ;# SMC_MODE0
-
- mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
- mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
-
- mww 0xffffef1c 0x2 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
-
- mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
- #mww 0xffffea08 0x85227254 ;# SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
-
- mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
- mww 0x20000000 0
- mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
- mww 0x20000000 0
- mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x4
- mww 0x20000000 0
- mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
- mww 0x20000000 0
- mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
- mww 0x20000000 0
- mww 0xffffea04 0x5d2 ;# SDRAMC_TR : Set refresh timer count to 15us
-}
diff --git a/openocd-0.10.0/scripts/target/at91sam9261.cfg b/openocd-0.10.0/scripts/target/at91sam9261.cfg
deleted file mode 100644
index 3ad141182aa1ffe2edeb3c5157d8151135224f4b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam9261.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-######################################
-# Target: Atmel AT91SAM9261
-######################################
-
-if { [info exists CHIPNAME] } {
- set AT91_CHIPNAME $CHIPNAME
-} else {
- set AT91_CHIPNAME at91sam9261
-}
-
-source [find target/at91sam9.cfg]
-
-# Internal sram1 memory
-$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x28000 -work-area-backup 1
diff --git a/openocd-0.10.0/scripts/target/at91sam9263.cfg b/openocd-0.10.0/scripts/target/at91sam9263.cfg
deleted file mode 100644
index d2ee113b2cb0ab781ab0665d7559c466fee9de78..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam9263.cfg
+++ /dev/null
@@ -1,20 +0,0 @@
-######################################
-# Target: Atmel AT91SAM9263
-######################################
-
-if { [info exists CHIPNAME] } {
- set AT91_CHIPNAME $CHIPNAME
-} else {
- set AT91_CHIPNAME at91sam9263
-}
-
-source [find target/at91sam9.cfg]
-
-# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
-# AT91SAM9263 has two SRAM areas,
-# one starting at 0x00300000 of 80KiB
-# and the other starting at 0x00500000 of 16KiB.
-
-# Internal sram1 memory
-$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x14000 -work-area-backup 1
-#$_TARGETNAME configure -work-area-phys 0x00500000 -work-area-size 0x4000 -work-area-backup 1
diff --git a/openocd-0.10.0/scripts/target/at91sam9g10.cfg b/openocd-0.10.0/scripts/target/at91sam9g10.cfg
deleted file mode 100644
index b49f3d9d28a7817cf601048eb21d91899ccb8e66..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam9g10.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-######################################
-# Target: Atmel AT91SAM9G10
-######################################
-
-if { [info exists CHIPNAME] } {
- set AT91_CHIPNAME $CHIPNAME
-} else {
- set AT91_CHIPNAME at91sam9g10
-}
-
-source [find target/at91sam9.cfg]
-
-# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
-# AT91SAM9G10 has one SRAM area at 0x00300000 of 16KiB
-
-$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
diff --git a/openocd-0.10.0/scripts/target/at91sam9g20.cfg b/openocd-0.10.0/scripts/target/at91sam9g20.cfg
deleted file mode 100644
index 3f5e3c6264d3e63834e4abe48ea180d34be0ac58..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam9g20.cfg
+++ /dev/null
@@ -1,22 +0,0 @@
-######################################
-# Target: Atmel AT91SAM9G20
-######################################
-
-if { [info exists CHIPNAME] } {
- set AT91_CHIPNAME $CHIPNAME
-} else {
- set AT91_CHIPNAME at91sam9g20
-}
-
-source [find target/at91sam9.cfg]
-
-# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
-
-adapter_khz 5
-
-# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
-# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
-# Both areas are 16 kB long.
-
-#$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
-$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
diff --git a/openocd-0.10.0/scripts/target/at91sam9g45.cfg b/openocd-0.10.0/scripts/target/at91sam9g45.cfg
deleted file mode 100644
index 7323679b9e1dea726e883cc593f1d57f9bb6fd11..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam9g45.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-######################################
-# Target: Atmel AT91SAM9G45
-######################################
-
-if { [info exists CHIPNAME] } {
- set AT91_CHIPNAME $CHIPNAME
-} else {
- set AT91_CHIPNAME at91sam9g45
-}
-
-source [find target/at91sam9.cfg]
-
-# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The
-# AT91SAM9G45 has one SRAM area starting at 0x00300000 of 64 KiB.
-
-$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x200000 -work-area-backup 1
diff --git a/openocd-0.10.0/scripts/target/at91sam9rl.cfg b/openocd-0.10.0/scripts/target/at91sam9rl.cfg
deleted file mode 100644
index db0522928b4019f82cd42abe2a83bec60308c757..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91sam9rl.cfg
+++ /dev/null
@@ -1,14 +0,0 @@
-######################################
-# Target: Atmel AT91SAM9RL
-######################################
-
-if { [info exists CHIPNAME] } {
- set AT91_CHIPNAME $CHIPNAME
-} else {
- set AT91_CHIPNAME at91sam9rl
-}
-
-source [find target/at91sam9.cfg]
-
-# Internal sram1 memory
-$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x10000 -work-area-backup 1
diff --git a/openocd-0.10.0/scripts/target/at91samdXX.cfg b/openocd-0.10.0/scripts/target/at91samdXX.cfg
deleted file mode 100644
index 93a95c8eb9bc6d3817a21ad65d0fd0f83daedcad..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91samdXX.cfg
+++ /dev/null
@@ -1,82 +0,0 @@
-#
-# script for Atmel SAMD, SAMR, SAML or SAMC, a Cortex-M0 chip
-#
-
-#
-# samdXX devices only support SWD transports.
-#
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME at91samd
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 2kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x800
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4ba00477
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# SAMD DSU will hold the CPU in reset if TCK is low when RESET_N
-# deasserts (see datasheet Atmel-42181E–SAM-D21_Datasheet–02/2015, section 12.6.2)
-#
-# dsu_reset_deassert configures whether we want to run or halt out of reset,
-# then instruct the DSU to let us out of reset.
-$_TARGETNAME configure -event reset-deassert-post {
- at91samd dsu_reset_deassert
-}
-
-# SRST (wired to RESET_N) resets debug circuitry
-# srst_pulls_trst is not configured here to avoid an error raised in reset halt
-reset_config srst_gates_jtag
-
-# Do not use a reset button with other SWD adapter than Atmel's EDBG.
-# DSU usually locks MCU in reset state until you issue a reset command
-# in OpenOCD.
-
-# SAMD runs at SYSCLK = 1 MHz divided from RC oscillator after reset.
-# Other members of family usually use SYSCLK = 4 MHz after reset.
-# Datasheet does not specify SYSCLK to SWD clock ratio.
-# Usually used SYSCLK/6 is slow, testing shows that debugging can
-# work @ SYSCLK/2 but your mileage may vary.
-# This limit is most probably imposed by incorrectly handled SWD WAIT
-# on some SWD adapters.
-
-adapter_khz 400
-
-# Atmel's EDBG (on-board cmsis-dap adapter of Xplained kits) works
-# without problem at maximal clock speed. Atmel recommends
-# adapter speed less than 10 * CPU clock.
-# adapter_khz 5000
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91samd 0x00000000 0 1 1 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/at91samg5x.cfg b/openocd-0.10.0/scripts/target/at91samg5x.cfg
deleted file mode 100644
index 57274c0c577acf3f3761430d0c40899b90dea921..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/at91samg5x.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-# script for the ATMEL samg5x Cortex-M4F chip family
-#
-
-source [find target/at91sam4XXX.cfg]
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91sam4 0x00400000 0 1 1 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/atheros_ar2313.cfg b/openocd-0.10.0/scripts/target/atheros_ar2313.cfg
deleted file mode 100644
index 0966c6c7ecf24a9e2ba70ae2875a77e2608d848c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/atheros_ar2313.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $_CHIPNAME
-} else {
- set _CHIPNAME ar2313
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x00000001
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/atheros_ar2315.cfg b/openocd-0.10.0/scripts/target/atheros_ar2315.cfg
deleted file mode 100644
index 92ad376000b150854e257495d395aee8d31747ba..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/atheros_ar2315.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $_CHIPNAME
-} else {
- set _CHIPNAME ar2315
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x00000001
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/atheros_ar9331.cfg b/openocd-0.10.0/scripts/target/atheros_ar9331.cfg
deleted file mode 100644
index c5609bb1d35b2f62aa34caa565b69a4215d7cf71..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/atheros_ar9331.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $_CHIPNAME
-} else {
- set _CHIPNAME ar9331
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x00000001
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/atmega128.cfg b/openocd-0.10.0/scripts/target/atmega128.cfg
deleted file mode 100644
index b8f7d0175d004738f3484f61a5bffc7314601b30..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/atmega128.cfg
+++ /dev/null
@@ -1,40 +0,0 @@
-# for avr
-
- set _CHIPNAME avr
- set _ENDIAN little
-
-# jtag speed
-adapter_khz 4500
-
-reset_config srst_only
-adapter_nsrst_delay 100
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x8970203F
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
-
-#$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
-
-#to use it, script will be like:
-#init
-#adapter_khz 4500
-#reset init
-#verify_ircapture disable
-#
-#halt
-#wait halt
-#poll
-#avr mass_erase 0
-#flash write_image E:/Versaloon/Software/CAMERAPROTOCOLAGENT.hex
-#reset run
-#shutdown
diff --git a/openocd-0.10.0/scripts/target/atsamv.cfg b/openocd-0.10.0/scripts/target/atsamv.cfg
deleted file mode 100644
index b6c48423739f914eedddbc42bb7f35dc5e833ef6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/atsamv.cfg
+++ /dev/null
@@ -1,51 +0,0 @@
-# ATMEL SAMV, SAMS, and SAME chips are Cortex-M7 parts
-# The chips are very similar; the SAMV series just has
-# more peripherals and seems like the "flagship" of the
-# family. This script will work for all of them.
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME samv
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 16kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x4000
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x0bd11477
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-adapter_khz 1800
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
-
diff --git a/openocd-0.10.0/scripts/target/avr32.cfg b/openocd-0.10.0/scripts/target/avr32.cfg
deleted file mode 100644
index f5ee1a4866a21d1e2d22f5e692bb18ce67cfd678..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/avr32.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-set _CHIPNAME avr32
-set _ENDIAN big
-
-set _CPUTAPID 0x21e8203f
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
-reset_config trst_and_srst separate
-
-# jtag scan chain
-# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME avr32_ap7k -endian $_ENDIAN -chain-position $_TARGETNAME
-
diff --git a/openocd-0.10.0/scripts/target/bcm281xx.cfg b/openocd-0.10.0/scripts/target/bcm281xx.cfg
deleted file mode 100644
index 224af793333be0c97d4b89f1aa69a8b13f9da804..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/bcm281xx.cfg
+++ /dev/null
@@ -1,33 +0,0 @@
-# BCM281xx
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME bcm281xx
-}
-
-
-# Main CPU DAP
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x4ba00477
-}
-
-jtag newtap $_CHIPNAME dap -expected-id $_DAP_TAPID -irlen 4
-
-
-# Dual Cortex-A9
-set _TARGETNAME0 $_CHIPNAME.cpu0
-set _TARGETNAME1 $_CHIPNAME.cpu1
-
-target create $_TARGETNAME0 cortex_a -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x3fe10000
-target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap -coreid 1 -dbgbase 0x3fe12000
-target smp $_TARGETNAME0 $_TARGETNAME1
-
-$_TARGETNAME0 configure -event gdb-attach {
- cortex_a dbginit
-}
-$_TARGETNAME1 configure -event gdb-attach {
- cortex_a dbginit
-}
diff --git a/openocd-0.10.0/scripts/target/bcm4706.cfg b/openocd-0.10.0/scripts/target/bcm4706.cfg
deleted file mode 100644
index 10b32c77d4c4153987ac4fc2c9137ae75d04cee2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/bcm4706.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-set _CHIPNAME bcm4706
-set _CPUID 0x1008c17f
-
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/bcm4718.cfg b/openocd-0.10.0/scripts/target/bcm4718.cfg
deleted file mode 100644
index 8193914a368416e406ca66053920d48f7bb11bce..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/bcm4718.cfg
+++ /dev/null
@@ -1,5 +0,0 @@
-set _CHIPNAME bcm4718
-set _LVTAPID 0x1471617f
-set _CPUID 0x0008c17f
-
-source [find target/bcm47xx.cfg]
diff --git a/openocd-0.10.0/scripts/target/bcm47xx.cfg b/openocd-0.10.0/scripts/target/bcm47xx.cfg
deleted file mode 100644
index 0132bb80246659209c3b3f70015e1f7e8d922741..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/bcm47xx.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-echo "Forcing reset_config to none to prevent OpenOCD from pulling SRST after the switch from LV is already performed"
-reset_config none
-
-jtag newtap $_CHIPNAME-lv tap -irlen 32 -ircapture 0x1 -irmask 0x1f -expected-id $_LVTAPID -expected-id $_CPUID
-jtag configure $_CHIPNAME-lv.tap -event setup "jtag tapenable $_CHIPNAME.cpu"
-jtag configure $_CHIPNAME-lv.tap -event tap-disable {}
-
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID -disable
-jtag configure $_CHIPNAME.cpu -event tap-enable "switch_lv_to_ejtag"
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME
-
-proc switch_lv_to_ejtag {} {
- global _CHIPNAME
- poll 0
- irscan $_CHIPNAME-lv.tap 0x143ff3a
- drscan $_CHIPNAME-lv.tap 32 1
- jtag tapdisable $_CHIPNAME-lv.tap
- poll 1
-}
diff --git a/openocd-0.10.0/scripts/target/bcm5352e.cfg b/openocd-0.10.0/scripts/target/bcm5352e.cfg
deleted file mode 100644
index 3f0495a3eacc0119afd5148bc2dc6270f95c6d51..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/bcm5352e.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-set _CHIPNAME bcm5352e
-set _CPUID 0x0535217f
-
-jtag newtap $_CHIPNAME cpu -irlen 8 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/bcm6348.cfg b/openocd-0.10.0/scripts/target/bcm6348.cfg
deleted file mode 100644
index 2540b51afbdb492f78eaed12a62e51c0303a2ee3..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/bcm6348.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-set _CHIPNAME bcm6348
-set _CPUID 0x0634817f
-
-adapter_khz 1000
-
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/c100.cfg b/openocd-0.10.0/scripts/target/c100.cfg
deleted file mode 100644
index 1eaa8fe8a640cb5f07fb9f0d3b8cf7852ce2f54b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/c100.cfg
+++ /dev/null
@@ -1,42 +0,0 @@
-# c100 config.
-# This is ARM1136 dual core
-# this script only configures one core (that is used to run Linux)
-
-# assume no PLL lock, start slowly
-adapter_khz 100
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME c100
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x27b3645b
-}
-
-if { [info exists DSPTAPID] } {
- set _DSPTAPID $DSPTAPID
-} else {
- set _DSPTAPID 0x27b3645b
-}
-
-jtag newtap $_CHIPNAME dsp -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_DSPTAPID
-
-
-# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# C100's ARAM 64k SRAM
-$_TARGETNAME configure -work-area-phys 0x0a000000 -work-area-size 0x10000 -work-area-backup 0
diff --git a/openocd-0.10.0/scripts/target/c100config.tcl b/openocd-0.10.0/scripts/target/c100config.tcl
deleted file mode 100644
index 52efa83c255b575671ae91448a1320adf0ebb331..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/c100config.tcl
+++ /dev/null
@@ -1,412 +0,0 @@
-
-# board(-config) specfic parameters file.
-
-# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
-proc config {label} {
- return [dict get [configC100] $label ]
-}
-
-# show the value for the param. with label
-proc showconfig {label} {
- echo [format "0x%x" [dict get [configC100] $label ]]
-}
-
-# Telo board config
-# when there are more then one board config
-# use soft links to c100board-config.tcl
-# so that only the right board-config gets
-# included (just like include/configs/board-configs.h
-# in u-boot.
-proc configC100 {} {
- # xtal freq. 24MHz
- dict set configC100 CFG_REFCLKFREQ 24000000
-
- # Amba Clk 165MHz
- dict set configC100 CONFIG_SYS_HZ_CLOCK 165000000
- dict set configC100 w_amba 1
- dict set configC100 x_amba 1
- # y = amba_clk * (w+1)*(x+1)*2/xtal_clk
- dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
-
- # Arm Clk 450MHz, must be a multiple of 25 MHz
- dict set configC100 CFG_ARM_CLOCK 450000000
- dict set configC100 w_arm 0
- dict set configC100 x_arm 1
- # y = arm_clk * (w+1)*(x+1)*2/xtal_clk
- dict set configC100 y_arm [expr ([dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
-
-
-}
-
-# This should be called for reset init event handler
-proc setupTelo {} {
-
- # setup GPIO used as control signals for C100
- setupGPIO
- # This will allow acces to lower 8MB or NOR
- lowGPIO5
- # setup NOR size,timing,etc.
- setupNOR
- # setup internals + PLL + DDR2
- initC100
-}
-
-
-proc setupNOR {} {
- echo "Setting up NOR: 16MB, 16-bit wide bus, CS0"
- # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
- set EX_CSEN_REG [regs EX_CSEN_REG ]
- set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
- set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
- set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
- set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
- set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
- set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
- set EX_MFSM_REG [regs EX_MFSM_REG ]
- set EX_CSFSM_REG [regs EX_CSFSM_REG ]
- set EX_WRFSM_REG [regs EX_WRFSM_REG ]
- set EX_RDFSM_REG [regs EX_RDFSM_REG ]
-
- # enable Expansion Bus Clock + CS0 (NOR)
- mww $EX_CSEN_REG 0x3
- # set the address space for CS0=16MB
- mww $EX_CS0_SEG_REG 0x7ff
- # set the CS0 bus width to 16-bit
- mww $EX_CS0_CFG_REG 0x202
- # set timings to NOR
- mww $EX_CS0_TMG1_REG 0x03034006
- mww $EX_CS0_TMG2_REG 0x04040002
- #mww $EX_CS0_TMG3_REG
- # set EBUS clock 165/5=33MHz
- mww $EX_CLOCK_DIV_REG 0x5
- # everthing else is OK with default
-}
-
-proc bootNOR {} {
- set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
- set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
- set DDR_RST [regs DDR_RST]
-
- # put DDR controller in reset (so that it comes reset in u-boot)
- mmw $BLOCK_RESET_REG 0x0 $DDR_RST
- # setup CS0 controller for NOR
- setupNOR
- # make sure we are accessing the lower part of NOR
- lowGPIO5
- # set PC to start of NOR (at boot 0x20000000 = 0x0)
- reg pc $EXP_CS0_BASEADDR
- # run
- resume
-}
-proc setupGPIO {} {
- echo "Setting up GPIO block for Telo"
- # This is current setup for Telo (see sch. for details):
- #GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup
- #GPIO1 irq line for FXS-FXO
- #GPIO5 addr22 for NOR flash (access to upper 8MB)
- #GPIO17 reset for DECT module.
- #GPIO29 CS_n for NAND
-
- set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
- set GPIO_OE_REG [regs GPIO_OE_REG]
-
- # set GPIO29=GPIO17=1, GPIO5=0
- mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17]
- # enable [as output] GPIO29,GPIO17,GPIO5
- mww $GPIO_OE_REG [expr 1<<29 | 1<<17 | 1<<5]
-}
-
-proc highGPIO5 {} {
- echo "GPIO5 high"
- set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
- # set GPIO5=1
- mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
-}
-
-proc lowGPIO5 {} {
- echo "GPIO5 low"
- set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
- # set GPIO5=0
- mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
-}
-
-proc boardID {id} {
- # so far built:
- # 4'b1111
- dict set boardID 15 name "EVT1"
- dict set boardID 15 ddr2size 128M
- # dict set boardID 15 nandsize 1G
- # dict set boardID 15 norsize 16M
- # 4'b0000
- dict set boardID 0 name "EVT2"
- dict set boardID 0 ddr2size 128M
- # 4'b0001
- dict set boardID 1 name "EVT3"
- dict set boardID 1 ddr2size 256M
- # 4'b1110
- dict set boardID 14 name "EVT3_old"
- dict set boardID 14 ddr2size 128M
- # 4'b0010
- dict set boardID 2 name "EVT4"
- dict set boardID 2 ddr2size 256M
-
- return $boardID
-}
-
-
-# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
-# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
-proc ooma_board_detect {} {
- set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
-
- # read the current value of the BOOTSRAP pins
- set tmp [mrw $GPIO_BOOTSTRAP_REG]
- echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
- # extract the GPBP bits
- set gpbt [expr ($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3]
-
- # display board ID
- echo [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
- # show it on serial console
- putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt]
- # return the ddr2 size, used to configure DDR2 on a given board.
- return [dict get [boardID $gpbt] $gpbt ddr2size]
-}
-
-proc configureDDR2regs_256M {} {
-
- set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
- set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
- set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
- set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
- set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
- set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
- set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
- set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
- set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
- set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
- set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
- set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
- set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
- set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
- set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
- set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
- set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
- set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
- set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
- set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
- set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
-
- set DENALI_CTL_02_VAL 0x0100000000010100
- set DENALI_CTL_11_VAL 0x433a32164a560a00
-
- mw64bit $DENALI_CTL_00_DATA 0x0100000101010101
- # 01_DATA mod [40]=1, enable BA2
- mw64bit $DENALI_CTL_01_DATA 0x0100010100000001
- mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL
- mw64bit $DENALI_CTL_03_DATA 0x0102020202020201
- mw64bit $DENALI_CTL_04_DATA 0x0000010100000001
- mw64bit $DENALI_CTL_05_DATA 0x0203010300010101
- mw64bit $DENALI_CTL_06_DATA 0x060a020200020202
- mw64bit $DENALI_CTL_07_DATA 0x0000000300000206
- mw64bit $DENALI_CTL_08_DATA 0x6400003f3f0a0209
- mw64bit $DENALI_CTL_09_DATA 0x1a000000001a1a1a
- mw64bit $DENALI_CTL_10_DATA 0x0120202020191a18
- # 11_DATA mod [39-32]=16,more refresh
- mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL
- mw64bit $DENALI_CTL_12_DATA 0x0000000000000800
- mw64bit $DENALI_CTL_13_DATA 0x0010002000100040
- mw64bit $DENALI_CTL_14_DATA 0x0010004000100040
- mw64bit $DENALI_CTL_15_DATA 0x04f8000000000000
- mw64bit $DENALI_CTL_16_DATA 0x000000002cca0000
- mw64bit $DENALI_CTL_17_DATA 0x0000000000000000
- mw64bit $DENALI_CTL_18_DATA 0x0302000000000000
- mw64bit $DENALI_CTL_19_DATA 0x00001300c8030600
- mw64bit $DENALI_CTL_20_DATA 0x0000000081fe00c8
-
- set wr_dqs_shift 0x40
- # start DDRC
- mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
- # wait int_status[2] (DRAM init complete)
- echo -n "Waiting for DDR2 controller to init..."
- set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
- while { [expr $tmp & 0x040000] == 0 } {
- sleep 1
- set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
- }
- echo "done."
-
- # do ddr2 training sequence
- # TBD (for now, if you need it, run trainDDR command)
-}
-
-# converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()
-# The values are computed based on Mindspeed and Nanya datasheets
-proc configureDDR2regs_128M {} {
-
- set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
- set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
- set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
- set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
- set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
- set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
- set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
- set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
- set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
- set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
- set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
- set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
- set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
- set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
- set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
- set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
- set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
- set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
- set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
- set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
- set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
-
-
- set DENALI_CTL_02_VAL 0x0100010000010100
- set DENALI_CTL_11_VAL 0x433A42124A650A37
- # set some default values
- mw64bit $DENALI_CTL_00_DATA 0x0100000101010101
- mw64bit $DENALI_CTL_01_DATA 0x0100000100000101
- mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL
- mw64bit $DENALI_CTL_03_DATA 0x0102020202020201
- mw64bit $DENALI_CTL_04_DATA 0x0201010100000201
- mw64bit $DENALI_CTL_05_DATA 0x0203010300010101
- mw64bit $DENALI_CTL_06_DATA 0x050A020200020202
- mw64bit $DENALI_CTL_07_DATA 0x000000030E0B0205
- mw64bit $DENALI_CTL_08_DATA 0x6427003F3F0A0209
- mw64bit $DENALI_CTL_09_DATA 0x1A00002F00001A00
- mw64bit $DENALI_CTL_10_DATA 0x01202020201A1A1A
- mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL
- mw64bit $DENALI_CTL_12_DATA 0x0000080000000800
- mw64bit $DENALI_CTL_13_DATA 0x0010002000100040
- mw64bit $DENALI_CTL_14_DATA 0x0010004000100040
- mw64bit $DENALI_CTL_15_DATA 0x0508000000000000
- mw64bit $DENALI_CTL_16_DATA 0x000020472D200000
- mw64bit $DENALI_CTL_17_DATA 0x0000000008000000
- mw64bit $DENALI_CTL_18_DATA 0x0302000000000000
- mw64bit $DENALI_CTL_19_DATA 0x00001400C8030604
- mw64bit $DENALI_CTL_20_DATA 0x00000000823600C8
-
- set wr_dqs_shift 0x40
- # start DDRC
- mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
- # wait int_status[2] (DRAM init complete)
- echo -n "Waiting for DDR2 controller to init..."
- set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
- while { [expr $tmp & 0x040000] == 0 } {
- sleep 1
- set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
- }
- # This is not necessary
- #mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
- echo "done."
-
- # do ddr2 training sequence
- # TBD (for now, if you need it, run trainDDR command)
-}
-
-
-
-proc setupUART0 {} {
- # configure UART0 to 115200, 8N1
- set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
- set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
- set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
- set GPIO_IOCTRL_UART0 [regs GPIO_IOCTRL_UART0]
- set UART0_LCR [regs UART0_LCR]
- set LCR_DLAB [regs LCR_DLAB]
- set UART0_DLL [regs UART0_DLL]
- set UART0_DLH [regs UART0_DLH]
- set UART0_IIR [regs UART0_IIR]
- set UART0_IER [regs UART0_IER]
- set LCR_ONE_STOP [regs LCR_ONE_STOP]
- set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8]
- set FCR_XMITRES [regs FCR_XMITRES]
- set FCR_RCVRRES [regs FCR_RCVRRES]
- set FCR_FIFOEN [regs FCR_FIFOEN]
- set IER_UUE [regs IER_UUE]
-
- # unlock writing to IOCTRL register
- mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
- # enable UART0
- mmw $GPIO_IOCTRL_REG $GPIO_IOCTRL_UART0 0x0
- # baudrate 115200
- # This should really be amba_clk/(16*115200) but amba_clk=165MHz
- set tmp 89
- # Enable Divisor Latch access
- mmw $UART0_LCR $LCR_DLAB 0x0
- # set the divisor to $tmp
- mww $UART0_DLL [expr $tmp & 0xff]
- mww $UART0_DLH [expr $tmp >> 8]
- # Disable Divisor Latch access
- mmw $UART0_LCR 0x0 $LCR_DLAB
- # set the UART to 8N1
- mmw $UART0_LCR [expr $LCR_ONE_STOP | $LCR_CHAR_LEN_8 ] 0x0
- # reset FIFO
- mmw $UART0_IIR [expr $FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN ] 0x0
- # enable FFUART
- mww $UART0_IER $IER_UUE
-}
-
-proc putcUART0 {char} {
-
- set UART0_LSR [regs UART0_LSR]
- set UART0_THR [regs UART0_THR]
- set LSR_TEMT [regs LSR_TEMT]
-
- # convert the 'char' to digit
- set tmp [ scan $char %c ]
- # /* wait for room in the tx FIFO on FFUART */
- while {[expr [mrw $UART0_LSR] & $LSR_TEMT] == 0} { sleep 1 }
- mww $UART0_THR $tmp
- if { $char == "\n" } { putcUART0 \r }
-}
-
-proc putsUART0 {str} {
- set index 0
- set len [string length $str]
- while { $index < $len } {
- putcUART0 [string index $str $index]
- set index [expr $index + 1]
- }
-}
-
-
-proc trainDDR2 {} {
- set ARAM_BASEADDR [regs ARAM_BASEADDR]
-
- # you must have run 'reset init' or u-boot
- # load the training code to ARAM
- load_image ./images/ddr2train.bin $ARAM_BASEADDR bin
- # set PC to start of NOR (at boot 0x20000000 = 0x0)
- reg pc $ARAM_BASEADDR
- # run
- resume
-}
-
-proc flashUBOOT {file} {
- # this will update uboot on NOR partition
- set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
-
- # setup CS0 controller for NOR
- setupNOR
- # make sure we are accessing the lower part of NOR
- lowGPIO5
- flash probe 0
- echo "Erasing sectors 0-3 for uboot"
- putsUART0 "Erasing sectors 0-3 for uboot\n"
- flash erase_sector 0 0 3
- echo "Programming u-boot"
- putsUART0 "Programming u-boot..."
- arm11 memwrite burst enable
- flash write_image $file $EXP_CS0_BASEADDR
- arm11 memwrite burst disable
- putsUART0 "done.\n"
- putsUART0 "Rebooting, please wait!\n"
- reboot
-}
\ No newline at end of file
diff --git a/openocd-0.10.0/scripts/target/c100helper.tcl b/openocd-0.10.0/scripts/target/c100helper.tcl
deleted file mode 100644
index c9124cbc637c21f4586cd141095ccc9f6caa0212..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/c100helper.tcl
+++ /dev/null
@@ -1,506 +0,0 @@
-
-proc helpC100 {} {
- echo "List of useful functions for C100 processor:"
- echo "1) reset init: will set up your Telo board"
- echo "2) setupNOR: will setup NOR access"
- echo "3) showNOR: will show current NOR config registers for 16-bit, 16MB NOR"
- echo "4) setupGPIO: will setup GPIOs for Telo board"
- echo "5) showGPIO: will show current GPIO config registers"
- echo "6) highGPIO5: will set GPIO5=NOR_addr22=1 to access upper 8MB"
- echo "7) lowGPIO5: will set GPIO5=NOR_addr22=0 to access lower 8MB"
- echo "8) showAmbaClk: will show current config registers for Amba Bus Clock"
- echo "9) setupAmbaClk: will setup Amba Bus Clock=165MHz"
- echo "10) showArmClk: will show current config registers for Arm Bus Clock"
- echo "11) setupArmClk: will setup Amba Bus Clock=450MHz"
- echo "12) ooma_board_detect: will show which version of Telo you have"
- echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg"
- echo "14) showDDR2: will show DDR2 config registers"
- echo "15) showWatchdog: will show current regster config for watchdog"
- echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
- echo "17) bootNOR: will boot Telo from NOR"
- echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured"
- echo "19) putcUART0: will print a character on UART0"
- echo "20) putsUART0: will print a string on UART0"
- echo "21) trainDDR2: will run DDR2 training program"
- echo "22) flashUBOOT: will prgram NOR sectors 0-3 with u-boot.bin"
-}
-
-source [find mem_helper.tcl]
-
-# read a 64-bit register (memory mapped)
-proc mr64bit {reg} {
- set value ""
- mem2array value 32 $reg 2
- return $value
-}
-
-
-# write a 64-bit register (memory mapped)
-proc mw64bit {reg value} {
- set high [expr $value >> 32]
- set low [expr $value & 0xffffffff]
- #echo [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low]
- mww $reg $low
- mww [expr $reg+4] $high
-}
-
-
-proc showNOR {} {
- echo "This is the current NOR setup"
- set EX_CSEN_REG [regs EX_CSEN_REG ]
- set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
- set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
- set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
- set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
- set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
- set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
- set EX_MFSM_REG [regs EX_MFSM_REG ]
- set EX_CSFSM_REG [regs EX_CSFSM_REG ]
- set EX_WRFSM_REG [regs EX_WRFSM_REG ]
- set EX_RDFSM_REG [regs EX_RDFSM_REG ]
-
- echo [format "EX_CSEN_REG (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]
- echo [format "EX_CS0_SEG_REG (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]
- echo [format "EX_CS0_CFG_REG (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]]
- echo [format "EX_CS0_TMG1_REG (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]]
- echo [format "EX_CS0_TMG2_REG (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]]
- echo [format "EX_CS0_TMG3_REG (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]]
- echo [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]]
- echo [format "EX_MFSM_REG (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]]
- echo [format "EX_CSFSM_REG (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]]
- echo [format "EX_WRFSM_REG (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]]
- echo [format "EX_RDFSM_REG (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]]
-}
-
-
-
-proc showGPIO {} {
- echo "This is the current GPIO register setup"
- # GPIO outputs register
- set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
- # GPIO Output Enable register
- set GPIO_OE_REG [regs GPIO_OE_REG]
- set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG]
- set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG]
- # GPIO input register
- set GPIO_INPUT_REG [regs GPIO_INPUT_REG]
- set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
- set MUX_CONF_REG [regs MUX_CONF_REG]
- set SYSCONF_REG [regs SYSCONF_REG]
- set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG]
- set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
- set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
- set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
- set GPIO_DEVID_REG [regs GPIO_DEVID_REG]
-
- echo [format "GPIO_OUTPUT_REG (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]
- echo [format "GPIO_OE_REG (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]
- echo [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]]
- echo [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]]
- echo [format "GPIO_INPUT_REG (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]]
- echo [format "APB_ACCESS_WS_REG (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]]
- echo [format "MUX_CONF_REG (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]]
- echo [format "SYSCONF_REG (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]]
- echo [format "GPIO_ARM_ID_REG (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]]
- echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]]
- echo [format "GPIO_LOCK_REG (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]]
- echo [format "GPIO_IOCTRL_REG (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]]
- echo [format "GPIO_DEVID_REG (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]]
-}
-
-
-
-# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk())
-proc showAmbaClk {} {
- set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
- set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
- set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
-
- echo [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
- mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
- # see if the PLL is in bypass mode
- set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
- echo [format "PLL bypass bit: %d" $bypass]
- if {$bypass == 1} {
- echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
- } else {
- # nope, extract x,y,w and compute the PLL output freq.
- set x [expr ($value(0) & 0x0001F0000) >> 16]
- echo [format "x: %d" $x]
- set y [expr ($value(0) & 0x00000007F)]
- echo [format "y: %d" $y]
- set w [expr ($value(0) & 0x000000300) >> 8]
- echo [format "w: %d" $w]
- echo [format "Amba PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
- }
-}
-
-
-# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())
-# this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)
-proc setupAmbaClk {} {
- set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
- set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
- set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
- set ARM_AHB_BYP [regs ARM_AHB_BYP]
- set PLL_DISABLE [regs PLL_DISABLE]
- set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
- set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
- set DIV_BYPASS [regs DIV_BYPASS]
- set AHBCLK_PLL_LOCK [regs AHBCLK_PLL_LOCK]
- set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
- set CONFIG_SYS_HZ_CLOCK [config CONFIG_SYS_HZ_CLOCK]
- set w [config w_amba]
- set x [config x_amba]
- set y [config y_amba]
-
- echo [format "Setting Amba PLL to lock to %d MHz" [expr $CONFIG_SYS_HZ_CLOCK/1000000]]
- #echo [format "setupAmbaClk: w= %d" $w]
- #echo [format "setupAmbaClk: x= %d" $x]
- #echo [format "setupAmbaClk: y= %d" $y]
- # set PLL into BYPASS mode using MUX
- mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0
- # do an internal PLL bypass
- mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0
- # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
- # openocd smallest resolution is 1ms so, wait 1ms
- sleep 1
- # disable the PLL
- mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0
- # wait 1ms
- sleep 1
- # enable the PLL
- mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE
- sleep 1
- # set X, W and X
- mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
- mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
- # wait for PLL to lock
- echo "Wating for Amba PLL to lock"
- while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
- # remove the internal PLL bypass
- mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
- # remove PLL from BYPASS mode using MUX
- mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
-}
-
-
-# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk())
-proc showArmClk {} {
- set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
- set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
- set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
-
- echo [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
- mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
- # see if the PLL is in bypass mode
- set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
- echo [format "PLL bypass bit: %d" $bypass]
- if {$bypass == 1} {
- echo [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
- } else {
- # nope, extract x,y,w and compute the PLL output freq.
- set x [expr ($value(0) & 0x0001F0000) >> 16]
- echo [format "x: %d" $x]
- set y [expr ($value(0) & 0x00000007F)]
- echo [format "y: %d" $y]
- set w [expr ($value(0) & 0x000000300) >> 8]
- echo [format "w: %d" $w]
- echo [format "Arm PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
- }
-}
-
-# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk())
-# Arm Clock is used by two ARM1136 cores
-proc setupArmClk {} {
- set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
- set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
- set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
- set ARM_AHB_BYP [regs ARM_AHB_BYP]
- set PLL_DISABLE [regs PLL_DISABLE]
- set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
- set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
- set DIV_BYPASS [regs DIV_BYPASS]
- set FCLK_PLL_LOCK [regs FCLK_PLL_LOCK]
- set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
- set CFG_ARM_CLOCK [config CFG_ARM_CLOCK]
- set w [config w_arm]
- set x [config x_arm]
- set y [config y_arm]
-
- echo [format "Setting Arm PLL to lock to %d MHz" [expr $CFG_ARM_CLOCK/1000000]]
- #echo [format "setupArmClk: w= %d" $w]
- #echo [format "setupArmaClk: x= %d" $x]
- #echo [format "setupArmaClk: y= %d" $y]
- # set PLL into BYPASS mode using MUX
- mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0
- # do an internal PLL bypass
- mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0
- # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
- # openocd smallest resolution is 1ms so, wait 1ms
- sleep 1
- # disable the PLL
- mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0
- # wait 1ms
- sleep 1
- # enable the PLL
- mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE
- sleep 1
- # set X, W and X
- mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
- mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
- # wait for PLL to lock
- echo "Wating for Amba PLL to lock"
- while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
- # remove the internal PLL bypass
- mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
- # remove PLL from BYPASS mode using MUX
- mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
-}
-
-
-
-proc setupPLL {} {
- echo "PLLs setup"
- setupAmbaClk
- setupArmClk
-}
-
-# converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init()
-proc setupDDR2 {} {
- echo "Configuring DDR2"
-
- set MEMORY_BASE_ADDR [regs MEMORY_BASE_ADDR]
- set MEMORY_MAX_ADDR [regs MEMORY_MAX_ADDR]
- set MEMORY_CR [regs MEMORY_CR]
- set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
- set DDR_RST [regs DDR_RST]
-
- # put DDR controller in reset (so that it is reset and correctly configured)
- # this is only necessary if DDR was previously confiured
- # and not reset.
- mmw $BLOCK_RESET_REG 0x0 $DDR_RST
-
- set M [expr 1024 * 1024]
- set DDR_SZ_1024M [expr 1024 * $M]
- set DDR_SZ_256M [expr 256 * $M]
- set DDR_SZ_128M [expr 128 * $M]
- set DDR_SZ_64M [expr 64 * $M]
- # ooma_board_detect returns DDR2 memory size
- set tmp [ooma_board_detect]
- if {$tmp == "128M"} {
- echo "DDR2 size 128MB"
- set ddr_size $DDR_SZ_128M
- } elseif {$tmp == "256M"} {
- echo "DDR2 size 256MB"
- set ddr_size $DDR_SZ_256M
- } else {
- echo "Don't know how to handle this DDR2 size?"
- }
-
- # Memory setup register
- mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]
- # disbale ROM remap
- mww $MEMORY_CR 0x0
- # Take DDR controller out of reset
- mmw $BLOCK_RESET_REG $DDR_RST 0x0
- # min. 20 ops delay
- sleep 1
-
- # This will setup Denali DDR2 controller
- if {$tmp == "128M"} {
- configureDDR2regs_128M
- } elseif {$tmp == "256M"} {
- configureDDR2regs_256M
- } else {
- echo "Don't know how to configure DDR2 setup?"
- }
-}
-
-
-
-proc showDDR2 {} {
-
- set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
- set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
- set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
- set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
- set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
- set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
- set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
- set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
- set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
- set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
- set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
- set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
- set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
- set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
- set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
- set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
- set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
- set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
- set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
- set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
- set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
-
- set tmp [mr64bit $DENALI_CTL_00_DATA]
- echo [format "DENALI_CTL_00_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_01_DATA]
- echo [format "DENALI_CTL_01_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_02_DATA]
- echo [format "DENALI_CTL_02_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_03_DATA]
- echo [format "DENALI_CTL_03_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_04_DATA]
- echo [format "DENALI_CTL_04_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_05_DATA]
- echo [format "DENALI_CTL_05_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_06_DATA]
- echo [format "DENALI_CTL_06_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_07_DATA]
- echo [format "DENALI_CTL_07_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_08_DATA]
- echo [format "DENALI_CTL_08_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_09_DATA]
- echo [format "DENALI_CTL_09_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_10_DATA]
- echo [format "DENALI_CTL_10_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_11_DATA]
- echo [format "DENALI_CTL_11_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_12_DATA]
- echo [format "DENALI_CTL_12_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_13_DATA]
- echo [format "DENALI_CTL_13_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_14_DATA]
- echo [format "DENALI_CTL_14_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_15_DATA]
- echo [format "DENALI_CTL_15_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_16_DATA]
- echo [format "DENALI_CTL_16_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_17_DATA]
- echo [format "DENALI_CTL_17_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_18_DATA]
- echo [format "DENALI_CTL_18_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_19_DATA]
- echo [format "DENALI_CTL_19_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)]
- set tmp [mr64bit $DENALI_CTL_20_DATA]
- echo [format "DENALI_CTL_20_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)]
-
-}
-
-proc initC100 {} {
- # this follows u-boot/cpu/arm1136/start.S
- set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
- set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
- set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
- set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
- set ASA_ARAM_BASEADDR [regs ASA_ARAM_BASEADDR]
- set ASA_ARAM_TC_CR_REG [regs ASA_ARAM_TC_CR_REG]
- set ASA_EBUS_BASEADDR [regs ASA_EBUS_BASEADDR]
- set ASA_EBUS_TC_CR_REG [regs ASA_EBUS_TC_CR_REG]
- set ASA_TC_REQIDMAEN [regs ASA_TC_REQIDMAEN]
- set ASA_TC_REQTDMEN [regs ASA_TC_REQTDMEN]
- set ASA_TC_REQIPSECUSBEN [regs ASA_TC_REQIPSECUSBEN]
- set ASA_TC_REQARM0EN [regs ASA_TC_REQARM0EN]
- set ASA_TC_REQARM1EN [regs ASA_TC_REQARM1EN]
- set ASA_TC_REQMDMAEN [regs ASA_TC_REQMDMAEN]
- set INTC_ARM1_CONTROL_REG [regs INTC_ARM1_CONTROL_REG]
-
-
- # unlock writing to IOCTRL register
- mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
- # enable address lines A15-A21
- mmw $GPIO_IOCTRL_REG 0xf 0x0
- # set ARM into supervisor mode (SVC32)
- # disable IRQ, FIQ
- # Do I need this in JTAG mode?
- # it really should be done as 'and ~0x1f | 0xd3 but
- # openocd does not support this yet
- reg cpsr 0xd3
- # /*
- # * flush v4 I/D caches
- # */
- # mov r0, #0
- # mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- arm mcr 15 0 7 7 0 0x0
- # mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
- arm mcr 15 0 8 7 0 0x0
-
- # /*
- # * disable MMU stuff and caches
- # */
- # mrc p15, 0, r0, c1, c0, 0
- arm mrc 15 0 1 0 0
- # bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
- # bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
- # orr r0, r0, #0x00000002 @ set bit 2 (A) Align
- # orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
- # orr r0, r0, #0x00400000 @ set bit 22 (U)
- # mcr p15, 0, r0, c1, c0, 0
- arm mcr 15 0 1 0 0 0x401002
- # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
- # APB init
- # // Setting APB Bus Wait states to 1, set post write
- # (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
- mww [expr $APB_ACCESS_WS_REG] 0x40
- # AHB init
- # // enable all 6 masters for ARAM
- mmw $ASA_ARAM_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
- # // enable all 6 masters for EBUS
- mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
-
- # ARAM init
- # // disable pipeline mode in ARAM
- # I don't think this is documented anywhere?
- mww $INTC_ARM1_CONTROL_REG 0x1
- # configure clocks
- setupPLL
- # setupUART0 must be run before setupDDR2 as setupDDR2 uses UART.
- setupUART0
- # enable cache
- # ? (u-boot does nothing here)
- # DDR2 memory init
- setupDDR2
- putsUART0 "C100 initialization complete.\n"
- echo "C100 initialization complete."
-}
-
-# show current state of watchdog timer
-proc showWatchdog {} {
- set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
- set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
- set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
-
- echo [format "TIMER_WDT_HIGH_BOUND (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]]
- echo [format "TIMER_WDT_CONTROL (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]]
- echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
-}
-
-# converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored)
-# this will trigger watchdog reset
-# the sw. reset does not work on C100
-# watchdog reset effectively works as hw. reset
-proc reboot {} {
- set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
- set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
- set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
-
- # allow the counter to count to high value before triggering
- # this is because regsiter writes are slow over JTAG and
- # I don't want to miss the high_bound==curr_count condition
- mww $TIMER_WDT_HIGH_BOUND 0xffffff
- mww $TIMER_WDT_CURRENT_COUNT 0x0
- echo "JTAG speed lowered to 100kHz"
- adapter_khz 100
- mww $TIMER_WDT_CONTROL 0x1
- # wait until the reset
- echo -n "Wating for watchdog to trigger..."
- #while {[mrw $TIMER_WDT_CONTROL] == 1} {
- # echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
- # sleep 1
- #
- #}
- while {[c100.cpu curstate] != "running"} { sleep 1}
- echo "done."
- echo [format "Note that C100 is in %s state, type halt to stop" [c100.cpu curstate]]
-}
diff --git a/openocd-0.10.0/scripts/target/c100regs.tcl b/openocd-0.10.0/scripts/target/c100regs.tcl
deleted file mode 100644
index a2c7a60d0539b385752447f682dd7b91f20a5c50..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/c100regs.tcl
+++ /dev/null
@@ -1,493 +0,0 @@
-# Note that I basically converted
-# u-boot/include/asm-arm/arch/comcerto_100.h
-# defines
-
-# this is a work-around for 'global' not working under Linux
-# access registers by calling this routine.
-# For example:
-# set EX_CS_TMG1_REG [regs EX_CS0_TMG1_REG]
-proc regs {reg} {
- return [dict get [regsC100] $reg ]
-}
-
-proc showreg {reg} {
- echo [format "0x%x" [dict get [regsC100] $reg ]]
-}
-
-proc regsC100 {} {
-#/* memcore */
-#/* device memory base addresses */
-#// device memory sizes
-#/* ARAM SIZE=64K */
-dict set regsC100 ARAM_SIZE 0x00010000
-dict set regsC100 ARAM_BASEADDR 0x0A000000
-
-#/* Hardware Interface Units */
-dict set regsC100 APB_BASEADDR 0x10000000
-#/* APB_SIZE=16M address range */
-dict set regsC100 APB_SIZE 0x01000000
-
-dict set regsC100 EXP_CS0_BASEADDR 0x20000000
-dict set regsC100 EXP_CS1_BASEADDR 0x24000000
-dict set regsC100 EXP_CS2_BASEADDR 0x28000000
-dict set regsC100 EXP_CS3_BASEADDR 0x2C000000
-dict set regsC100 EXP_CS4_BASEADDR 0x30000000
-
-dict set regsC100 DDR_BASEADDR 0x80000000
-
-dict set regsC100 TDM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x000000]
-dict set regsC100 PHI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x010000]
-dict set regsC100 TDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x020000]
-dict set regsC100 ASA_DDR_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x040000]
-dict set regsC100 ASA_ARAM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x048000]
-dict set regsC100 TIMER_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x050000]
-dict set regsC100 ASD_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x060000]
-dict set regsC100 GPIO_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x070000]
-dict set regsC100 UART0_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x090000]
-dict set regsC100 UART1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x094000]
-dict set regsC100 SPI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x098000]
-dict set regsC100 I2C_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x09C000]
-dict set regsC100 INTC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0A0000]
-dict set regsC100 CLKCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000]
-dict set regsC100 PUI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000]
-dict set regsC100 GEMAC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0D0000]
-dict set regsC100 IDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0E0000]
-dict set regsC100 MEMCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0F0000]
-dict set regsC100 ASA_EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x100000]
-dict set regsC100 ASA_AAB_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x108000]
-dict set regsC100 GEMAC1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x190000]
-dict set regsC100 EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1A0000]
-dict set regsC100 MDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1E0000]
-
-
-#////////////////////////////////////////////////////////////
-#// AHB block //
-#////////////////////////////////////////////////////////////
-dict set regsC100 ASA_ARAM_PRI_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00]
-dict set regsC100 ASA_ARAM_TC_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04]
-dict set regsC100 ASA_ARAM_TC_CR_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08]
-dict set regsC100 ASA_ARAM_STAT_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C]
-
-dict set regsC100 ASA_EBUS_PRI_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00]
-dict set regsC100 ASA_EBUS_TC_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04]
-dict set regsC100 ASA_EBUS_TC_CR_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08]
-dict set regsC100 ASA_EBUS_STAT_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C]
-
-dict set regsC100 IDMA_MASTER 0
-dict set regsC100 TDMA_MASTER 1
-dict set regsC100 USBIPSEC_MASTER 2
-dict set regsC100 ARM0_MASTER 3
-dict set regsC100 ARM1_MASTER 4
-dict set regsC100 MDMA_MASTER 5
-
-#define IDMA_PRIORITY(level) (level)
-#define TDM_PRIORITY(level) (level << 4)
-#define USBIPSEC_PRIORITY(level) (level << 8)
-#define ARM0_PRIORITY(level) (level << 12)
-#define ARM1_PRIORITY(level) (level << 16)
-#define MDMA_PRIORITY(level) (level << 20)
-
-dict set regsC100 ASA_TC_REQIDMAEN [expr 1<<18]
-dict set regsC100 ASA_TC_REQTDMEN [expr 1<<19]
-dict set regsC100 ASA_TC_REQIPSECUSBEN [expr 1<<20]
-dict set regsC100 ASA_TC_REQARM0EN [expr 1<<21]
-dict set regsC100 ASA_TC_REQARM1EN [expr 1<<22]
-dict set regsC100 ASA_TC_REQMDMAEN [expr 1<<23]
-
-dict set regsC100 MEMORY_BASE_ADDR 0x80000000
-dict set regsC100 MEMORY_MAX_ADDR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x10]
-dict set regsC100 MEMORY_CR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x14]
-dict set regsC100 ROM_REMAP_EN 0x1
-
-#define HAL_asb_priority(level) \
-#*(volatile unsigned *)ASA_PRI_REG = level
-
-#define HAL_aram_priority(level) \
-#*(volatile unsigned *)ASA_ARAM_PRI_REG = level
-
-#define HAL_aram_arbitration(arbitration_mask) \
-#*(volatile unsigned *)ASA_ARAM_TC_CR_REG |= arbitration_mask
-
-#define HAL_aram_defmaster(mask) \
-#*(volatile unsigned *)ASA_ARAM_TC_CR_REG = (*(volatile unsigned *)ASA_TC_CR_REG & 0xFFFF) | (mask << 24)
-
-#////////////////////////////////////////////////////////////
-#// INTC block //
-#////////////////////////////////////////////////////////////
-
-dict set regsC100 INTC_ARM1_CONTROL_REG [expr [dict get $regsC100 INTC_BASEADDR ] + 0x18]
-
-#////////////////////////////////////////////////////////////
-#// TIMER block //
-#////////////////////////////////////////////////////////////
-
-dict set regsC100 TIMER0_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x00]
-dict set regsC100 TIMER0_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x04]
-dict set regsC100 TIMER1_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x08]
-dict set regsC100 TIMER1_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x0C]
-
-dict set regsC100 TIMER2_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x18]
-dict set regsC100 TIMER2_LBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x10]
-dict set regsC100 TIMER2_HBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x14]
-dict set regsC100 TIMER2_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x1C]
-
-dict set regsC100 TIMER3_LOBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x20]
-dict set regsC100 TIMER3_HIBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x24]
-dict set regsC100 TIMER3_CTRL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x28]
-dict set regsC100 TIMER3_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x2C]
-
-dict set regsC100 TIMER_MASK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x40]
-dict set regsC100 TIMER_STATUS [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50]
-dict set regsC100 TIMER_ACK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50]
-dict set regsC100 TIMER_WDT_HIGH_BOUND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD0]
-dict set regsC100 TIMER_WDT_CONTROL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD4]
-dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD8]
-
-
-
-#////////////////////////////////////////////////////////////
-#// EBUS block
-#////////////////////////////////////////////////////////////
-
-dict set regsC100 EX_SWRST_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x00]
-dict set regsC100 EX_CSEN_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x04]
-dict set regsC100 EX_CS0_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x08]
-dict set regsC100 EX_CS1_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x0C]
-dict set regsC100 EX_CS2_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x10]
-dict set regsC100 EX_CS3_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x14]
-dict set regsC100 EX_CS4_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x18]
-dict set regsC100 EX_CS0_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x1C]
-dict set regsC100 EX_CS1_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x20]
-dict set regsC100 EX_CS2_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x24]
-dict set regsC100 EX_CS3_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x28]
-dict set regsC100 EX_CS4_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x2C]
-dict set regsC100 EX_CS0_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x30]
-dict set regsC100 EX_CS1_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x34]
-dict set regsC100 EX_CS2_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x38]
-dict set regsC100 EX_CS3_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x3C]
-dict set regsC100 EX_CS4_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x40]
-dict set regsC100 EX_CS0_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x44]
-dict set regsC100 EX_CS1_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x48]
-dict set regsC100 EX_CS2_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x4C]
-dict set regsC100 EX_CS3_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x50]
-dict set regsC100 EX_CS4_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x54]
-dict set regsC100 EX_CS0_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x58]
-dict set regsC100 EX_CS1_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x5C]
-dict set regsC100 EX_CS2_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x60]
-dict set regsC100 EX_CS3_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x64]
-dict set regsC100 EX_CS4_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x68]
-dict set regsC100 EX_CLOCK_DIV_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x6C]
-
-dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100]
-dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100]
-dict set regsC100 EX_CSFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x104]
-dict set regsC100 EX_WRFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x108]
-dict set regsC100 EX_RDFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x10C]
-
-
-dict set regsC100 EX_CLK_EN 0x00000001
-dict set regsC100 EX_CSBOOT_EN 0x00000002
-dict set regsC100 EX_CS0_EN 0x00000002
-dict set regsC100 EX_CS1_EN 0x00000004
-dict set regsC100 EX_CS2_EN 0x00000008
-dict set regsC100 EX_CS3_EN 0x00000010
-dict set regsC100 EX_CS4_EN 0x00000020
-
-dict set regsC100 EX_MEM_BUS_8 0x00000000
-dict set regsC100 EX_MEM_BUS_16 0x00000002
-dict set regsC100 EX_MEM_BUS_32 0x00000004
-dict set regsC100 EX_CS_HIGH 0x00000008
-dict set regsC100 EX_WE_HIGH 0x00000010
-dict set regsC100 EX_RE_HIGH 0x00000020
-dict set regsC100 EX_ALE_MODE 0x00000040
-dict set regsC100 EX_STRB_MODE 0x00000080
-dict set regsC100 EX_DM_MODE 0x00000100
-dict set regsC100 EX_NAND_MODE 0x00000200
-dict set regsC100 EX_RDY_EN 0x00000400
-dict set regsC100 EX_RDY_EDGE 0x00000800
-
-#////////////////////////////////////////////////////////////
-#// GPIO block
-#////////////////////////////////////////////////////////////
-
-# GPIO outputs register
-dict set regsC100 GPIO_OUTPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x00]
-# GPIO Output Enable register
-dict set regsC100 GPIO_OE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x04]
-dict set regsC100 GPIO_HI_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x08]
-dict set regsC100 GPIO_LO_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x0C]
-# GPIO input register
-dict set regsC100 GPIO_INPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x10]
-dict set regsC100 APB_ACCESS_WS_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x14]
-dict set regsC100 MUX_CONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x18]
-dict set regsC100 SYSCONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x1C]
-dict set regsC100 GPIO_ARM_ID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x30]
-dict set regsC100 GPIO_BOOTSTRAP_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x40]
-dict set regsC100 GPIO_LOCK_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x38]
-dict set regsC100 GPIO_IOCTRL_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x44]
-dict set regsC100 GPIO_DEVID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x50]
-
-dict set regsC100 GPIO_IOCTRL_A15A16 0x00000001
-dict set regsC100 GPIO_IOCTRL_A17A18 0x00000002
-dict set regsC100 GPIO_IOCTRL_A19A21 0x00000004
-dict set regsC100 GPIO_IOCTRL_TMREVT0 0x00000008
-dict set regsC100 GPIO_IOCTRL_TMREVT1 0x00000010
-dict set regsC100 GPIO_IOCTRL_GPBT3 0x00000020
-dict set regsC100 GPIO_IOCTRL_I2C 0x00000040
-dict set regsC100 GPIO_IOCTRL_UART0 0x00000080
-dict set regsC100 GPIO_IOCTRL_UART1 0x00000100
-dict set regsC100 GPIO_IOCTRL_SPI 0x00000200
-dict set regsC100 GPIO_IOCTRL_HBMODE 0x00000400
-
-dict set regsC100 GPIO_IOCTRL_VAL 0x55555555
-
-dict set regsC100 GPIO_0 0x01
-dict set regsC100 GPIO_1 0x02
-dict set regsC100 GPIO_2 0x04
-dict set regsC100 GPIO_3 0x08
-dict set regsC100 GPIO_4 0x10
-dict set regsC100 GPIO_5 0x20
-dict set regsC100 GPIO_6 0x40
-dict set regsC100 GPIO_7 0x80
-
-dict set regsC100 GPIO_RISING_EDGE 1
-dict set regsC100 GPIO_FALLING_EDGE 2
-dict set regsC100 GPIO_BOTH_EDGES 3
-
-#////////////////////////////////////////////////////////////
-#// UART
-#////////////////////////////////////////////////////////////
-
-dict set regsC100 UART0_RBR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
-dict set regsC100 UART0_THR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
-dict set regsC100 UART0_DLL [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
-dict set regsC100 UART0_IER [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04]
-dict set regsC100 UART0_DLH [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04]
-dict set regsC100 UART0_IIR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08]
-dict set regsC100 UART0_FCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08]
-dict set regsC100 UART0_LCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x0C]
-dict set regsC100 UART0_MCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x10]
-dict set regsC100 UART0_LSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x14]
-dict set regsC100 UART0_MSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x18]
-dict set regsC100 UART0_SCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x1C]
-
-dict set regsC100 UART1_RBR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
-dict set regsC100 UART1_THR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
-dict set regsC100 UART1_DLL [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
-dict set regsC100 UART1_IER [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04]
-dict set regsC100 UART1_DLH [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04]
-dict set regsC100 UART1_IIR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08]
-dict set regsC100 UART1_FCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08]
-dict set regsC100 UART1_LCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x0C]
-dict set regsC100 UART1_MCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x10]
-dict set regsC100 UART1_LSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x14]
-dict set regsC100 UART1_MSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x18]
-dict set regsC100 UART1_SCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x1C]
-
-# /* default */
-dict set regsC100 LCR_CHAR_LEN_5 0x00
-dict set regsC100 LCR_CHAR_LEN_6 0x01
-dict set regsC100 LCR_CHAR_LEN_7 0x02
-dict set regsC100 LCR_CHAR_LEN_8 0x03
-#/* One stop bit! - default */
-dict set regsC100 LCR_ONE_STOP 0x00
-#/* Two stop bit! */
-dict set regsC100 LCR_TWO_STOP 0x04
-#/* Parity Enable */
-dict set regsC100 LCR_PEN 0x08
-dict set regsC100 LCR_PARITY_NONE 0x00
-#/* Even Parity Select */
-dict set regsC100 LCR_EPS 0x10
-#/* Enable Parity Stuff */
-dict set regsC100 LCR_PS 0x20
-#/* Start Break */
-dict set regsC100 LCR_SBRK 0x40
-#/* Parity Stuff Bit */
-dict set regsC100 LCR_PSB 0x80
-#/* UART 16550 Divisor Latch Assess */
-dict set regsC100 LCR_DLAB 0x80
-
-#/* FIFO Error Status */
-dict set regsC100 LSR_FIFOE [expr 1 << 7]
-#/* Transmitter Empty */
-dict set regsC100 LSR_TEMT [expr 1 << 6]
-#/* Transmit Data Request */
-dict set regsC100 LSR_TDRQ [expr 1 << 5]
-#/* Break Interrupt */
-dict set regsC100 LSR_BI [expr 1 << 4]
-#/* Framing Error */
-dict set regsC100 LSR_FE [expr 1 << 3]
-#/* Parity Error */
-dict set regsC100 LSR_PE [expr 1 << 2]
-#/* Overrun Error */
-dict set regsC100 LSR_OE [expr 1 << 1]
-#/* Data Ready */
-dict set regsC100 LSR_DR [expr 1 << 0]
-
-#/* DMA Requests Enable */
-dict set regsC100 IER_DMAE [expr 1 << 7]
-#/* UART Unit Enable */
-dict set regsC100 IER_UUE [expr 1 << 6]
-#/* NRZ coding Enable */
-dict set regsC100 IER_NRZE [expr 1 << 5]
-#/* Receiver Time Out Interrupt Enable */
-dict set regsC100 IER_RTIOE [expr 1 << 4]
-#/* Modem Interrupt Enable */
-dict set regsC100 IER_MIE [expr 1 << 3]
-#/* Receiver Line Status Interrupt Enable */
-dict set regsC100 IER_RLSE [expr 1 << 2]
-#/* Transmit Data request Interrupt Enable */
-dict set regsC100 IER_TIE [expr 1 << 1]
-#/* Receiver Data Available Interrupt Enable */
-dict set regsC100 IER_RAVIE [expr 1 << 0]
-
-#/* FIFO Mode Enable Status */
-dict set regsC100 IIR_FIFOES1 [expr 1 << 7]
-#/* FIFO Mode Enable Status */
-dict set regsC100 IIR_FIFOES0 [expr 1 << 6]
-#/* Time Out Detected */
-dict set regsC100 IIR_TOD [expr 1 << 3]
-#/* Interrupt Source Encoded */
-dict set regsC100 IIR_IID2 [expr 1 << 2]
-#/* Interrupt Source Encoded */
-dict set regsC100 IIR_IID1 [expr 1 << 1]
-#/* Interrupt Pending (active low) */
-dict set regsC100 IIR_IP [expr 1 << 0]
-
-#/* UART 16550 FIFO Control Register */
-dict set regsC100 FCR_FIFOEN 0x01
-dict set regsC100 FCR_RCVRRES 0x02
-dict set regsC100 FCR_XMITRES 0x04
-
-#/* Interrupt Enable Register */
-#// UART 16550
-#// Enable Received Data Available Interrupt
-dict set regsC100 IER_RXTH 0x01
-#// Enable Transmitter Empty Interrupt
-dict set regsC100 IER_TXTH 0x02
-
-
-
-#////////////////////////////////////////////////////////////
-#// CLK + RESET block
-#////////////////////////////////////////////////////////////
-
-dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x00]
-dict set regsC100 CLKCORE_AHB_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x04]
-dict set regsC100 CLKCORE_PLL_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x08]
-dict set regsC100 CLKCORE_CLKDIV_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C]
-dict set regsC100 CLKCORE_TDM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x10]
-dict set regsC100 CLKCORE_FSYNC_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x14]
-dict set regsC100 CLKCORE_CLK_PWR_DWN [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x18]
-dict set regsC100 CLKCORE_RNG_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C]
-dict set regsC100 CLKCORE_RNG_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x20]
-dict set regsC100 CLKCORE_ARM_CLK_CNTRL2 [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x24]
-dict set regsC100 CLKCORE_TDM_REF_DIV_RST [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x40]
-
-dict set regsC100 ARM_PLL_BY_CTRL 0x80000000
-dict set regsC100 ARM_AHB_BYP 0x04000000
-dict set regsC100 PLL_DISABLE 0x02000000
-dict set regsC100 PLL_CLK_BYPASS 0x01000000
-
-dict set regsC100 AHB_PLL_BY_CTRL 0x80000000
-dict set regsC100 DIV_BYPASS 0x40000000
-dict set regsC100 SYNC_MODE 0x20000000
-
-dict set regsC100 EPHY_CLKDIV_BYPASS 0x00200000
-dict set regsC100 EPHY_CLKDIV_RATIO_SHIFT 16
-dict set regsC100 PUI_CLKDIV_BYPASS 0x00004000
-dict set regsC100 PUI_CLKDIV_SRCCLK 0x00002000
-dict set regsC100 PUI_CLKDIV_RATIO_SHIFT 8
-dict set regsC100 PCI_CLKDIV_BYPASS 0x00000020
-dict set regsC100 PCI_CLKDIV_RATIO_SHIFT 0
-
-dict set regsC100 ARM0_CLK_PD 0x00200000
-dict set regsC100 ARM1_CLK_PD 0x00100000
-dict set regsC100 EPHY_CLK_PD 0x00080000
-dict set regsC100 TDM_CLK_PD 0x00040000
-dict set regsC100 PUI_CLK_PD 0x00020000
-dict set regsC100 PCI_CLK_PD 0x00010000
-dict set regsC100 MDMA_AHBCLK_PD 0x00000400
-dict set regsC100 I2CSPI_AHBCLK_PD 0x00000200
-dict set regsC100 UART_AHBCLK_PD 0x00000100
-dict set regsC100 IPSEC_AHBCLK_PD 0x00000080
-dict set regsC100 TDM_AHBCLK_PD 0x00000040
-dict set regsC100 USB1_AHBCLK_PD 0x00000020
-dict set regsC100 USB0_AHBCLK_PD 0x00000010
-dict set regsC100 GEMAC1_AHBCLK_PD 0x00000008
-dict set regsC100 GEMAC0_AHBCLK_PD 0x00000004
-dict set regsC100 PUI_AHBCLK_PD 0x00000002
-dict set regsC100 HIF_AHBCLK_PD 0x00000001
-
-dict set regsC100 ARM1_DIV_BP 0x00001000
-dict set regsC100 ARM1_DIV_VAL_SHIFT 8
-dict set regsC100 ARM0_DIV_BP 0x00000010
-dict set regsC100 ARM0_DIV_VAL_SHIFT 0
-
-dict set regsC100 AHBCLK_PLL_LOCK 0x00000002
-dict set regsC100 FCLK_PLL_LOCK 0x00000001
-
-
-#// reset block
-dict set regsC100 BLOCK_RESET_REG [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x100]
-dict set regsC100 CSP_RESET_REG [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x104]
-
-dict set regsC100 RNG_RST 0x1000
-dict set regsC100 IPSEC_RST 0x0800
-dict set regsC100 DDR_RST 0x0400
-dict set regsC100 USB1_PHY_RST 0x0200
-dict set regsC100 USB0_PHY_RST 0x0100
-dict set regsC100 USB1_RST 0x0080
-dict set regsC100 USB0_RST 0x0040
-dict set regsC100 GEMAC1_RST 0x0020
-dict set regsC100 GEMAC0_RST 0x0010
-dict set regsC100 TDM_RST 0x0008
-dict set regsC100 PUI_RST 0x0004
-dict set regsC100 HIF_RST 0x0002
-dict set regsC100 PCI_RST 0x0001
-
-#////////////////////////////////////////////////////////////////
-#// DDR CONTROLLER block
-#////////////////////////////////////////////////////////////////
-
-dict set regsC100 DDR_CONFIG_BASEADDR 0x0D000000
-dict set regsC100 DENALI_CTL_00_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x00]
-dict set regsC100 DENALI_CTL_01_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x08]
-dict set regsC100 DENALI_CTL_02_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x10]
-dict set regsC100 DENALI_CTL_03_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x18]
-dict set regsC100 DENALI_CTL_04_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x20]
-dict set regsC100 DENALI_CTL_05_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x28]
-dict set regsC100 DENALI_CTL_06_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x30]
-dict set regsC100 DENALI_CTL_07_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x38]
-dict set regsC100 DENALI_CTL_08_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x40]
-dict set regsC100 DENALI_CTL_09_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x48]
-dict set regsC100 DENALI_CTL_10_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x50]
-dict set regsC100 DENALI_CTL_11_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x58]
-dict set regsC100 DENALI_CTL_12_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x60]
-dict set regsC100 DENALI_CTL_13_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x68]
-dict set regsC100 DENALI_CTL_14_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x70]
-dict set regsC100 DENALI_CTL_15_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x78]
-dict set regsC100 DENALI_CTL_16_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x80]
-dict set regsC100 DENALI_CTL_17_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x88]
-dict set regsC100 DENALI_CTL_18_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x90]
-dict set regsC100 DENALI_CTL_19_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x98]
-dict set regsC100 DENALI_CTL_20_DATA [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0xA0]
-
-# 32-bit value
-dict set regsC100 DENALI_READY_CHECK [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x44]
-# 8-bit
-dict set regsC100 DENALI_WR_DQS [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5D]
-# 8-bit
-dict set regsC100 DENALI_DQS_OUT [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x5A]
-# 8-bit
-dict set regsC100 DENALI_DQS_DELAY0 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] + 0x4F]
-# 8-bit
-dict set regsC100 DENALI_DQS_DELAY1 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x50]
-# 8-bit
-dict set regsC100 DENALI_DQS_DELAY2 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x51]
-# 8-bit
-dict set regsC100 DENALI_DQS_DELAY3 [expr [dict get $regsC100 DDR_CONFIG_BASEADDR ] +0x52]
-
-
-# end of proc regsC100
-}
diff --git a/openocd-0.10.0/scripts/target/cc2538.cfg b/openocd-0.10.0/scripts/target/cc2538.cfg
deleted file mode 100644
index 81593c105c936eecf808725bd20d374bbefcdebb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/cc2538.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-# Config for Texas Instruments low power RF SoC CC2538
-# http://www.ti.com/lit/pdf/swru319
-
-if { [info exists CHIPNAME] } {
- set CHIPNAME $CHIPNAME
-} else {
- set CHIPNAME cc2538
-}
-
-if { [info exists JRC_TAPID] } {
- set JRC_TAPID $JRC_TAPID
-} else {
- set JRC_TAPID 0x8B96402F
-}
-
-source [find target/cc26xx.cfg]
diff --git a/openocd-0.10.0/scripts/target/cc26xx.cfg b/openocd-0.10.0/scripts/target/cc26xx.cfg
deleted file mode 100644
index 1492e6a220089dff8a56b3dade75522053f8ab31..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/cc26xx.cfg
+++ /dev/null
@@ -1,43 +0,0 @@
-# Config for Texas Instruments low power SoC CC26xx family
-
-adapter_khz 100
-
-source [find target/icepick.cfg]
-source [find target/ti-cjtag.cfg]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME cc26xx
-}
-
-#
-# Main DAP
-#
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x4BA00477
-}
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
-
-#
-# ICEpick-C (JTAG route controller)
-#
-if { [info exists JRC_TAPID] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x1B99A02F
-}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
-# A start sequence is needed to change from cJTAG (Compact JTAG) to
-# 4-pin JTAG before talking via JTAG commands
-jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
-jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
-
-#
-# Cortex-M3 target
-#
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap
diff --git a/openocd-0.10.0/scripts/target/cc32xx.cfg b/openocd-0.10.0/scripts/target/cc32xx.cfg
deleted file mode 100644
index 154bf9106be839fc8a320e9c8baafbf35d15dedf..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/cc32xx.cfg
+++ /dev/null
@@ -1,53 +0,0 @@
-# Config for Texas Instruments SoC CC32xx family
-
-source [find target/swj-dp.tcl]
-
-adapter_khz 100
-
-source [find target/icepick.cfg]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME cc32xx
-}
-
-#
-# Main DAP
-#
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- if {[using_jtag]} {
- set _DAP_TAPID 0x4BA00477
- } else {
- set _DAP_TAPID 0x2BA01477
- }
-}
-
-if {[using_jtag]} {
- jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
- jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
-} else {
- swj_newdap $_CHIPNAME dap -expected-id $_DAP_TAPID
-}
-
-#
-# ICEpick-C (JTAG route controller)
-#
-if { [info exists JRC_TAPID] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x0B97C02F
-}
-
-if {[using_jtag]} {
- jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
- jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
-}
-
-#
-# Cortex-M3 target
-#
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap
diff --git a/openocd-0.10.0/scripts/target/cs351x.cfg b/openocd-0.10.0/scripts/target/cs351x.cfg
deleted file mode 100644
index cb05da2cfc97502e70e75a28c30c80ba619b3a4a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/cs351x.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME cs351x
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x00526fa1
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# Create the GDB Target.
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME fa526 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# There is 16K of SRAM on this chip
-# FIXME: flash programming is not working by using this work area. So comment this out for now.
-#$_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1
-
-# This chip has a DCC ... use it
-arm7_9 dcc_downloads enable
-
diff --git a/openocd-0.10.0/scripts/target/davinci.cfg b/openocd-0.10.0/scripts/target/davinci.cfg
deleted file mode 100644
index 859a92539a0a0faef1854cbef78d8e89c56b444a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/davinci.cfg
+++ /dev/null
@@ -1,377 +0,0 @@
-#
-# Utility code for DaVinci-family chips
-#
-
-# davinci_pinmux: assigns PINMUX$reg <== $value
-proc davinci_pinmux {soc reg value} {
- mww [expr [dict get $soc sysbase] + 4 * $reg] $value
-}
-
-source [find mem_helper.tcl]
-
-#
-# pll_setup: initialize PLL
-# - pll_addr ... physical addr of controller
-# - mult ... pll multiplier
-# - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers
-#
-# For PLLs that don't have a given register (e.g. plldiv8), or where a
-# given divider is non-programmable, caller provides *NO* config mapping.
-#
-
-# PLL version 0x02: tested on dm355
-# REVISIT: On dm6446/dm357 the PLLRST polarity is different.
-proc pll_v02_setup {pll_addr mult config} {
- set pll_ctrl_addr [expr $pll_addr + 0x100]
- set pll_ctrl [mrw $pll_ctrl_addr]
-
- # 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
- # NOTE: this assumes we should clear that bit
- set pll_ctrl [expr $pll_ctrl & ~0x0100]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 2 - clear PLLENSRC (bit 5)
- set pll_ctrl [expr $pll_ctrl & ~0x0020]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 3 - clear PLLEN (bit 0) ... enter bypass mode
- set pll_ctrl [expr $pll_ctrl & ~0x0001]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 4 - wait at least 4 refclk cycles
- sleep 1
-
- # 5 - set PLLRST (bit 3)
- set pll_ctrl [expr $pll_ctrl | 0x0008]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 6 - set PLLDIS (bit 4)
- set pll_ctrl [expr $pll_ctrl | 0x0010]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 7 - clear PLLPWRDN (bit 1)
- set pll_ctrl [expr $pll_ctrl & ~0x0002]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 8 - clear PLLDIS (bit 4)
- set pll_ctrl [expr $pll_ctrl & ~0x0010]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 9 - optional: write prediv, postdiv, and pllm
- # NOTE: for dm355 PLL1, postdiv is controlled via MISC register
- mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff]
- if { [dict exists $config prediv] } {
- set div [dict get $config prediv]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0114] $div
- }
- if { [dict exists $config postdiv] } {
- set div [dict get $config postdiv]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0128] $div
- }
-
- # 10 - optional: set plldiv1, plldiv2, ...
- # NOTE: this assumes some registers have their just-reset values:
- # - PLLSTAT.GOSTAT is clear when we enter
- # - ALNCTL has everything set
- set go 0
- if { [dict exists $config div1] } {
- set div [dict get $config div1]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0118] $div
- set go 1
- }
- if { [dict exists $config div2] } {
- set div [dict get $config div2]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x011c] $div
- set go 1
- }
- if { [dict exists $config div3] } {
- set div [dict get $config div3]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0120] $div
- set go 1
- }
- if { [dict exists $config div4] } {
- set div [dict get $config div4]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0160] $div
- set go 1
- }
- if { [dict exists $config div5] } {
- set div [dict get $config div5]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0164] $div
- set go 1
- }
- if {$go != 0} {
- # write pllcmd.GO; poll pllstat.GO
- mww [expr $pll_addr + 0x0138] 0x01
- set pllstat [expr $pll_addr + 0x013c]
- while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
- }
- mww [expr $pll_addr + 0x0138] 0x00
-
- # 11 - wait at least 5 usec for reset to finish
- # (assume covered by overheads including JTAG messaging)
-
- # 12 - clear PLLRST (bit 3)
- set pll_ctrl [expr $pll_ctrl & ~0x0008]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 13 - wait at least 8000 refclk cycles for PLL to lock
- # if we assume 24 MHz (slowest osc), that's 1/3 msec
- sleep 3
-
- # 14 - set PLLEN (bit 0) ... leave bypass mode
- set pll_ctrl [expr $pll_ctrl | 0x0001]
- mww $pll_ctrl_addr $pll_ctrl
-}
-
-# PLL version 0x03: tested on dm365
-proc pll_v03_setup {pll_addr mult config} {
- set pll_ctrl_addr [expr $pll_addr + 0x100]
- set pll_secctrl_addr [expr $pll_addr + 0x108]
- set pll_ctrl [mrw $pll_ctrl_addr]
-
- # 1 - power up the PLL
- set pll_ctrl [expr $pll_ctrl & ~0x0002]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 2 - clear PLLENSRC (bit 5)
- set pll_ctrl [expr $pll_ctrl & ~0x0020]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 2 - clear PLLEN (bit 0) ... enter bypass mode
- set pll_ctrl [expr $pll_ctrl & ~0x0001]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 3 - wait at least 4 refclk cycles
- sleep 1
-
- # 4 - set PLLRST (bit 3)
- set pll_ctrl [expr $pll_ctrl | 0x0008]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 5 - wait at least 5 usec
- sleep 1
-
- # 6 - clear PLLRST (bit 3)
- set pll_ctrl [expr $pll_ctrl & ~0x0008]
- mww $pll_ctrl_addr $pll_ctrl
-
- # 9 - optional: write prediv, postdiv, and pllm
- mww [expr $pll_addr + 0x0110] [expr ($mult / 2) & 0x1ff]
- if { [dict exists $config prediv] } {
- set div [dict get $config prediv]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0114] $div
- }
- if { [dict exists $config postdiv] } {
- set div [dict get $config postdiv]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0128] $div
- }
-
- # 10 - write start sequence to PLLSECCTL
- mww $pll_secctrl_addr 0x00470000
- mww $pll_secctrl_addr 0x00460000
- mww $pll_secctrl_addr 0x00400000
- mww $pll_secctrl_addr 0x00410000
-
- # 11 - optional: set plldiv1, plldiv2, ...
- # NOTE: this assumes some registers have their just-reset values:
- # - PLLSTAT.GOSTAT is clear when we enter
- set aln 0
- if { [dict exists $config div1] } {
- set div [dict get $config div1]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0118] $div
- set aln [expr $aln | 0x1]
- } else {
- mww [expr $pll_addr + 0x0118] 0
- }
- if { [dict exists $config div2] } {
- set div [dict get $config div2]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x011c] $div
- set aln [expr $aln | 0x2]
- } else {
- mww [expr $pll_addr + 0x011c] 0
- }
- if { [dict exists $config div3] } {
- set div [dict get $config div3]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0120] $div
- set aln [expr $aln | 0x4]
- } else {
- mww [expr $pll_addr + 0x0120] 0
- }
- if { [dict exists $config oscdiv] } {
- set div [dict get $config oscdiv]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0124] $div
- } else {
- mww [expr $pll_addr + 0x0124] 0
- }
- if { [dict exists $config div4] } {
- set div [dict get $config div4]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0160] $div
- set aln [expr $aln | 0x8]
- } else {
- mww [expr $pll_addr + 0x0160] 0
- }
- if { [dict exists $config div5] } {
- set div [dict get $config div5]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0164] $div
- set aln [expr $aln | 0x10]
- } else {
- mww [expr $pll_addr + 0x0164] 0
- }
- if { [dict exists $config div6] } {
- set div [dict get $config div6]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0168] $div
- set aln [expr $aln | 0x20]
- } else {
- mww [expr $pll_addr + 0x0168] 0
- }
- if { [dict exists $config div7] } {
- set div [dict get $config div7]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x016c] $div
- set aln [expr $aln | 0x40]
- } else {
- mww [expr $pll_addr + 0x016c] 0
- }
- if { [dict exists $config div8] } {
- set div [dict get $config div8]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0170] $div
- set aln [expr $aln | 0x80]
- } else {
- mww [expr $pll_addr + 0x0170] 0
- }
- if { [dict exists $config div9] } {
- set div [dict get $config div9]
- set div [expr 0x8000 | ($div - 1)]
- mww [expr $pll_addr + 0x0174] $div
- set aln [expr $aln | 0x100]
- } else {
- mww [expr $pll_addr + 0x0174] 0
- }
- if {$aln != 0} {
- # clear pllcmd.GO
- mww [expr $pll_addr + 0x0138] 0x00
- # write alingment flags
- mww [expr $pll_addr + 0x0140] $aln
- # write pllcmd.GO; poll pllstat.GO
- mww [expr $pll_addr + 0x0138] 0x01
- set pllstat [expr $pll_addr + 0x013c]
- while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
- }
- mww [expr $pll_addr + 0x0138] 0x00
- set addr [dict get $config ctladdr]
- while {[expr [mrw $addr] & 0x0e000000] != 0x0e000000} { sleep 1 }
-
- # 12 - set PLLEN (bit 0) ... leave bypass mode
- set pll_ctrl [expr $pll_ctrl | 0x0001]
- mww $pll_ctrl_addr $pll_ctrl
-}
-
-# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain
-# modules can be enabled.
-
-# prepare a non-DSP module to be enabled; finish with psc_go
-proc psc_enable {module} {
- set psc_addr 0x01c41000
- # write MDCTL
- mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
-}
-
-# prepare a non-DSP module to be reset; finish with psc_go
-proc psc_reset {module} {
- set psc_addr 0x01c41000
- # write MDCTL
- mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f
-}
-
-# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
-proc psc_go {} {
- set psc_addr 0x01c41000
- set ptstat_addr [expr $psc_addr + 0x0128]
-
- # just in case PTSTAT.go isn't clear
- while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
-
- # write PTCMD.go ... ignoring any DSP power domain
- mww [expr $psc_addr + 0x0120] 1
-
- # wait for PTSTAT.go to clear (again ignoring DSP power domain)
- while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
-}
-
-#
-# A reset using only SRST is a "Warm Reset", resetting everything in the
-# chip except ARM emulation (and everything _outside_ the chip that hooks
-# up to SRST). But many boards don't expose SRST via their JTAG connectors
-# (it's not present on TI-14 headers).
-#
-# From the chip-only perspective, a "Max Reset" is a "Warm" reset ... except
-# without any board-wide side effects, since it's triggered using JTAG using
-# either (a) ARM watchdog timer, or (b) ICEpick.
-#
-proc davinci_wdog_reset {} {
- set timer2_phys 0x01c21c00
-
- # NOTE -- on entry
- # - JTAG communication with the ARM *must* be working OK; this
- # may imply using adaptive clocking or disabling WFI-in-idle
- # - current target must be the DaVinci ARM
- # - that ARM core must be halted
- # - timer2 clock is still enabled (PSC 29 on most chips)
-
- #
- # Part I -- run regardless of being halted via JTAG
- #
- # NOTE: for now, we assume there's no DSP that could control the
- # watchdog; or, equivalently, SUSPSRC.TMR2SRC says the watchdog
- # suspend signal is controlled via ARM emulation suspend.
- #
-
- # EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
- mww phys [expr $timer2_phys + 0x28] 0x00004000
-
- #
- # Part II -- in case watchdog hasn't been set up
- #
-
- # TCR: disable, force internal clock source
- mww phys [expr $timer2_phys + 0x20] 0
-
- # TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
- mww phys [expr $timer2_phys + 0x24] 0
- mww phys [expr $timer2_phys + 0x24] 0x110b
-
- # clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
- # so watchdog triggers ASAP
- mww phys [expr $timer2_phys + 0x10] 0
- mww phys [expr $timer2_phys + 0x14] 0
- mww phys [expr $timer2_phys + 0x18] 0
- mww phys [expr $timer2_phys + 0x1c] 0
-
- # WDTCR: put into pre-active state, then active
- mww phys [expr $timer2_phys + 0x28] 0xa5c64000
- mww phys [expr $timer2_phys + 0x28] 0xda7e4000
-
- #
- # Part III -- it's ready to rumble
- #
-
- # WDTCR: write invalid WDKEY to trigger reset
- mww phys [expr $timer2_phys + 0x28] 0x00004000
-}
diff --git a/openocd-0.10.0/scripts/target/dragonite.cfg b/openocd-0.10.0/scripts/target/dragonite.cfg
deleted file mode 100644
index 750fd6437cb46de0bc9a329ff3317ed65de5c095..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/dragonite.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-######################################
-# Target: Marvell Dragonite CPU core
-######################################
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME dragonite
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x121003d3
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME
-
-reset_config trst_and_srst
-adapter_nsrst_delay 200
-jtag_ntrst_delay 200
-
diff --git a/openocd-0.10.0/scripts/target/dsp56321.cfg b/openocd-0.10.0/scripts/target/dsp56321.cfg
deleted file mode 100644
index 6f3222373f36e04368fd721b367521d753f5305a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/dsp56321.cfg
+++ /dev/null
@@ -1,37 +0,0 @@
-# Script for freescale DSP56321
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME dsp56321
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a big endian
- set _ENDIAN big
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x1181501d
-}
-
-#jtag speed
-adapter_khz 4500
-
-#has only srst
-reset_config srst_only
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x1 -expected-id $_CPUTAPID
-
-#target configuration
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME dsp563xx -endian $_ENDIAN -chain-position $_TARGETNAME
-
-#working area at base of ram
-$_TARGETNAME configure -work-area-virt 0
diff --git a/openocd-0.10.0/scripts/target/dsp568013.cfg b/openocd-0.10.0/scripts/target/dsp568013.cfg
deleted file mode 100644
index 0c491fa959cc03eb9edc9061714ead73593ebb6f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/dsp568013.cfg
+++ /dev/null
@@ -1,76 +0,0 @@
-# Script for freescale DSP568013
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME dsp568013
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a big endian
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x01f2401d
-}
-
-#jtag speed
-adapter_khz 800
-
-reset_config srst_only
-
-#MASTER tap
-jtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID
-
-#CORE tap
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004
-
-#target configuration - There is only 1 tap at a time, hence only 1 target is defined.
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# Setup the interesting tap
-# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations requiere certain instruction to be in the IR register during reset, and polling would change this)
-jtag configure $_CHIPNAME.chp -event setup "
- jtag tapenable $_TARGETNAME
- poll off
-"
-
-#select CORE tap by modifying the TLM register.
-#to be used when MASTER tap is selected.
-jtag configure $_TARGETNAME -event tap-enable "
- irscan $_CHIPNAME.chp 0x05;
- drscan $_CHIPNAME.chp 4 0x02;
- jtag tapdisable $_CHIPNAME.chp;
-"
-
-#select MASTER tap by modifying the TLM register.
-#to be used when CORE tap is selected.
-jtag configure $_CHIPNAME.chp -event tap-enable "
- irscan $_TARGETNAME 0x08;
- drscan $_TARGETNAME 4 0x1;
- jtag tapdisable $_TARGETNAME;
-"
-
-#disables the master tap
-jtag configure $_TARGETNAME -event tap-disable "
-"
-#TODO FIND SMARTER WAY.
-
-jtag configure $_CHIPNAME.chp -event tap-disable "
-"
-#TODO FIND SMARTER WAY.
-
-
-#working area at base of ram
-$_TARGETNAME configure -work-area-virt 0
-
-#setup flash
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
-
diff --git a/openocd-0.10.0/scripts/target/dsp568037.cfg b/openocd-0.10.0/scripts/target/dsp568037.cfg
deleted file mode 100644
index 01194d0028ad2f18965dcf0c10d282b3138dcfcd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/dsp568037.cfg
+++ /dev/null
@@ -1,72 +0,0 @@
-# Script for freescale DSP568037
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME dsp568037
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a big endian
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x01f2801d
-}
-
-#jtag speed
-adapter_khz 800
-
-reset_config srst_only
-
-#MASTER tap
-jtag newtap $_CHIPNAME chp -irlen 8 -ircapture 1 -irmask 0x03 -expected-id $_CPUTAPID
-
-#CORE tap
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x03 -disable -expected-id 0x02211004
-
-#target configuration - There is only 1 tap at a time, hence only 1 target is defined.
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# Setup the interesting tap
-jtag configure $_CHIPNAME.chp -event setup "jtag tapenable $_TARGETNAME"
-
-#select CORE tap by modifying the TLM register.
-#to be used when MASTER tap is selected.
-jtag configure $_TARGETNAME -event tap-enable "
- irscan $_CHIPNAME.chp 0x05;
- drscan $_CHIPNAME.chp 4 0x02;
- jtag tapdisable $_CHIPNAME.chp;
-"
-
-#select MASTER tap by modifying the TLM register.
-#to be used when CORE tap is selected.
-jtag configure $_CHIPNAME.chp -event tap-enable "
- irscan $_TARGETNAME 0x08;
- drscan $_TARGETNAME 4 0x1;
- jtag tapdisable $_TARGETNAME;
-"
-
-#disables the master tap
-jtag configure $_TARGETNAME -event tap-disable "
-"
-#TODO FIND SMARTER WAY.
-
-jtag configure $_CHIPNAME.chp -event tap-disable "
-"
-#TODO FIND SMARTER WAY.
-
-
-#working area at base of ram
-$_TARGETNAME configure -work-area-virt 0
-
-#setup flash
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
-
diff --git a/openocd-0.10.0/scripts/target/efm32.cfg b/openocd-0.10.0/scripts/target/efm32.cfg
deleted file mode 100644
index 33610d5a81c9a263202dea3652ebd3262752b23c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/efm32.cfg
+++ /dev/null
@@ -1,43 +0,0 @@
-#
-# efm32 target
-#
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME efm32
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 2kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x800
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x2ba01477
-}
-
-swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
-
-adapter_khz 1000
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/efm32_stlink.cfg b/openocd-0.10.0/scripts/target/efm32_stlink.cfg
deleted file mode 100644
index 230155ea02118aaeedd4d181a618ef6f0554d06a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/efm32_stlink.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-echo "WARNING: target/efm32_stlink.cfg is deprecated, please switch to target/efm32.cfg"
-source [find target/efm32.cfg]
diff --git a/openocd-0.10.0/scripts/target/em357.cfg b/openocd-0.10.0/scripts/target/em357.cfg
deleted file mode 100644
index 24ffb04f92378db7333182489a71f638875cf353..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/em357.cfg
+++ /dev/null
@@ -1,76 +0,0 @@
-#
-# Target configuration for the Silicon Labs EM357 chips
-#
-
-#
-# em357 family supports JTAG and SWD transports
-#
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME em357
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 4kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x1000
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- set _CPUTAPID 0x3ba00477
- } else {
- set _CPUTAPID 0x1ba00477
- }
-}
-
-if { [info exists BSTAPID] } {
- set _BSTAPID $BSTAPID
-} else {
- set _BSTAPID 0x069a962b
-}
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME em358
-}
-
-if { [info exists FLASHSIZE] } {
- set _FLASHSIZE $FLASHSIZE
-} else {
- set _FLASHSIZE 0x30000
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-if { [using_jtag] } {
- swj_newdap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME em357 0x08000000 $_FLASHSIZE 0 0 $_TARGETNAME
-
-if { ![using_hla]} {
-# according to errata, we need to use vectreset rather than sysresetreq to avoid lockup
-# There is a bug in the chip, which means that when using external debuggers the chip
-# may lock up in certain CPU clock modes. Affected modes are operating the CPU at
-# 24MHz derived from the 24MHz crystal, or 12MHz derived from the high frequency RC
-# oscillator. If an external debugger tool asserts SYSRESETREQ, the chip will lock up and
-# require a pin reset or power cycle.
-#
-# for details, refer to:
-# http://www.silabs.com/Support%20Documents/TechnicalDocs/EM35x-Errata.pdf
- cortex_m reset_config vectreset
-}
diff --git a/openocd-0.10.0/scripts/target/em358.cfg b/openocd-0.10.0/scripts/target/em358.cfg
deleted file mode 100644
index 92e65a4c78afec624c49441fa444bb4f09b368c4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/em358.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-# Target configuration for the Silicon Labs EM358 chips
-
-#
-# em357 family supports JTAG and SWD transports
-#
-
-if { ![info exists CHIPNAME] } {
- set CHIPNAME em358
-}
-
-if { ![info exists BSTAPID] } {
- set BSTAPID 0x069aa62b
-}
-
-# 512K of flash in the em358 chips
-set FLASHSIZE 0x80000
-source [find target/em357.cfg]
diff --git a/openocd-0.10.0/scripts/target/epc9301.cfg b/openocd-0.10.0/scripts/target/epc9301.cfg
deleted file mode 100644
index f186d37dc680410482dc905150c3449472cf71dd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/epc9301.cfg
+++ /dev/null
@@ -1,32 +0,0 @@
-# Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME ep9301
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # Force an error until we get a good number.
- set _CPUTAPID 0xffffffff
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1
-
-#flash configuration
-#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x60000000 0x1000000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/exynos5250.cfg b/openocd-0.10.0/scripts/target/exynos5250.cfg
deleted file mode 100644
index 36783410ba009bc0b5c8bb85910fa47ab364bc84..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/exynos5250.cfg
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# Samsung Exynos 5250 - dual-core ARM Cortex-A15
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME exynos5250
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4ba00477
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create ${_TARGETNAME}0 cortex_a -chain-position $_TARGETNAME
-target create ${_TARGETNAME}1 cortex_a -chain-position $_TARGETNAME
-
-target smp ${_TARGETNAME}0 ${_TARGETNAME}1
diff --git a/openocd-0.10.0/scripts/target/faux.cfg b/openocd-0.10.0/scripts/target/faux.cfg
deleted file mode 100644
index d3891cded94a800e455189a259a55b85e4a56a88..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/faux.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-#Script for faux target - used for testing
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME at91eb40a
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x00000000
-}
-
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-#target configuration
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-#dummy flash driver
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME faux 0x01000000 0x200000 2 2 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/feroceon.cfg b/openocd-0.10.0/scripts/target/feroceon.cfg
deleted file mode 100644
index 389576e55c7e0fd058cf0986c1c390aad45043f3..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/feroceon.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-######################################
-# Target: Marvell Feroceon CPU core
-######################################
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME feroceon
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x20a023d3
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
-
-reset_config trst_and_srst
-adapter_nsrst_delay 200
-jtag_ntrst_delay 200
-
diff --git a/openocd-0.10.0/scripts/target/fm3.cfg b/openocd-0.10.0/scripts/target/fm3.cfg
deleted file mode 100644
index 78bbc945cea63967e767307fda1c6947214de638..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/fm3.cfg
+++ /dev/null
@@ -1,53 +0,0 @@
-# MB9BF506
-# Fujitsu Cortex-M3 with 512kB Flash and 64kB RAM
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME mb9bfxx6
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4ba00477
-}
-
-# delays on reset lines
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-# Fujitsu Cortex-M3 reset configuration
-reset_config trst_only
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# MB9BF506 has 64kB of SRAM on its main system bus
-$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
-
-# MB9BF506 has 512kB internal FLASH
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
-
-# 4MHz / 6 = 666kHz, so use 500
-adapter_khz 500
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/fm4.cfg b/openocd-0.10.0/scripts/target/fm4.cfg
deleted file mode 100644
index e5d0f8d60e2336544ebd885594323a2e1e3a3356..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/fm4.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-#
-# Spansion FM4 (ARM Cortex-M4)
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME fm4
-}
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CPUTAPID] } {
- set _CPU_TAPID $CPUTAPID
-} elseif { [using_jtag] } {
- set _CPU_TAPID 0x4ba00477
-} else {
- set _CPU_TAPID 0x2ba01477
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
-
-adapter_khz 500
-
-if {![using_hla]} {
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/fm4_mb9bf.cfg b/openocd-0.10.0/scripts/target/fm4_mb9bf.cfg
deleted file mode 100644
index e53fdc8787f51906e28c34d66f445fa974c8469a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/fm4_mb9bf.cfg
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# Spansion FM4 MB9BFxxx (ARM Cortex-M4)
-#
-
-source [find target/fm4.cfg]
-
-# MB9BF566 M/N/R have 32 KB SRAM0
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x8000
-}
-
-$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE] \
- -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME fm4 0x00000000 0 0 0 $_TARGETNAME $CHIPSERIES
diff --git a/openocd-0.10.0/scripts/target/fm4_s6e2cc.cfg b/openocd-0.10.0/scripts/target/fm4_s6e2cc.cfg
deleted file mode 100644
index 60b73b9747feb35fb47186387f3ff1fe41a3116b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/fm4_s6e2cc.cfg
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Spansion FM4 S6E2CC (ARM Cortex-M4)
-#
-
-source [find target/fm4.cfg]
-
-# S6E2CC8 H/J/L have 96 KB SRAM0
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x18000
-}
-
-$_TARGETNAME configure -work-area-phys [expr 0x20000000 - $_WORKAREASIZE] \
- -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank ${_FLASHNAME}0 fm4 0x00000000 0 0 0 $_TARGETNAME $CHIPSERIES
-flash bank ${_FLASHNAME}1 fm4 0x00100000 0 0 0 $_TARGETNAME $CHIPSERIES
diff --git a/openocd-0.10.0/scripts/target/gp326xxxa.cfg b/openocd-0.10.0/scripts/target/gp326xxxa.cfg
deleted file mode 100644
index feb7554b7924c6fc27edc441fd6ff2d2b8a71eaf..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/gp326xxxa.cfg
+++ /dev/null
@@ -1,94 +0,0 @@
-#
-# Support for General Plus GP326XXXA chips
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME gp326xxxa
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4f1f0f0f
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# Use internal SRAM as a work area
-$_TARGETNAME configure -work-area-phys 0xf8000000 -work-area-size 0x8000 -work-area-backup 0
-
-# The chip has both lines connected together
-reset_config trst_and_srst srst_pulls_trst
-# This delay is needed otherwise communication with the target would
-# be unreliable
-adapter_nsrst_delay 100
-
-# Set the adapter speed ridiculously low just in case we are
-# running off of a 32kHz clock
-adapter_khz 2
-
-proc gp32xxxa_halt_and_reset_control_registers {} {
- # System control registers
- set P_SYSTEM_CTRL_NEW 0xD0000008
- set P_SYSTEM_CTRL 0xD000000C
- set P_SYSTEM_CLK_EN0 0xD0000010
- set P_SYSTEM_CLK_EN1 0xD0000014
- set P_SYSTEM_RESET_FLAG 0xD0000018
- set P_SYSTEM_CLK_CTRL 0xD000001C
- set P_SYSTEM_LVR_CTRL 0xD0000020
- set P_SYSTEM_WATCHDOG_CTRL 0xD0000024
- set P_SYSTEM_PLLEN 0xD000005C
-
- # Since we can't use SRST without pulling TRST
- # we can't assume the state of the clock configuration
- # or watchdog settings. So reset them before porceeding
-
- # Set the adapter speed ridiculously low just in case we are
- # running off of a 32kHz clock
- adapter_khz 2
-
- # Disable any advanced features at this stage
- arm7_9 dcc_downloads disable
- arm7_9 fast_memory_access disable
-
- # Do a "soft reset"
- soft_reset_halt
- # Reset all system control registers to their default "after-reset" values
- mwh $P_SYSTEM_WATCHDOG_CTRL 0x0000
- mwh $P_SYSTEM_LVR_CTRL 0x0000
-
- mwh $P_SYSTEM_CTRL_NEW 0x0001
- mwh $P_SYSTEM_CTRL 0x0001
- # Clear all reset flags by writing 1's
- mwh $P_SYSTEM_RESET_FLAG 0x001C
-
- mwh $P_SYSTEM_CLK_CTRL 0x8000
- mwh $P_SYSTEM_CLK_EN0 0xFFFF
- mwh $P_SYSTEM_CLK_EN1 0xFFFF
- mwh $P_SYSTEM_PLLEN 0x0010
-
- # Unfortunately there's no register that would allow us to
- # know if PLL is locked. So just wait for 100ms in hopes that
- # it would be enough.
- sleep 100
-
- # Now that we know that we are running at 48Mhz
- # Increase JTAG speed and enable speed optimization features
- adapter_khz 5000
- arm7_9 dcc_downloads enable
- arm7_9 fast_memory_access enable
-}
-
-$_TARGETNAME configure -event reset-end { gp32xxxa_halt_and_reset_control_registers }
diff --git a/openocd-0.10.0/scripts/target/hilscher_netx10.cfg b/openocd-0.10.0/scripts/target/hilscher_netx10.cfg
deleted file mode 100644
index 3f96607c6a944cd49a739ff4319ca34ea2cac15c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/hilscher_netx10.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-################################################################################
-# Author: Michael Trensch (MTrensch@googlemail.com)
-################################################################################
-
-#Hilscher netX 10 CPU
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME netx10
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x25966021
-}
-
-# jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# that TAP is associated with a target
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
-
diff --git a/openocd-0.10.0/scripts/target/hilscher_netx50.cfg b/openocd-0.10.0/scripts/target/hilscher_netx50.cfg
deleted file mode 100644
index c6510c613810348d27e79cb000f264d927e1f43a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/hilscher_netx50.cfg
+++ /dev/null
@@ -1,50 +0,0 @@
-################################################################################
-# Author: Michael Trensch (MTrensch@googlemail.com)
-################################################################################
-
-#Hilscher netX 50 CPU
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME netx50
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x25966021
-}
-
-# jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# that TAP is associated with a target
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# On netX50 SDRAM is not accessible at offset 0xDEAD0-0xDEADF as it is busy from
-# DMA controller at init. This function will setup a dummy DMA to free this ares
-# and must be called before using SDRAM
-proc sdram_fix { } {
-
- mww 0x1c005830 0x00000001
-
- mww 0x1c005104 0xBFFFFFFC
- mww 0x1c00510c 0x00480001
- mww 0x1c005110 0x00000001
-
- sleep 100
-
- mww 0x1c00510c 0
- mww 0x1c005110 0
- mww 0x1c005830 0x00000000
-
- puts "SDRAM Fix executed!"
-}
diff --git a/openocd-0.10.0/scripts/target/hilscher_netx500.cfg b/openocd-0.10.0/scripts/target/hilscher_netx500.cfg
deleted file mode 100644
index 93375fd819f65f85198dcbb5da49b5936c874ae6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/hilscher_netx500.cfg
+++ /dev/null
@@ -1,47 +0,0 @@
-#Hilscher netX 500 CPU
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME netx500
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07926021
-}
-
-# jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# that TAP is associated with a target
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
-
-proc mread32 {addr} {
- set value(0) 0
- mem2array value 32 $addr 1
- return $value(0)
-}
-
-# This function must be called on netX100/500 right after halt
-# If it is called later the needed register cannot be written anymore
-proc sdram_fix { } {
-
- set accesskey [mread32 0x00100070]
- mww 0x00100070 [expr $accesskey]
- mww 0x0010002c 0x00000001
-
- if {[expr [mread32 0x0010002c] & 0x07] == 0x07} {
- puts "SDRAM Fix was not executed. Probably your CPU halted too late and the register is already locked!"
- } else {
- puts "SDRAM Fix succeeded!"
- }
-}
diff --git a/openocd-0.10.0/scripts/target/icepick.cfg b/openocd-0.10.0/scripts/target/icepick.cfg
deleted file mode 100644
index abd7b6a084db6c5468edc49db3acffcaf97241c1..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/icepick.cfg
+++ /dev/null
@@ -1,142 +0,0 @@
-#
-# Copyright (C) 2011 by Karl Kurbjun
-# Copyright (C) 2009 by David Brownell
-#
-
-# Utilities for TI ICEpick-C/D used in most TI SoCs
-# Details about the ICEPick are available in the the TRM for each SoC
-# and http://processors.wiki.ti.com/index.php/ICEPICK
-
-# create "constants"
-proc CONST { key } {
-
- array set constant {
- # define ICEPick instructions
- IR_BYPASS 0x00
- IR_ROUTER 0x02
- IR_CONNECT 0x07
- IF_BYPASS 0x3F
- }
- return $constant($key)
-}
-
-# Instruction to connect to the icepick module
-proc icepick_c_connect {jrc} {
-
- # Send CONNECT instruction in IR state
- irscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE
-
- # Send write and connect key
- drscan $jrc 8 0x89 -endstate DRPAUSE
-}
-
-# Instruction to disconnect to the icepick module
-proc icepick_c_disconnect {jrc} {
-
- # Send CONNECT instruction in IR state
- irscan $jrc [CONST IR_CONNECT] -endstate IRPAUSE
-
- # Send write and connect key
- drscan $jrc 8 0x86 -endstate DRPAUSE
-}
-
-#
-# icepick_c_router:
-# this function is for sending router commands
-# arguments are:
-# jrc: TAP name for the ICEpick
-# rw: read/write (0 for read, 1 for write)
-# block: icepick or DAP
-# register: which register to read/write
-# payload: value to read/write
-# this function is for sending router commands
-#
-proc icepick_c_router {jrc rw block register payload} {
-
- set new_dr_value \
- [expr ( ($rw & 0x1) << 31) | ( ($block & 0x7) << 28) | \
- ( ($register & 0xF) << 24) | ( $payload & 0xFFFFFF ) ]
-
-# echo "\tNew router value:\t0x[format %x $new_dr_value]"
-
- # select router
- irscan $jrc [CONST IR_ROUTER] -endstate IRPAUSE
-
- # ROUTER instructions are 32 bits wide
- set old_dr_value [drscan $jrc 32 $new_dr_value -endstate DRPAUSE]
-}
-
-# Configure the icepick control register
-proc icepick_c_setup {jrc} {
-
- # send a router write, block is 0, register is 1, value is 0x2100
- icepick_c_router $jrc 1 0x0 0x1 0x001000
-}
-
-# jrc == TAP name for the ICEpick
-# port == a port number, 0..15
-proc icepick_c_tapenable {jrc port} {
-
- # First CONNECT to the ICEPick
-# echo "Connecting to ICEPick"
- icepick_c_connect $jrc
-
-# echo "Configuring the ICEpick"
- icepick_c_setup $jrc
-
- # NOTE: it's important not to enter RUN/IDLE state until
- # done sending these instructions and data to the ICEpick.
- # And never to enter RESET, which will disable the TAPs.
-
- # first enable power and clock for TAP
- icepick_c_router $jrc 1 0x2 $port 0x100048
-
- # TRM states that the register should be read back here, skipped for now
-
- # enable debug "default" mode
- icepick_c_router $jrc 1 0x2 $port 0x102048
-
- # TRM states that debug enable and debug mode should be read back and
- # confirmed - skipped for now
-
- # Finally select the tap
- icepick_c_router $jrc 1 0x2 $port 0x102148
-
- # Enter the bypass state
- irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE
- runtest 10
-}
-
-# jrc == TAP name for the ICEpick
-# coreid== core id number 0..15 (not same as port number!)
-proc icepick_d_set_coreid {jrc coreid } {
- icepick_c_router $jrc 1 0x6 $coreid 0x2008
-}
-
-# jrc == TAP name for the ICEpick
-# port == a port number, 0..15
-# Follow the sequence described in
-# http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf
-proc icepick_d_tapenable {jrc port coreid} {
- # First CONNECT to the ICEPick
- icepick_c_connect $jrc
- icepick_c_setup $jrc
-
- # Select the port
- icepick_c_router $jrc 1 0x2 $port 0x2108
-
- # Set 4 bit core ID to the Cortex-A
- icepick_d_set_coreid $jrc $coreid
-
- # Enter the bypass state
- irscan $jrc [CONST IF_BYPASS] -endstate RUN/IDLE
- runtest 10
-}
-
-# This function uses the ICEPick to send a warm system reset
-proc icepick_c_wreset {jrc} {
-
- # send a router write, block is 0, register is 1, value is 0x2100
- icepick_c_router $jrc 1 0x0 0x1 0x002101
-}
-
diff --git a/openocd-0.10.0/scripts/target/imx.cfg b/openocd-0.10.0/scripts/target/imx.cfg
deleted file mode 100644
index 9eea53eef2194305a03540b177136beba5c4f76f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/imx.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-# utility fn's for Freescale i.MX series
-
-global TARGETNAME
-set TARGETNAME $_TARGETNAME
-
-# rewrite commands of the form below to arm11 mcr...
-# Data.Set c15:0x042f %long 0x40000015
-proc setc15 {regs value} {
- global TARGETNAME
-
- echo [format "set p15 0x%04x, 0x%08x" $regs $value]
-
- arm mcr 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
-}
-
-
-proc imx3x_reset {} {
- # this reset script comes from the Freescale PDK
- #
- # http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX35PDK
-
- echo "Target Setup: initialize DRAM controller and peripherals"
-
-# Data.Set c15:0x01 %long 0x00050078
- setc15 0x01 0x00050078
-
- echo "configuring CP15 for enabling the peripheral bus"
-# Data.Set c15:0x042f %long 0x40000015
- setc15 0x042f 0x40000015
-}
diff --git a/openocd-0.10.0/scripts/target/imx21.cfg b/openocd-0.10.0/scripts/target/imx21.cfg
deleted file mode 100644
index 2d9ce39c61f7e80e0b13812db1fc19dec6f3d785..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/imx21.cfg
+++ /dev/null
@@ -1,34 +0,0 @@
-#use combined on interfaces or targets that can't set TRST/SRST separately
-#
-# Hmmm.... should srst_pulls_trst be used here like i.MX27???
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imx21
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-
-# Note above there is 1 tap
-
-# The CPU tap
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x0792611f
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-
-# Create the GDB Target.
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
-
-arm7_9 dcc_downloads enable
diff --git a/openocd-0.10.0/scripts/target/imx25.cfg b/openocd-0.10.0/scripts/target/imx25.cfg
deleted file mode 100644
index bc91278c4efcc4c23970cf54354a2f6829992b16..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/imx25.cfg
+++ /dev/null
@@ -1,46 +0,0 @@
-#
-# imx25 config
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imx25
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists ETBTAPID] } {
- set _ETBTAPID $ETBTAPID
-} else {
- set _ETBTAPID 0x1b900f0f
-}
-jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0x0f -expected-id $_ETBTAPID
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07926041
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id 0x0
-
-if { [info exists SDMATAPID] } {
- set _SDMATAPID $SDMATAPID
-} else {
- set _SDMATAPID 0x0882301d
-}
-jtag newtap $_CHIPNAME sdma -irlen 5 -expected-id $_SDMATAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN \
- -chain-position $_TARGETNAME
-
-# trace setup
-etm config $_TARGETNAME 16 normal full etb
-etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/openocd-0.10.0/scripts/target/imx27.cfg b/openocd-0.10.0/scripts/target/imx27.cfg
deleted file mode 100644
index e5a5035d4fd7ea698ade06b7a7a3d7d809a529a2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/imx27.cfg
+++ /dev/null
@@ -1,53 +0,0 @@
-# page 3-34 of "MCIMC27 Multimedia Applications Processor Reference Manual, Rev 0.3"
-# SRST pulls TRST
-#
-# Without setting these options correctly you'll see all sorts
-# of weird errors, e.g. MOE=0xe, invalid cpsr values, reset
-# failing, etc.
-reset_config trst_and_srst srst_pulls_trst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imx27
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-
-# Note above there are 2 taps
-
-# trace buffer
-if { [info exists ETBTAPID] } {
- set _ETBTAPID $ETBTAPID
-} else {
- set _ETBTAPID 0x1b900f0f
-}
-jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
-
-# The CPU tap
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07926121
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# Create the GDB Target.
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
-# REVISIT what operating environment sets up this virtual address mapping?
-$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 \
- -work-area-size 0x8000 -work-area-backup 1
-# Internal to the chip, there is 45K of SRAM
-#
-
-arm7_9 dcc_downloads enable
-
-# trace setup
-etm config $_TARGETNAME 16 normal full etb
-etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/openocd-0.10.0/scripts/target/imx28.cfg b/openocd-0.10.0/scripts/target/imx28.cfg
deleted file mode 100644
index 4cc3950be8693125a456316daac05b42a08302d6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/imx28.cfg
+++ /dev/null
@@ -1,38 +0,0 @@
-# i.MX28 config file.
-# based off of the imx21.cfg file.
-
-reset_config trst_and_srst
-
-#jtag nTRST and nSRST delay
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imx28
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-
-# Note above there is 1 tap
-
-# The CPU tap
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x079264f3
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-
-# Create the GDB Target.
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
-
-arm7_9 dcc_downloads enable
diff --git a/openocd-0.10.0/scripts/target/imx31.cfg b/openocd-0.10.0/scripts/target/imx31.cfg
deleted file mode 100644
index ca639515f1badc6d60e1301772a7302af5487503..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/imx31.cfg
+++ /dev/null
@@ -1,68 +0,0 @@
-# imx31 config
-#
-
-reset_config trst_and_srst srst_gates_jtag
-
-adapter_nsrst_delay 5
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imx31
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07b3601d
-}
-
-if { [info exists SDMATAPID] } {
- set _SDMATAPID $SDMATAPID
-} else {
- set _SDMATAPID 0x2190101d
-}
-
-if { [info exists ETBTAPID] } {
- set _ETBTAPID $ETBTAPID
-} else {
- set _ETBTAPID 0x2b900f0f
-}
-
-#========================================
-
-jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
-
-# The "SDMA" - <S>mart <DMA> controller debug tap
-# Based on some IO pins - this can be disabled & removed
-# See diagram: 6-14
-# SIGNAL NAME:
-# SJC_MOD - controls multiplexer - disables ARM1136
-# SDMA_BYPASS - disables SDMA -
-#
-# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-
-# No IDCODE for this TAP
-jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0
-
-# Per section 40.17.1, table 40-85 the IR register is 4 bits
-# But this conflicts with Diagram 6-13, "3bits ir and drs"
-jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-
-proc power_restore {} { echo "Sensed power restore. No action." }
-proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
-
-# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
-etm config $_TARGETNAME 16 normal full etb
-etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/openocd-0.10.0/scripts/target/imx35.cfg b/openocd-0.10.0/scripts/target/imx35.cfg
deleted file mode 100644
index 21495c23ccfa7e7fba28f46206e2a5a8b2f853bc..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/imx35.cfg
+++ /dev/null
@@ -1,55 +0,0 @@
-# imx35 config
-#
-
-reset_config trst_and_srst srst_gates_jtag
-jtag_ntrst_delay 100
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imx35
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07b3601d
-}
-
-if { [info exists SDMATAPID] } {
- set _SDMATAPID $SDMATAPID
-} else {
- set _SDMATAPID 0x0882601d
-}
-
-if { [info exists ETBTAPID] } {
- set _ETBTAPID $ETBTAPID
-} else {
- set _ETBTAPID 0x2b900f0f
-}
-
-#========================================
-
-jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETBTAPID
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-
-# No IDCODE for this TAP
-jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0x0 -expected-id 0x0
-
-jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-proc power_restore {} { echo "Sensed power restore. No action." }
-proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
-
-# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
-etm config $_TARGETNAME 16 normal full etb
-etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/openocd-0.10.0/scripts/target/imx51.cfg b/openocd-0.10.0/scripts/target/imx51.cfg
deleted file mode 100644
index d10cf9f5d5b2da3df6bb1ecd3f3fc484696a8a2d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/imx51.cfg
+++ /dev/null
@@ -1,44 +0,0 @@
-# Freescale i.MX51
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imx51
-}
-
-# CoreSight Debug Access Port
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x1ba00477
-}
-
-jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_DAP_TAPID
-
-# SDMA / no IDCODE
-jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf
-
-# SJC
-if { [info exists SJC_TAPID] } {
- set _SJC_TAPID SJC_TAPID
-} else {
- set _SJC_TAPID 0x0190c01d
-}
-
-jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
- -expected-id $_SJC_TAPID -ignore-version
-
-# GDB target: Cortex-A8, using DAP
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
-
-# some TCK tycles are required to activate the DEBUG power domain
-jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
-
-proc imx51_dbginit {target} {
- # General Cortex-A8 debug initialisation
- cortex_a dbginit
-}
-
-$_TARGETNAME configure -event reset-assert-post "imx51_dbginit $_TARGETNAME"
diff --git a/openocd-0.10.0/scripts/target/imx53.cfg b/openocd-0.10.0/scripts/target/imx53.cfg
deleted file mode 100644
index 5ad6473a8ef890fc44107bf9b13575d404e3b359..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/imx53.cfg
+++ /dev/null
@@ -1,44 +0,0 @@
-# Freescale i.MX53
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imx53
-}
-
-# CoreSight Debug Access Port
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x1ba00477
-}
-
-jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_DAP_TAPID
-
-# SDMA / no IDCODE
-jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf
-
-# SJC
-if { [info exists SJC_TAPID] } {
- set _SJC_TAPID SJC_TAPID
-} else {
- set _SJC_TAPID 0x0190d01d
-}
-
-jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
- -expected-id $_SJC_TAPID -ignore-version
-
-# GDB target: Cortex-A8, using DAP
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
-
-# some TCK tycles are required to activate the DEBUG power domain
-jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
-
-proc imx53_dbginit {target} {
- # General Cortex-A8 debug initialisation
- cortex_a dbginit
-}
-
-$_TARGETNAME configure -event reset-assert-post "imx53_dbginit $_TARGETNAME"
diff --git a/openocd-0.10.0/scripts/target/imx6.cfg b/openocd-0.10.0/scripts/target/imx6.cfg
deleted file mode 100644
index 4f7e98afd033e82b7649af714e80c23b48f70d8b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/imx6.cfg
+++ /dev/null
@@ -1,59 +0,0 @@
-# Freescale i.MX6 series single/dual/quad core processor
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imx6
-}
-
-# CoreSight Debug Access Port
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x4ba00477
-}
-
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
- -expected-id $_DAP_TAPID
-
-# SDMA / no IDCODE
-jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
-
-# System JTAG Controller
-if { [info exists SJC_TAPID] } {
- set _SJC_TAPID $SJC_TAPID
-} else {
- set _SJC_TAPID 0x0191c01d
-}
-set _SJC_TAPID2 0x2191c01d
-set _SJC_TAPID3 0x2191e01d
-set _SJC_TAPID4 0x1191c01d
-
-jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
- -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2 \
- -expected-id $_SJC_TAPID3 -expected-id $_SJC_TAPID4
-
-# GDB target: Cortex-A9, using DAP, configuring only one core
-# Base addresses of cores:
-# core 0 - 0x82150000
-# core 1 - 0x82152000
-# core 2 - 0x82154000
-# core 3 - 0x82156000
-set _TARGETNAME $_CHIPNAME.cpu.0
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
- -coreid 0 -dbgbase 0x82150000
-
-# some TCK cycles are required to activate the DEBUG power domain
-jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
-
-proc imx6_dbginit {target} {
- # General Cortex-A8/A9 debug initialisation
- cortex_a dbginit
-}
-
-# Slow speed to be sure it will work
-adapter_khz 1000
-$_TARGETNAME configure -event reset-start { adapter_khz 1000 }
-
-$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
-$_TARGETNAME configure -event gdb-attach { halt }
diff --git a/openocd-0.10.0/scripts/target/is5114.cfg b/openocd-0.10.0/scripts/target/is5114.cfg
deleted file mode 100644
index 31f1aa1aa0b66f6d5c01056e1a242568e36f2608..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/is5114.cfg
+++ /dev/null
@@ -1,46 +0,0 @@
-# script for Insilica IS-5114
-# AKA: Atmel AT76C114 - an ARM946 chip
-# ATMEL sold his product line to Insilica...
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME is5114
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a little endian
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # Force an error until we get a good number.
- set _CPUTAPID 0xffffffff
-}
-
-# jtag speed. We need to stick to 16kHz until we've finished reset.
-adapter_khz 16
-
-reset_config trst_and_srst
-
-# Do not specify a tap id here...
-jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1
-# This is the "arm946" chip.
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x0e -irmask 0xf
-jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1
-
-
-#arm946e-s and
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -event reset-start { adapter_khz 16 }
-$_TARGETNAME configure -event reset-init {
- # We can increase speed now that we know the target is halted.
- adapter_khz 3000
-}
-$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1
diff --git a/openocd-0.10.0/scripts/target/ixp42x.cfg b/openocd-0.10.0/scripts/target/ixp42x.cfg
deleted file mode 100644
index d7b5bf47067eab91970f47253a265cc66fcbf848..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ixp42x.cfg
+++ /dev/null
@@ -1,107 +0,0 @@
-#xscale ixp42x CPU
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME ixp42x
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a bigendian
- set _ENDIAN big
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x19274013
-}
-set _CPUTAPID2 0x19275013
-set _CPUTAPID3 0x19277013
-set _CPUTAPID4 0x29274013
-set _CPUTAPID5 0x29275013
-set _CPUTAPID6 0x29277013
-
-jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3 -expected-id $_CPUTAPID4 -expected-id $_CPUTAPID5 -expected-id $_CPUTAPID6
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
-
-
-# register constants for IXP42x SDRAM controller
-global IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
-global IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
-set IXP425_SDRAM_IR_MODE_SET_CAS2_CMD 0x0000
-set IXP425_SDRAM_IR_MODE_SET_CAS3_CMD 0x0001
-
-global IXP42x_SDRAM_CL3
-global IXP42x_SDRAM_CL2
-set IXP42x_SDRAM_CL3 0x0008
-set IXP42x_SDRAM_CL2 0x0000
-
-global IXP42x_SDRAM_8MB_2Mx32_1BANK
-global IXP42x_SDRAM_16MB_2Mx32_2BANK
-global IXP42x_SDRAM_16MB_4Mx16_1BANK
-global IXP42x_SDRAM_32MB_4Mx16_2BANK
-global IXP42x_SDRAM_32MB_8Mx16_1BANK
-global IXP42x_SDRAM_64MB_8Mx16_2BANK
-global IXP42x_SDRAM_64MB_16Mx16_1BANK
-global IXP42x_SDRAM_128MB_16Mx16_2BANK
-global IXP42x_SDRAM_128MB_32Mx16_1BANK
-global IXP42x_SDRAM_256MB_32Mx16_2BANK
-
-set IXP42x_SDRAM_8MB_2Mx32_1BANK 0x0030
-set IXP42x_SDRAM_16MB_2Mx32_2BANK 0x0031
-set IXP42x_SDRAM_16MB_4Mx16_1BANK 0x0032
-set IXP42x_SDRAM_32MB_4Mx16_2BANK 0x0033
-set IXP42x_SDRAM_32MB_8Mx16_1BANK 0x0010
-set IXP42x_SDRAM_64MB_8Mx16_2BANK 0x0011
-set IXP42x_SDRAM_64MB_16Mx16_1BANK 0x0012
-set IXP42x_SDRAM_128MB_16Mx16_2BANK 0x0013
-set IXP42x_SDRAM_128MB_32Mx16_1BANK 0x0014
-set IXP42x_SDRAM_256MB_32Mx16_2BANK 0x0015
-
-
-# helper function to init SDRAM on IXP42x.
-# SDRAM_CFG: one of IXP42X_SDRAM_xxx
-# REFRESH: refresh counter reload value (integer)
-# CASLAT: 2 or 3
-proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
-
- switch $CASLAT {
- 2 {
- set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL2 ]
- set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
- }
- 3 {
- set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL3 ]
- set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
- }
- default { error [format "unsupported cas latency \"%s\" " $CASLAT] }
- }
- echo [format "\tIXP42x SDRAM Config: 0x%x, Refresh %d " $SDRAM_CFG $REFRESH]
-
- mww 0xCC000000 $SDRAM_CFG ;# SDRAM_CFG: 0x2A: 64MBit, CL3
- mww 0xCC000004 0 ;# disable refresh
- mww 0xCC000008 3 ;# NOP
- sleep 100
- mww 0xCC000004 $REFRESH ;# set refresh counter
- mww 0xCC000008 2 ;# Precharge All Banks
- sleep 100
- mww 0xCC000008 4 ;# Auto Refresh
- mww 0xCC000008 4 ;# Auto Refresh
- mww 0xCC000008 4 ;# Auto Refresh
- mww 0xCC000008 4 ;# Auto Refresh
- mww 0xCC000008 4 ;# Auto Refresh
- mww 0xCC000008 4 ;# Auto Refresh
- mww 0xCC000008 4 ;# Auto Refresh
- mww 0xCC000008 4 ;# Auto Refresh
- mww 0xCC000008 $CASCMD ;# Mode Select CL2/CL3
-}
-
-proc ixp42x_set_bigendian { } {
- reg XSCALE_CTRL 0xF8
-}
-
diff --git a/openocd-0.10.0/scripts/target/k1921vk01t.cfg b/openocd-0.10.0/scripts/target/k1921vk01t.cfg
deleted file mode 100644
index 61b193e39214f84c70fe7e721aad5860b21fcd6f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/k1921vk01t.cfg
+++ /dev/null
@@ -1,55 +0,0 @@
-# K1921VK01T
-# http://niiet.ru/chips/nis?id=354
-
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME k1921vk01t
-}
-
-set _ENDIAN little
-
-# Work-area is a space in RAM used for flash programming
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x10000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- set _CPUTAPID 0x4ba00477
- } {
- # SWD IDCODE
- set _CPUTAPID 0x2ba01477
- }
-}
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-flash bank $_CHIPNAME.flash niietcm4 0 0 0 0 $_TARGETNAME
-
-adapter_khz 2000
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-reset_config srst_nogate
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/k40.cfg b/openocd-0.10.0/scripts/target/k40.cfg
deleted file mode 100644
index 981161156b3becb5bd917ebb70b2ff1ffdccd0ca..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/k40.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Freescale Kinetis K40 devices
-#
-
-set CHIPNAME k40
-source [find target/kx.cfg]
diff --git a/openocd-0.10.0/scripts/target/k60.cfg b/openocd-0.10.0/scripts/target/k60.cfg
deleted file mode 100644
index b9c5e3a1e65adfadaeb962e7ed94dee7837485ea..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/k60.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Freescale Kinetis K60 devices
-#
-
-set CHIPNAME k60
-source [find target/kx.cfg]
diff --git a/openocd-0.10.0/scripts/target/ke02.cfg b/openocd-0.10.0/scripts/target/ke02.cfg
deleted file mode 100644
index 8311920ade99879944f27e59428efb63e8db33e7..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ke02.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Freescale Kinetis KE02 devices
-#
-
-set CHIPNAME ke02
-source [find target/kex.cfg]
diff --git a/openocd-0.10.0/scripts/target/ke04.cfg b/openocd-0.10.0/scripts/target/ke04.cfg
deleted file mode 100644
index f63d77c5e0c222fedbba43ccea3f7de9f81d07e2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ke04.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Freescale Kinetis KE04 devices
-#
-
-set CHIPNAME ke04
-source [find target/kex.cfg]
diff --git a/openocd-0.10.0/scripts/target/ke06.cfg b/openocd-0.10.0/scripts/target/ke06.cfg
deleted file mode 100644
index 3465b8b33ba8d5b687932c0dd8d3b6d946cfde97..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ke06.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Freescale Kinetis KE06 devices
-#
-
-set CHIPNAME ke06
-source [find target/kex.cfg]
diff --git a/openocd-0.10.0/scripts/target/kex.cfg b/openocd-0.10.0/scripts/target/kex.cfg
deleted file mode 100644
index dca8a35ab24686c2b97184519bc4f1d7c5812c8a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/kex.cfg
+++ /dev/null
@@ -1,58 +0,0 @@
-#
-# Freescale Kinetis KE series devices
-#
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME ke
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 1kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x400
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- set _CPUTAPID 0x4ba00477
- } {
- set _CPUTAPID 0x2ba01477
- }
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME kinetis_ke 0 0 0 0 $_TARGETNAME
-
-adapter_khz 1000
-
-reset_config srst_nogate
-
-if {![using_hla]} {
-
- # It is important that "kinetis_ke mdm check_security" is called for
- # 'examine-end' event and not 'eximine-start'. Calling it in 'examine-start'
- # causes "kinetis_ke mdm check_security" to fail the first time openocd
- # calls it when it tries to connect after the CPU has been power-cycled.
- $_CHIPNAME.cpu configure -event examine-end {
- kinetis_ke mdm check_security
- }
-
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/kl25.cfg b/openocd-0.10.0/scripts/target/kl25.cfg
deleted file mode 100644
index 0e716e3ae2b243fd197538e4f7295a8a5cb43fce..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/kl25.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Freescale Kinetis KL25 devices
-#
-
-set CHIPNAME kl25
-source [find target/klx.cfg]
diff --git a/openocd-0.10.0/scripts/target/kl25z_hla.cfg b/openocd-0.10.0/scripts/target/kl25z_hla.cfg
deleted file mode 100644
index e4deac6157f98bcaa7e8acb6dcde3bf7d2ca6789..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/kl25z_hla.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-echo "WARNING: target/kl25z_hla.cfg is deprecated, please switch to target/kl25.cfg"
-source [find target/kl25.cfg]
diff --git a/openocd-0.10.0/scripts/target/kl46.cfg b/openocd-0.10.0/scripts/target/kl46.cfg
deleted file mode 100644
index 70ea273ee3a0f6507c2037a467cfb4650eabf469..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/kl46.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Freescale Kinetis KL46 devices
-#
-
-set CHIPNAME kl46
-source [find target/klx.cfg]
diff --git a/openocd-0.10.0/scripts/target/klx.cfg b/openocd-0.10.0/scripts/target/klx.cfg
deleted file mode 100644
index 0df6612f708d93a9919e6feabf669f0765c784f3..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/klx.cfg
+++ /dev/null
@@ -1,60 +0,0 @@
-#
-# Freescale Kinetis KL series devices
-#
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME klx
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 4kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x1000
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x0bc11477
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
-
-# Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
-# specifies up to 1MHz for VLPR mode.
-adapter_khz 1000
-
-reset_config srst_nogate
-
-if {![using_hla]} {
- # Detect secured MCU or boot lock-up in RESET/WDOG loop
- $_CHIPNAME.cpu configure -event examine-start {
- kinetis mdm check_security
- }
-
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-# Table 5-1. Clock Summary of KL25 Sub-Family Reference Manual
-# specifies up to 24MHz for run mode; Table 17 of Sub-Family Data
-# Sheet rev4 lists 25MHz as the maximum frequency.
-# Uncoment only if VLPR mode is not used
-#$_TARGETNAME configure -event reset-init {
-# adapter_khz 24000
-#}
diff --git a/openocd-0.10.0/scripts/target/ks869x.cfg b/openocd-0.10.0/scripts/target/ks869x.cfg
deleted file mode 100644
index 0f6829c9101af0a69236a339380a4f37733fa3eb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ks869x.cfg
+++ /dev/null
@@ -1,34 +0,0 @@
-# ARM920T CPU
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME ks869x
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x00922f0f
-}
-
-adapter_khz 6000
-
-# jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0
-
-# speed up memory downloads
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
diff --git a/openocd-0.10.0/scripts/target/kx.cfg b/openocd-0.10.0/scripts/target/kx.cfg
deleted file mode 100644
index b39ee3dd18227a9ab7e4ca11256fcbc09985470f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/kx.cfg
+++ /dev/null
@@ -1,54 +0,0 @@
-#
-# Freescale Kinetis Kx series devices
-#
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME kx
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 4kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x1000
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- set _CPUTAPID 0x4ba00477
- } {
- set _CPUTAPID 0x2ba01477
- }
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME kinetis 0 0 0 0 $_TARGETNAME
-
-adapter_khz 1000
-
-reset_config srst_nogate
-
-if {![using_hla]} {
- # Detect secured MCU or boot lock-up in RESET/WDOG loop
- $_CHIPNAME.cpu configure -event examine-start {
- kinetis mdm check_security
- }
-
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/lpc11xx.cfg b/openocd-0.10.0/scripts/target/lpc11xx.cfg
deleted file mode 100644
index 7a65c1f479a108c6fab4fd368e8306c74b012725..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc11xx.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# NXP LPC11xx Cortex-M0 with at least 1kB SRAM
-set CHIPNAME lpc11xx
-set CHIPSERIES lpc1100
-if { ![info exists WORKAREASIZE] } {
- set WORKAREASIZE 0x400
-}
-
-source [find target/lpc1xxx.cfg]
diff --git a/openocd-0.10.0/scripts/target/lpc12xx.cfg b/openocd-0.10.0/scripts/target/lpc12xx.cfg
deleted file mode 100644
index a37c6febca84bf5c11b41697a36835ee913d2d0e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc12xx.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# NXP LPC12xx Cortex-M0 with at least 4kB SRAM
-set CHIPNAME lpc12xx
-set CHIPSERIES lpc1200
-if { ![info exists WORKAREASIZE] } {
- set WORKAREASIZE 0x1000
-}
-
-source [find target/lpc1xxx.cfg]
diff --git a/openocd-0.10.0/scripts/target/lpc13xx.cfg b/openocd-0.10.0/scripts/target/lpc13xx.cfg
deleted file mode 100644
index 3d128c9637e2bc9928415911b0ff41701a6aefac..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc13xx.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# NXP LPC13xx Cortex-M3 with at least 4kB SRAM
-set CHIPNAME lpc13xx
-set CHIPSERIES lpc1300
-if { ![info exists WORKAREASIZE] } {
- set WORKAREASIZE 0x1000
-}
-
-source [find target/lpc1xxx.cfg]
diff --git a/openocd-0.10.0/scripts/target/lpc17xx.cfg b/openocd-0.10.0/scripts/target/lpc17xx.cfg
deleted file mode 100644
index dccf880da87a3a3a7a46d1eef21093e9c9d9b259..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc17xx.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# NXP LPC17xx Cortex-M3 with at least 8kB SRAM
-set CHIPNAME lpc17xx
-set CHIPSERIES lpc1700
-if { ![info exists WORKAREASIZE] } {
- set WORKAREASIZE 0x2000
-}
-
-source [find target/lpc1xxx.cfg]
diff --git a/openocd-0.10.0/scripts/target/lpc1850.cfg b/openocd-0.10.0/scripts/target/lpc1850.cfg
deleted file mode 100644
index a7814037482e1bc5a4748e1963b1f06e88ed7e42..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc1850.cfg
+++ /dev/null
@@ -1,34 +0,0 @@
-source [find target/swj-dp.tcl]
-
-adapter_khz 500
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lpc1850
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-#
-# M3 JTAG mode TAP
-#
-if { [info exists M3_JTAG_TAPID] } {
- set _M3_JTAG_TAPID $M3_JTAG_TAPID
-} else {
- set _M3_JTAG_TAPID 0x4ba00477
-}
-
-swj_newdap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
-
-set _TARGETNAME $_CHIPNAME.m3
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/lpc1xxx.cfg b/openocd-0.10.0/scripts/target/lpc1xxx.cfg
deleted file mode 100644
index 9c10e9f933a3bc1633e22e611d7dfa08a86131ca..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc1xxx.cfg
+++ /dev/null
@@ -1,159 +0,0 @@
-# Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts
-#
-# !!!!!!
-#
-# This file should not be included directly, rather by the lpc11xx.cfg,
-# lpc13xx.cfg, lpc17xx.cfg, etc. which set the needed variables to the
-# appropriate values.
-#
-# !!!!!!
-
-# LPC8xx chips support only SWD transport.
-# LPC11xx chips support only SWD transport.
-# LPC12xx chips support only SWD transport.
-# LPC11Uxx chips support only SWD transports.
-# LPC13xx chips support only SWD transports.
-# LPC17xx chips support both JTAG and SWD transports.
-# LPC40xx chips support both JTAG and SWD transports.
-# Adapt based on what transport is active.
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- error "CHIPNAME not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
-}
-
-if { [info exists CHIPSERIES] } {
- # Validate chip series is supported
- if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" && $CHIPSERIES != "lpc4000" } {
- error "Unsupported LPC1xxx chip series specified."
- }
- set _CHIPSERIES $CHIPSERIES
-} else {
- error "CHIPSERIES not set. Please do not include lpc1xxx.cfg directly, but the specific chip configuration file (lpc11xx.cfg, lpc13xx.cfg, lpc17xx.cfg, etc)."
-}
-
-# After reset, the chip is clocked by an internal RC oscillator.
-# When board-specific code (reset-init handler or device firmware)
-# configures another oscillator and/or PLL0, set CCLK to match; if
-# you don't, then flash erase and write operations may misbehave.
-# (The ROM code doing those updates cares about core clock speed...)
-# CCLK is the core clock frequency in KHz
-if { [info exists CCLK] } {
- # Allow user override
- set _CCLK $CCLK
-} else {
- # LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x)
- if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
- set _CCLK 12000
- } elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
- set _CCLK 4000
- }
-}
-
-if { [info exists CPUTAPID] } {
- # Allow user override
- set _CPUTAPID $CPUTAPID
-} else {
- # LPC8xx/LPC11xx/LPC12xx use a Cortex-M0/M0+ core, LPC13xx/LPC17xx use a Cortex-M3 core, LPC40xx use a Cortex-M4F core.
- if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
- set _CPUTAPID 0x0bb11477
- } elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
- if { [using_jtag] } {
- set _CPUTAPID 0x4ba00477
- } {
- set _CPUTAPID 0x2ba01477
- }
- }
-}
-
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- error "WORKAREASIZE is not set. The $CHIPNAME part is available in several Flash and RAM size configurations. Please set WORKAREASIZE."
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
-# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
-# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
-# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
-# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
-# The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
-# The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000)
-$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
-
-# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
-# The LPC12xx devies have 32/48/64/80/96/128kB of flash memory (at 0x00000000)
-# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)
-# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
-# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
-# The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000)
-#
-# All are compatible with the "lpc1700" variant of the LPC2000 flash driver
-# (same cmd51 destination boundary alignment, and all three support 256 byte
-# transfers).
-#
-# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME lpc2000 0x0 0 0 0 $_TARGETNAME \
- auto $_CCLK calc_checksum
-
-if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
- # Do not remap 0x0000-0x0200 to anything but the flash (i.e. select
- # "User Flash Mode" where interrupt vectors are _not_ remapped,
- # and reside in flash instead).
- #
- # Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
- # Bit Symbol Value Description
- # 1:0 MAP System memory remap
- # 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM.
- # 0x1 User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
- # 0x2 User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash.
- # 31:2 - - Reserved.
- $_TARGETNAME configure -event reset-init {
- mww 0x40048000 0x02
- }
-} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
- # Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
- # "User Flash Mode" where interrupt vectors are _not_ remapped,
- # and reside in flash instead).
- #
- # See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
- # Bit Symbol Value Description Reset
- # value
- # 0 MAP Memory map control. 0
- # 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
- # 1 User mode. The on-chip Flash memory is mapped to address 0.
- # 31:1 - Reserved. The value read from a reserved bit is not defined. NA
- #
- # http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1768&type=user
- $_TARGETNAME configure -event reset-init {
- mww 0x400FC040 0x01
- }
-}
-
-# Run with *real slow* clock by default since the
-# boot rom could have been playing with the PLL, so
-# we have no idea what clock the target is running at.
-adapter_khz 10
-
-# delays on reset lines
-adapter_nsrst_delay 200
-if {[using_jtag]} {
- jtag_ntrst_delay 200
-}
-
-# LPC8xx (Cortex-M0+ core) support SYSRESETREQ
-# LPC11xx/LPC12xx (Cortex-M0 core) support SYSRESETREQ
-# LPC13xx/LPC17xx (Cortex-M3 core) support SYSRESETREQ
-# LPC40xx (Cortex-M4F core) support SYSRESETREQ
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/lpc2103.cfg b/openocd-0.10.0/scripts/target/lpc2103.cfg
deleted file mode 100644
index f55777f56508e9d9d610543b85f3cb3e4434d254..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc2103.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-# NXP LPC2103 ARM7TDMI-S with 32kB flash and 8kB SRAM, clocked with 12MHz crystal
-
-source [find target/lpc2xxx.cfg]
-
-# parameters:
-# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
-# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
-
-proc setup_lpc2103 {core_freq_khz adapter_freq_khz} {
- # 32kB flash and 8kB SRAM
- # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
- setup_lpc2xxx lpc2103 0x4f1f0f0f 0x8000 lpc2000_v2 0x2000 $core_freq_khz $adapter_freq_khz
-}
-
-proc init_targets {} {
- # default to core clocked with 12MHz crystal
- echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-
- # setup_lpc2103 <core_freq_khz> <adapter_freq_khz>
- setup_lpc2103 12000 1500
-}
diff --git a/openocd-0.10.0/scripts/target/lpc2124.cfg b/openocd-0.10.0/scripts/target/lpc2124.cfg
deleted file mode 100644
index 02517381af8e9302a1082f88c1a0f51867ba42f0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc2124.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-# NXP LPC2124 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal
-
-source [find target/lpc2xxx.cfg]
-
-# parameters:
-# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
-# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
-
-proc setup_lpc2124 {core_freq_khz adapter_freq_khz} {
- # 256kB flash and 16kB SRAM
- # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
- setup_lpc2xxx lpc2124 0x4f1f0f0f 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
-}
-
-proc init_targets {} {
- # default to core clocked with 12MHz crystal
- echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-
- # setup_lpc2124 <core_freq_khz> <adapter_freq_khz>
- setup_lpc2124 12000 1500
-}
diff --git a/openocd-0.10.0/scripts/target/lpc2129.cfg b/openocd-0.10.0/scripts/target/lpc2129.cfg
deleted file mode 100644
index 2c33cde310f5f6913e8f6b73e30006dc9f8c6a38..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc2129.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-# NXP LPC2129 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal
-
-source [find target/lpc2xxx.cfg]
-
-# parameters:
-# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
-# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
-
-proc setup_lpc2129 {core_freq_khz adapter_freq_khz} {
- # 256kB flash and 16kB SRAM
- # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
- setup_lpc2xxx lpc2129 0xcf1f0f0f 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
-}
-
-proc init_targets {} {
- # default to core clocked with 12MHz crystal
- echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-
- # setup_lpc2129 <core_freq_khz> <adapter_freq_khz>
- setup_lpc2129 12000 1500
-}
diff --git a/openocd-0.10.0/scripts/target/lpc2148.cfg b/openocd-0.10.0/scripts/target/lpc2148.cfg
deleted file mode 100644
index f3a2011a81e1c91f593c7d4652dc838680562748..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc2148.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-# NXP LPC2148 ARM7TDMI-S with 512kB flash (12kB used by bootloader) and 40kB SRAM (8kB for USB DMA), clocked with 12MHz crystal
-
-source [find target/lpc2xxx.cfg]
-
-# parameters:
-# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
-# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
-
-proc setup_lpc2148 {core_freq_khz adapter_freq_khz} {
- # 500kB flash and 32kB SRAM
- # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
- setup_lpc2xxx lpc2148 "0x3f0f0f0f 0x4f1f0f0f" 0x7d000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz
-}
-
-proc init_targets {} {
- # default to core clocked with 12MHz crystal
- echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-
- # setup_lpc2148 <core_freq_khz> <adapter_freq_khz>
- setup_lpc2148 12000 1500
-}
diff --git a/openocd-0.10.0/scripts/target/lpc2294.cfg b/openocd-0.10.0/scripts/target/lpc2294.cfg
deleted file mode 100644
index 83d595deb57f8bb87e85a681e86781720a47740a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc2294.cfg
+++ /dev/null
@@ -1,23 +0,0 @@
-# NXP LPC2294 ARM7TDMI-S with 256kB flash and 16kB SRAM, clocked with 12MHz crystal
-
-source [find target/lpc2xxx.cfg]
-
-# parameters:
-# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
-# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
-
-proc setup_lpc2294 {core_freq_khz adapter_freq_khz} {
- # 256kB flash and 16kB SRAM
- # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
-
- # !! TAPID unknown !!
- setup_lpc2xxx lpc2294 0xffffffff 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
-}
-
-proc init_targets {} {
- # default to core clocked with 12MHz crystal
- echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
-
- # setup_lpc2294 <core_freq_khz> <adapter_freq_khz>
- setup_lpc2294 12000 1500
-}
diff --git a/openocd-0.10.0/scripts/target/lpc2378.cfg b/openocd-0.10.0/scripts/target/lpc2378.cfg
deleted file mode 100644
index 0b66b82557452d39eda19d0357556275924cf42f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc2378.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-# NXP LPC2378 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 56kB SRAM (16kB for ETH, 8kB for DMA), clocked with 4MHz internal oscillator
-
-source [find target/lpc2xxx.cfg]
-
-# parameters:
-# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
-# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
-
-proc setup_lpc2378 {core_freq_khz adapter_freq_khz} {
- # 504kB flash and 32kB SRAM
- # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
- setup_lpc2xxx lpc2378 0x4f1f0f0f 0x7e000 lpc2000_v2 0x8000 $core_freq_khz $adapter_freq_khz
-}
-
-proc init_targets {} {
- # default to core clocked with 4MHz internal oscillator
- echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
-
- # setup_lpc2378 <core_freq_khz> <adapter_freq_khz>
- setup_lpc2378 4000 500
-}
diff --git a/openocd-0.10.0/scripts/target/lpc2460.cfg b/openocd-0.10.0/scripts/target/lpc2460.cfg
deleted file mode 100644
index 69fdc4aafcb43f57230f46063aabccc178f3f4b6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc2460.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-# NXP LPC2460 ARM7TDMI-S with 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator
-
-source [find target/lpc2xxx.cfg]
-
-# parameters:
-# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
-# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
-
-proc setup_lpc2460 {core_freq_khz adapter_freq_khz} {
- # 64kB SRAM
- # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
- setup_lpc2xxx lpc2460 0x4f1f0f0f 0 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz
-}
-
-proc init_targets {} {
- # default to core clocked with 4MHz internal oscillator
- echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
-
- # setup_lpc2460 <core_freq_khz> <adapter_freq_khz>
- setup_lpc2460 4000 500
-}
diff --git a/openocd-0.10.0/scripts/target/lpc2478.cfg b/openocd-0.10.0/scripts/target/lpc2478.cfg
deleted file mode 100644
index 48e5bdf3f0af74e244062bc5dcb4bafcc0c575f3..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc2478.cfg
+++ /dev/null
@@ -1,21 +0,0 @@
-# NXP LPC2478 ARM7TDMI-S with 512kB flash (8kB used by bootloader) and 98kB SRAM (16kB for ETH, 16kB for DMA, 2kB for RTC), clocked with 4MHz internal oscillator
-
-source [find target/lpc2xxx.cfg]
-
-# parameters:
-# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
-# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
-
-proc setup_lpc2478 {core_freq_khz adapter_freq_khz} {
- # 504kB flash and 64kB SRAM
- # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
- setup_lpc2xxx lpc2478 0x4f1f0f0f 0x7e000 lpc2000_v2 0x10000 $core_freq_khz $adapter_freq_khz
-}
-
-proc init_targets {} {
- # default to core clocked with 4MHz internal oscillator
- echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
-
- # setup_lpc2478 <core_freq_khz> <adapter_freq_khz>
- setup_lpc2478 4000 500
-}
diff --git a/openocd-0.10.0/scripts/target/lpc2900.cfg b/openocd-0.10.0/scripts/target/lpc2900.cfg
deleted file mode 100644
index 53677873abd8785187f1b4fd1c918dd5ea8af793..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc2900.cfg
+++ /dev/null
@@ -1,66 +0,0 @@
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lpc2900
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x0596802B
-}
-
-if { [info exists HAS_ETB] } {
-} else {
- # Set default (no ETB).
- # Show a warning, because this should have been configured explicitely.
- set HAS_ETB 0
- # TODO: warning?
-}
-
-if { [info exists ETBTAPID] } {
- set _ETBTAPID $ETBTAPID
-} else {
- set _ETBTAPID 0x1B900F0F
-}
-
-# TRST and SRST both exist, and can be controlled independently
-reset_config trst_and_srst separate
-
-# Define the _TARGETNAME
-set _TARGETNAME $_CHIPNAME.cpu
-
-# Include the ETB tap controller if asked for.
-# Has to be done manually for newer devices (not an "old" LPC2917/2919).
-if { $HAS_ETB == 1 } {
- # Clear the HAS_ETB flag. Must be set again for a new tap in the chain.
- set HAS_ETB 0
-
- # Add the ETB tap controller and the ARM9 core debug tap
- jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID
- jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
- # Create the ".cpu" target
- target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
-
- # Configure ETM and ETB
- etm config $_TARGETNAME 8 normal full etb
- etb config $_TARGETNAME $_CHIPNAME.etb
-
-} else {
- # Add the ARM9 core debug tap
- jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
- # Create the ".cpu" target
- target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
-}
-
-arm7_9 dbgrq enable
-arm7_9 dcc_downloads enable
-
-# Flash bank configuration:
-# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>
-# Flash base address, total flash size, and number of sectors are all configured automatically.
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
diff --git a/openocd-0.10.0/scripts/target/lpc2xxx.cfg b/openocd-0.10.0/scripts/target/lpc2xxx.cfg
deleted file mode 100644
index 11f1c48bc15d0add63d19dc524b0dcd300de12ef..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc2xxx.cfg
+++ /dev/null
@@ -1,44 +0,0 @@
-# Common setup for the LPC2xxx parts
-
-# parameters:
-# - chip_name - name of the chip, e.g. lpc2103
-# - cputapids - TAP IDs of the core, should be quoted if more than one, e.g. 0x4f1f0f0f or "0x3f0f0f0f 0x4f1f0f0f"
-# - flash_size - size of on-chip flash (available for code, not including the bootloader) in bytes, e.g. 0x8000
-# - flash_variant - "type" of LPC2xxx device, lpc2000_v1 (LPC22xx and older LPC21xx) or lpc2000_v2 (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
-# - workarea_size - size of work-area in RAM for flashing procedures, must not exceed the size of RAM available at 0x40000000, e.g. 0x2000
-# - core_freq_khz - frequency of core in kHz during flashing, usually equal to connected crystal or internal oscillator, e.g. 12000
-# - adapter_freq_khz - frequency of debug adapter in kHz, should be 8x slower than core_freq_khz, e.g. 1000
-
-proc setup_lpc2xxx {chip_name cputapids flash_size flash_variant workarea_size core_freq_khz adapter_freq_khz} {
- reset_config trst_and_srst
-
- # reset delays
- adapter_nsrst_delay 100
- jtag_ntrst_delay 100
-
- adapter_khz $adapter_freq_khz
-
- foreach i $cputapids {
- append expected_ids "-expected-id " $i " "
- }
-
- eval "jtag newtap $chip_name cpu -irlen 4 -ircapture 0x1 -irmask 0xf $expected_ids"
-
- global _TARGETNAME
- set _TARGETNAME $chip_name.cpu
- target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
-
- $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size $workarea_size -work-area-backup 0
-
- if { $flash_size > 0 } {
- # flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
- set _FLASHNAME $chip_name.flash
- flash bank $_FLASHNAME lpc2000 0x0 $flash_size 0 0 $_TARGETNAME $flash_variant $core_freq_khz calc_checksum
- }
-}
-
-proc init_targets {} {
- # FIX!!! read out CPUTAPID here and choose right setup. In addition to the
- # CPUTAPID some querying of the target would be required.
- return -error "This is a generic LPC2xxx configuration file, use a specific target file."
-}
diff --git a/openocd-0.10.0/scripts/target/lpc3131.cfg b/openocd-0.10.0/scripts/target/lpc3131.cfg
deleted file mode 100644
index 27c1f67578ff5dc56138f85214915935c34c8afb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc3131.cfg
+++ /dev/null
@@ -1,76 +0,0 @@
-######################################
-# Target: NXP lpc3131
-######################################
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lpc3131
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# ARM926EJS core
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07926f0f
-}
-
-# Scan Tap
-# Wired to seperate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module
-# JTAGSEL pin must be 0 to activate, which reassigns arm tdo to a pass through.
-if { [info exists SJCTAPID] } {
- set _SJCTAPID $SJCTAPID
-} else {
- set _SJCTAPID 0x1541E02B
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-##################################################################
-# various symbol definitions, to avoid hard-wiring addresses
-##################################################################
-
-global lpc313x
-set lpc313x [ dict create ]
-
-# Physical addresses for controllers and memory
-dict set lpc313x sram0 0x11028000
-dict set lpc313x sram1 0x11040000
-dict set lpc313x uart 0x15001000
-dict set lpc313x cgu 0x13004000
-dict set lpc313x ioconfig 0x13003000
-dict set lpc313x sysconfig 0x13002800
-dict set lpc313x wdt 0x13002400
-
-##################################################################
-# Target configuration
-##################################################################
-
-adapter_nsrst_delay 1000
-jtag_ntrst_delay 0
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME invoke-event halted
-
-$_TARGETNAME configure -work-area-phys [dict get $lpc313x sram0] -work-area-size 0x30000 -work-area-backup 0
-
-$_TARGETNAME configure -event reset-init {
- echo "\nRunning reset init script for LPC3131\n"
- halt
- wait_halt
- reg cpsr 0xa00000d3 ;#Supervisor mode
- reg pc 0x11029000
- poll
- sleep 500
-}
-
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
diff --git a/openocd-0.10.0/scripts/target/lpc3250.cfg b/openocd-0.10.0/scripts/target/lpc3250.cfg
deleted file mode 100644
index 14bb0f61ba6d0b4d3d17249f34dd47909140780f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc3250.cfg
+++ /dev/null
@@ -1,43 +0,0 @@
-# lpc3250 config
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lpc3250
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x17900f0f
-}
-
-if { [info exists CPUTAPID_REV_A0] } {
- set _CPUTAPID_REV_A0 $CPUTAPID_REV_A0
-} else {
- set _CPUTAPID_REV_A0 0x17926f0f
-}
-
-if { [info exists SJCTAPID] } {
- set _SJCTAPID $SJCTAPID
-} else {
- set _SJCTAPID 0x1b900f0f
-}
-
-jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_SJCTAPID
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID \
- -expected-id $_CPUTAPID_REV_A0
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian little -chain-position $_TARGETNAME -work-area-phys 0x00000000 -work-area-size 0x7d0000 -work-area-backup 0
-
-proc power_restore {} { echo "Sensed power restore. No action." }
-proc srst_deasserted {} { echo "Sensed nSRST deasserted. No action." }
diff --git a/openocd-0.10.0/scripts/target/lpc40xx.cfg b/openocd-0.10.0/scripts/target/lpc40xx.cfg
deleted file mode 100644
index 606cda5c174402e849b3aa3de7ad6bfb824fad11..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc40xx.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-# NXP LPC40xx Cortex-M4F with at least 16kB SRAM
-set CHIPNAME lpc40xx
-set CHIPSERIES lpc4000
-if { ![info exists WORKAREASIZE] } {
- set WORKAREASIZE 0x4000
-}
-
-source [find target/lpc1xxx.cfg]
diff --git a/openocd-0.10.0/scripts/target/lpc4350.cfg b/openocd-0.10.0/scripts/target/lpc4350.cfg
deleted file mode 100644
index 4e23ffb0dd8111a53467f12789fbab7eceae9023..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc4350.cfg
+++ /dev/null
@@ -1,70 +0,0 @@
-source [find target/swj-dp.tcl]
-
-adapter_khz 500
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lpc4350
-}
-
-#
-# M4 JTAG mode TAP
-#
-if { [info exists M4_JTAG_TAPID] } {
- set _M4_JTAG_TAPID $M4_JTAG_TAPID
-} else {
- set _M4_JTAG_TAPID 0x4ba00477
-}
-
-#
-# M4 SWD mode TAP
-#
-if { [info exists M4_SWD_TAPID] } {
- set _M4_SWD_TAPID $M4_SWD_TAPID
-} else {
- set _M4_SWD_TAPID 0x2ba01477
-}
-
-if { [using_jtag] } {
- set _M4_TAPID $_M4_JTAG_TAPID
-} {
- set _M4_TAPID $_M4_SWD_TAPID
-}
-
-#
-# M0 TAP
-#
-if { [info exists M0_JTAG_TAPID] } {
- set _M0_JTAG_TAPID $M0_JTAG_TAPID
-} else {
- set _M0_JTAG_TAPID 0x0ba01477
-}
-
-swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_M4_TAPID
-target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
-
-if { [using_jtag] } {
- swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_M0_JTAG_TAPID
- target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
-}
-
-# LPC4350 has 96+32 KB SRAM
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x20000
-}
-$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
- -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-if {![using_hla]} {
- # on this CPU we should use VECTRESET to perform a soft reset and
- # manually reset the periphery
- # SRST or SYSRESETREQ disable the debug interface for the time of
- # the reset and will not fit our requirements for a consistent debug
- # session
- cortex_m reset_config vectreset
-}
diff --git a/openocd-0.10.0/scripts/target/lpc4357.cfg b/openocd-0.10.0/scripts/target/lpc4357.cfg
deleted file mode 100644
index 1a15ad62334013c67ec237060a8dfc5d38aa1f95..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc4357.cfg
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# NXP LPC4357
-#
-
-if { ![info exists CHIPNAME] } {
- set CHIPNAME lpc4357
-}
-set WORKAREASIZE 0x8000
-source [find target/lpc4350.cfg]
-
-flash bank $_CHIPNAME.flasha lpc2000 0x1A000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 204000 calc_checksum
-flash bank $_CHIPNAME.flashb lpc2000 0x1B000000 0x80000 0 0 $_CHIPNAME.m4 lpc4300 204000 calc_checksum
diff --git a/openocd-0.10.0/scripts/target/lpc4370.cfg b/openocd-0.10.0/scripts/target/lpc4370.cfg
deleted file mode 100644
index 67bff0adcacd47722d35b6de030454ac3e42b9b5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc4370.cfg
+++ /dev/null
@@ -1,85 +0,0 @@
-#
-# NXP LPC4370 - 1x ARM Cortex-M4 + 2x ARM Cortex-M0 @ up to 204 MHz each
-#
-
-adapter_khz 500
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lpc4370
-}
-
-#
-# M4 JTAG mode TAP
-#
-if { [info exists M4_JTAG_TAPID] } {
- set _M4_JTAG_TAPID $M4_JTAG_TAPID
-} else {
- set _M4_JTAG_TAPID 0x4ba00477
-}
-
-#
-# M4 SWD mode TAP
-#
-if { [info exists M4_SWD_TAPID] } {
- set _M4_SWD_TAPID $M4_SWD_TAPID
-} else {
- set _M4_SWD_TAPID 0x2ba01477
-}
-
-source [find target/swj-dp.tcl]
-
-if { [using_jtag] } {
- set _M4_TAPID $_M4_JTAG_TAPID
-} else {
- set _M4_TAPID $_M4_SWD_TAPID
-}
-
-#
-# M0 TAP
-#
-if { [info exists M0_JTAG_TAPID] } {
- set _M0_JTAG_TAPID $M0_JTAG_TAPID
-} else {
- set _M0_JTAG_TAPID 0x0ba01477
-}
-
-swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_M4_TAPID
-
-target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
-
-# LPC4370 has 96+32 KB contiguous SRAM
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x20000
-}
-$_CHIPNAME.m4 configure -work-area-phys 0x10000000 \
- -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-if { [using_jtag] } {
- jtag newtap $_CHIPNAME m0app -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_M0_JTAG_TAPID
- jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_M0_JTAG_TAPID
-
- target create $_CHIPNAME.m0app cortex_m -chain-position $_CHIPNAME.m0app
- target create $_CHIPNAME.m0sub cortex_m -chain-position $_CHIPNAME.m0sub
-
- # 32+8+32 KB SRAM
- $_CHIPNAME.m0app configure -work-area-phys 0x10080000 \
- -work-area-size 0x92000 -work-area-backup 0
-
- # 16+2 KB M0 subsystem SRAM
- $_CHIPNAME.m0sub configure -work-area-phys 0x18000000 \
- -work-area-size 0x4800 -work-area-backup 0
-
- # Default to the Cortex-M4
- targets $_CHIPNAME.m4
-}
-
-if { ![using_hla] } {
- cortex_m reset_config vectreset
-}
diff --git a/openocd-0.10.0/scripts/target/lpc8xx.cfg b/openocd-0.10.0/scripts/target/lpc8xx.cfg
deleted file mode 100644
index e0e210b967782715f836cd1be225ed0beb210ab1..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/lpc8xx.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-# NXP LPC8xx Cortex-M0+ with at least 1kB SRAM
-if { ![info exists CHIPNAME] } {
- set CHIPNAME lpc8xx
-}
-set CHIPSERIES lpc800
-if { ![info exists WORKAREASIZE] } {
- set WORKAREASIZE 0x400
-}
-
-source [find target/lpc1xxx.cfg]
diff --git a/openocd-0.10.0/scripts/target/mc13224v.cfg b/openocd-0.10.0/scripts/target/mc13224v.cfg
deleted file mode 100644
index 27ac8c3b29b3a0acf9e256b8340878076dfadbb8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/mc13224v.cfg
+++ /dev/null
@@ -1,54 +0,0 @@
-source [find bitsbytes.tcl]
-source [find cpu/arm/arm7tdmi.tcl]
-source [find memory.tcl]
-source [find mmr_helpers.tcl]
-
-set CHIP_MAKER freescale
-set CHIP_FAMILY mc1322x
-set CHIP_NAME mc13224
-set N_RAM 1
-set RAM(0,BASE) 0x00400000
-set RAM(0,LEN) 0x18000
-set RAM(0,HUMAN) "internal SRAM"
-set RAM(0,TYPE) "ram"
-set RAM(0,RWX) $RWX_RWX
-set RAM(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
-
-# I AM LAZY... I create 1 region for all MMRs.
-set N_MMREGS 1
-set MMREGS(0,CHIPSELECT) -1
-set MMREGS(0,BASE) 0x80000000
-set MMREGS(0,LEN) 0x00030000
-set MMREGS(0,HUMAN) "mm-regs"
-set MMREGS(0,TYPE) "mmr"
-set MMREGS(0,RWX) $RWX_RW
-set MMREGS(0,ACCESS_WIDTH) $ACCESS_WIDTH_ANY
-
-set N_XMEM 0
-
-set _CHIPNAME mc13224v
-set _CPUTAPID 0x1f1f001d
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-reset_config srst_only
-jtag_ntrst_delay 200
-
-# rclk hasn't been working well. This maybe the mc13224v or something else.
-#adapter_khz 2000
-adapter_khz 2000
-
-######################
-# Target configuration
-######################
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -chain-position $_TARGETNAME
-
-# Internal sram memory
-$_TARGETNAME configure -work-area-phys 0x00408000 \
- -work-area-size 0x1000 \
- -work-area-backup 1
-
-# flash support is pending (should be straightforward to implement)
-#flash bank mc1322x 0 0 0 0 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/mdr32f9q2i.cfg b/openocd-0.10.0/scripts/target/mdr32f9q2i.cfg
deleted file mode 100644
index 804ac1aefb2e3c6577d64d8f90e23a46cae03cc5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/mdr32f9q2i.cfg
+++ /dev/null
@@ -1,62 +0,0 @@
-# MDR32F9Q2I (1986ВЕ92У)
-# http://milandr.ru/index.php?mact=Products,cntnt01,details,0&cntnt01productid=57&cntnt01returnid=68
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME mdr32f9q2i
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x8000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- set _CPUTAPID 0x4ba00477
- } {
- # SWD IDCODE
- set _CPUTAPID 0x2ba01477
- }
-}
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# can't handle overlapping memory regions
-if { [info exists IMEMORY] && [string equal $IMEMORY true] } {
- flash bank ${_CHIPNAME}_info.flash mdr 0x08000000 0x01000 0 0 $_TARGETNAME 1 1 4
-} else {
- flash bank $_CHIPNAME.flash mdr 0x08000000 0x20000 0 0 $_TARGETNAME 0 32 4
-}
-
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/nds32v2.cfg b/openocd-0.10.0/scripts/target/nds32v2.cfg
deleted file mode 100644
index bbf6b3aee2f55d382a9d1782a505e6dcf2dce182..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/nds32v2.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Andes Core
-#
-# http://www.andestech.com
-#
-
-jtag newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME nds32_v2 -endian little -chain-position $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/nds32v3.cfg b/openocd-0.10.0/scripts/target/nds32v3.cfg
deleted file mode 100644
index 0c267cd7528db91d534e33fba936fa062c5baa13..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/nds32v3.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Andes Core
-#
-# http://www.andestech.com
-#
-
-jtag newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME nds32_v3 -endian little -chain-position $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/nds32v3m.cfg b/openocd-0.10.0/scripts/target/nds32v3m.cfg
deleted file mode 100644
index 169e3d11957836ff8fd5dd9a53c65e1bf8cdcf93..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/nds32v3m.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Andes Core
-#
-# http://www.andestech.com
-#
-
-jtag newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME nds32_v3m -endian little -chain-position $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/nrf51.cfg b/openocd-0.10.0/scripts/target/nrf51.cfg
deleted file mode 100644
index 280dd4ff365609d56cddc62a82d565bf817f1e8f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/nrf51.cfg
+++ /dev/null
@@ -1,60 +0,0 @@
-#
-# script for Nordic nRF51 series, a Cortex-M0 chip
-#
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME nrf51
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 16kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x4000
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x0bb11477
-}
-
-swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-if {![using_hla]} {
- # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
- cortex_m reset_config sysresetreq
-}
-
-flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME
-flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
-
-#
-# The chip should start up from internal 16Mhz RC, so setting adapter
-# clock to 1Mhz should be OK
-#
-adapter_khz 1000
-
-proc enable_all_ram {} {
- # nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
- # are reliably enabled after reset on some revisions (contrary to spec.) So after
- # resetting we enable all banks via the RAMON register
- mww 0x40000524 0xF
-}
-$_TARGETNAME configure -event reset-end { enable_all_ram }
diff --git a/openocd-0.10.0/scripts/target/nrf51_stlink.tcl b/openocd-0.10.0/scripts/target/nrf51_stlink.tcl
deleted file mode 100644
index 7e23c5a74438c7f18045f34a7261098516bf908d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/nrf51_stlink.tcl
+++ /dev/null
@@ -1,2 +0,0 @@
-echo "WARNING: target/nrf51_stlink.cfg is deprecated, please switch to target/nrf51.cfg"
-source [find target/nrf51.cfg]
diff --git a/openocd-0.10.0/scripts/target/nrf52.cfg b/openocd-0.10.0/scripts/target/nrf52.cfg
deleted file mode 100644
index c1cbf1a21de711c844d232433f00ef6e6ed5cf4e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/nrf52.cfg
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# Nordic nRF52 series: ARM Cortex-M4 @ 64 MHz
-#
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME nrf52
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x2ba01477
-}
-
-swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
-adapter_khz 10000
-
-if { ![using_hla] } {
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/nuc910.cfg b/openocd-0.10.0/scripts/target/nuc910.cfg
deleted file mode 100644
index 29cd29f35c472b46b809a8ba1c8636e848e7a0cb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/nuc910.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# Nuvoton nuc910 (previously W90P910) based soc
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME nuc910
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # set useful default
- set _CPUTAPID 0x07926f0f
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/numicro.cfg b/openocd-0.10.0/scripts/target/numicro.cfg
deleted file mode 100644
index 13d965432bf50faaa9eb9a39ce18e7b1944964d6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/numicro.cfg
+++ /dev/null
@@ -1,60 +0,0 @@
-# script for Nuvoton MuMicro Cortex-M0 Series
-
-# Adapt based on what transport is active.
-source [find target/swj-dp.tcl]
-
-# Set Chipname
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME NuMicro
-}
-
-# SWD DP-ID Nuvoton NuMicro Cortex-M0 has SWD Transport only.
-if { [info exists CPUDAPID] } {
- set _CPUDAPID $CPUDAPID
-} else {
- set _CPUDAPID 0x0BB11477
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 2kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x800
-}
-
-
-# Debug Adapter Target Settings
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# flash bank <name> numicro <base> <size(autodetect,set to 0)> 0 0 <target#>
-#set _FLASHNAME $_CHIPNAME.flash
-#flash bank $_FLASHNAME numicro 0 $_FLASHSIZE 0 0 $_TARGETNAME
-# flash size will be probed
-set _FLASHNAME $_CHIPNAME.flash_aprom
-flash bank $_FLASHNAME numicro 0x00000000 0 0 0 $_TARGETNAME
-set _FLASHNAME $_CHIPNAME.flash_data
-flash bank $_FLASHNAME numicro 0x0001F000 0 0 0 $_TARGETNAME
-set _FLASHNAME $_CHIPNAME.flash_ldrom
-flash bank $_FLASHNAME numicro 0x00100000 0 0 0 $_TARGETNAME
-set _FLASHNAME $_CHIPNAME.flash_config
-flash bank $_FLASHNAME numicro 0x00300000 0 0 0 $_TARGETNAME
-
-# set default SWCLK frequency
-adapter_khz 1000
-
-# set default srst setting "none"
-reset_config none
-
-# HLA doesn't have cortex_m commands
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/omap2420.cfg b/openocd-0.10.0/scripts/target/omap2420.cfg
deleted file mode 100644
index 7968ad1e82d927919b8c4e99902893657e1f51ab..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/omap2420.cfg
+++ /dev/null
@@ -1,61 +0,0 @@
-# Texas Instruments OMAP 2420
-# http://www.ti.com/omap
-# as seen in Nokia N8x0 tablets
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME omap2420
-}
-
-# NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
-reset_config srst_nogate
-
-# Subsidiary TAP: ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6).
-jtag newtap $_CHIPNAME iva -irlen 4 -disable
-
-# Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2).
-jtag newtap $_CHIPNAME dsp -irlen 38 -disable
-
-# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
-if { [info exists ETB_TAPID] } {
- set _ETB_TAPID $ETB_TAPID
-} else {
- set _ETB_TAPID 0x2b900f0f
-}
-jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETB_TAPID
-
-# Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
-if { [info exists CPU_TAPID] } {
- set _CPU_TAPID $CPU_TAPID
-} else {
- set _CPU_TAPID 0x07b3602f
-}
-jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID
-
-# Primary TAP: ICEpick-B (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x01ce4801
-}
-jtag newtap $_CHIPNAME jrc -irlen 2 -expected-id $_JRC_TAPID
-
-# GDB target: the ARM.
-set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
-
-# scratch: framebuffer, may be initially unavailable in some chips
-$_TARGETNAME configure -work-area-phys 0x40210000
-$_TARGETNAME configure -work-area-size 0x00081000
-$_TARGETNAME configure -work-area-backup 0
-
-# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
-etm config $_TARGETNAME 16 normal full etb
-etb config $_TARGETNAME $_CHIPNAME.etb
-
-# RM_RSTCTRL_WKUP.RST.GS - Trigger a global software reset, and
-# give it a chance to finish before we talk to the chip again.
-set RM_RSTCTRL_WKUP 0x48008450
-$_TARGETNAME configure -event reset-assert \
- "halt; $_TARGETNAME mww $RM_RSTCTRL_WKUP 2; sleep 200"
diff --git a/openocd-0.10.0/scripts/target/omap3530.cfg b/openocd-0.10.0/scripts/target/omap3530.cfg
deleted file mode 100644
index c2929d1c4079ba8e7cb7a213514baa7f1e55ff7e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/omap3530.cfg
+++ /dev/null
@@ -1,74 +0,0 @@
-# TI OMAP3530
-# http://focus.ti.com/docs/prod/folders/print/omap3530.html
-# Other OMAP3 chips remove DSP and/or the OpenGL support
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME omap3530
-}
-
-# ICEpick-C ... used to route Cortex, DSP, and more not shown here
-source [find target/icepick.cfg]
-
-# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
-jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
-
-# Subsidiary TAP: CoreSight Debug Access Port (DAP)
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x0b6d602f
-}
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 3"
-
-# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x0b7ae02f
-}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
- -expected-id $_JRC_TAPID
-
-# GDB target: Cortex-A8, using DAP
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
-
-# SRAM: 64K at 0x4020.0000; use the first 16K
-$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
-
-###################
-
-# the reset sequence is event-driven
-# and kind of finicky...
-
-# some TCK tycles are required to activate the DEBUG power domain
-jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
-
-# have the DAP "always" be active
-jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
-
-proc omap3_dbginit {target} {
- # General Cortex-A8 debug initialisation
- cortex_a dbginit
- # Enable DBGU signal for OMAP353x
- $target mww phys 0x5401d030 0x00002000
-}
-
-# be absolutely certain the JTAG clock will work with the worst-case
-# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
-# OK to speed up *after* PLL and clock tree setup.
-adapter_khz 1000
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 }
-
-# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
-# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
-# would issue. RST_DPLL3 (4) is a cold reset.
-set PRM_RSTCTRL 0x48307250
-$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"
-
-$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"
diff --git a/openocd-0.10.0/scripts/target/omap4430.cfg b/openocd-0.10.0/scripts/target/omap4430.cfg
deleted file mode 100644
index 6f3525aed78856c10e1fd0c134160f29713a6271..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/omap4430.cfg
+++ /dev/null
@@ -1,127 +0,0 @@
-# OMAP4430
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME omap4430
-}
-
-
-# Although the OMAP4430 supposedly has an ICEpick-D, only the
-# ICEpick-C router commands seem to work.
-# See http://processors.wiki.ti.com/index.php/ICEPICK
-source [find target/icepick.cfg]
-
-
-#
-# A9 DAP
-#
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x3BA00477
-}
-
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 9"
-
-
-#
-# M3 DAPs, one per core
-#
-if { [info exists M3_DAP_TAPID] } {
- set _M3_DAP_TAPID $M3_DAP_TAPID
-} else {
- set _M3_DAP_TAPID 0x4BA00477
-}
-
-jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m31_dap -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 5"
-
-jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m30_dap -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 4"
-
-
-#
-# ICEpick-D JRC (JTAG route controller)
-#
-if { [info exists JRC_TAPID] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x3b95c02f
- set _JRC_TAPID2 0x1b85202f
-}
-
-# PandaBoard REV EA1 (PEAP platforms)
-if { [info exists JRC_TAPID2] } {
- set _JRC_TAPID2 $JRC_TAPID2
-} else {
- set _JRC_TAPID2 0x1b85202f
-}
-
-
-
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
- -expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2
-
-# Required by ICEpick to power-up the debug domain
-jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
-
-
-#
-# GDB target: Cortex-A9, using DAP
-#
-# The debugger can connect to either core of the A9, but currently
-# not both simultaneously. Change -coreid to 1 to connect to the
-# second core.
-#
-set _TARGETNAME $_CHIPNAME.cpu
-
-# APB DBGBASE reads 0x80040000, but this points to an empty ROM table.
-# 0x80000000 is cpu0 coresight region
-#
-#
-# CORTEX_A8_PADDRDBG_CPU_SHIFT 13
-# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
-
-set _coreid 0
-set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
-echo "Using dbgbase = [format 0x%x $_dbgbase]"
-
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
- -coreid 0 -dbgbase $_dbgbase
-
-# SRAM: 56KiB at 0x4030.0000
-$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
-
-
-#
-# M3 targets, separate TAP/DAP for each core
-#
-target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
-target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
-
-
-# Once the JRC is up, enable our TAPs
-jtag configure $_CHIPNAME.jrc -event setup "
- jtag tapenable $_CHIPNAME.dap
- jtag tapenable $_CHIPNAME.m30_dap
- jtag tapenable $_CHIPNAME.m31_dap
-"
-
-# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
-# ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset.
-set PRM_RSTCTRL 0x4A307B00
-$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
-$_CHIPNAME.m30 configure -event reset-assert { }
-$_CHIPNAME.m31 configure -event reset-assert { }
-
-# Soft breakpoints don't currently work due to broken cache handling
-gdb_breakpoint_override hard
-
diff --git a/openocd-0.10.0/scripts/target/omap4460.cfg b/openocd-0.10.0/scripts/target/omap4460.cfg
deleted file mode 100644
index 9c40e62d00765c002e1a21ed055ba7477afdbfc3..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/omap4460.cfg
+++ /dev/null
@@ -1,126 +0,0 @@
-# OMAP4460
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME omap4460
-}
-
-
-# Although the OMAP4430 supposedly has an ICEpick-D, only the
-# ICEpick-C router commands seem to work.
-# See http://processors.wiki.ti.com/index.php/ICEPICK
-source [find target/icepick.cfg]
-
-
-#
-# A9 DAP
-#
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x3BA00477
-}
-
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 9"
-
-
-#
-# M3 DAPs, one per core
-#
-if { [info exists M3_DAP_TAPID] } {
- set _M3_DAP_TAPID $M3_DAP_TAPID
-} else {
- set _M3_DAP_TAPID 0x4BA00477
-}
-
-jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m31_dap -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 5"
-
-jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_M3_DAP_TAPID -disable
-jtag configure $_CHIPNAME.m30_dap -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 4"
-
-
-#
-# ICEpick-D JRC (JTAG route controller)
-#
-if { [info exists JRC_TAPID] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x2b94e02f
- set _JRC_TAPID2 0x1b85202f
-}
-
-# PandaBoard REV EA1 (PEAP platforms)
-if { [info exists JRC_TAPID2] } {
- set _JRC_TAPID2 $JRC_TAPID2
-} else {
- set _JRC_TAPID2 0x1b85202f
-}
-
-
-
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
- -expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2
-
-# Required by ICEpick to power-up the debug domain
-jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"
-
-
-#
-# GDB target: Cortex-A9, using DAP
-#
-# The debugger can connect to either core of the A9, but currently
-# not both simultaneously. Change -coreid to 1 to connect to the
-# second core.
-#
-set _TARGETNAME $_CHIPNAME.cpu
-
-# APB DBGBASE reads 0x80040000, but this points to an empty ROM table.
-# 0x80000000 is cpu0 coresight region
-#
-#
-# CORTEX_A8_PADDRDBG_CPU_SHIFT 13
-# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)
-
-set _coreid 0
-set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
-echo "Using dbgbase = [format 0x%x $_dbgbase]"
-
-target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
- -coreid 0 -dbgbase $_dbgbase
-
-# SRAM: 56KiB at 0x4030.0000
-$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
-
-
-#
-# M3 targets, separate TAP/DAP for each core
-#
-target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
-target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
-
-
-# Once the JRC is up, enable our TAPs
-jtag configure $_CHIPNAME.jrc -event setup "
- jtag tapenable $_CHIPNAME.dap
- jtag tapenable $_CHIPNAME.m30_dap
- jtag tapenable $_CHIPNAME.m31_dap
-"
-
-# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
-# ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset.
-set PRM_RSTCTRL 0x4A307B00
-$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"
-$_CHIPNAME.m30 configure -event reset-assert { }
-$_CHIPNAME.m31 configure -event reset-assert { }
-
-# Soft breakpoints don't currently work due to broken cache handling
-gdb_breakpoint_override hard
diff --git a/openocd-0.10.0/scripts/target/omap5912.cfg b/openocd-0.10.0/scripts/target/omap5912.cfg
deleted file mode 100644
index c4ff40e233f79d8299b624f59dfc815c77d9c7a7..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/omap5912.cfg
+++ /dev/null
@@ -1,52 +0,0 @@
-# TI OMAP5912 dual core processor
-# http://focus.ti.com/docs/prod/folders/print/omap5912.html
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME omap5912
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # NOTE: validated with XOMAP5912 part
- set _CPUTAPID 0x0692602f
-}
-
-adapter_nsrst_delay 100
-
-# NOTE: presumes irlen 38 is the C55x DSP, matching BSDL for
-# its standalone siblings (like TMS320VC5502) of the same era
-
-#jtag scan chain
-jtag newtap $_CHIPNAME dsp -irlen 38 -expected-id 0x03df1d81
-jtag newtap $_CHIPNAME arm -irlen 4 -expected-id $_CPUTAPID
-jtag newtap $_CHIPNAME unknown -irlen 8
-
-set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
-
-proc omap5912_reset {} {
- #
- # halt target
- #
- poll
- sleep 1
- halt
- wait_halt
- #
- # disable wdt
- #
- mww 0xfffec808 0x000000f5
- mww 0xfffec808 0x000000a0
-
- mww 0xfffeb048 0x0000aaaa
- sleep 500
- mww 0xfffeb048 0x00005555
- sleep 500
-}
-
-# omap5912 lcd frame buffer as working area
-$_TARGETNAME configure -work-area-phys 0x20000000 \
- -work-area-size 0x3e800 -work-area-backup 0
diff --git a/openocd-0.10.0/scripts/target/omapl138.cfg b/openocd-0.10.0/scripts/target/omapl138.cfg
deleted file mode 100644
index fd9ff4c2e7d061ab5257b24662b9120b3be3fb6e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/omapl138.cfg
+++ /dev/null
@@ -1,66 +0,0 @@
-#
-# Texas Instruments DaVinci family: OMAPL138
-#
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME omapl138
-}
-
-source [find target/icepick.cfg]
-
-# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
-if { [info exists ETB_TAPID] } {
- set _ETB_TAPID $ETB_TAPID
-} else {
- set _ETB_TAPID 0x2b900f0f
-}
-jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID -disable
-jtag configure $_CHIPNAME.etb -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 3"
-
-# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
-if { [info exists CPU_TAPID] } {
- set _CPU_TAPID $CPU_TAPID
-} else {
- set _CPU_TAPID 0x07926001
-}
-jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID -disable
-jtag configure $_CHIPNAME.arm -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 2"
-
-# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x0b7d102f
-}
-jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
-
-jtag configure $_CHIPNAME.jrc -event setup \
- "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
-
-################
-# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
-# and the ETB memory (4K) are other options, while trace is unused.
-# Little-endian; use the OpenOCD default.
-set _TARGETNAME $_CHIPNAME.arm
-
-target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x2000
-
-# be absolutely certain the JTAG clock will work with the worst-case
-# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
-# on the PLL and starts using it. OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
-
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-# trace setup
-etm config $_TARGETNAME 16 normal full etb
-etb config $_TARGETNAME $_CHIPNAME.etb
-
-gdb_breakpoint_override hard
-arm7_9 dbgrq enable
diff --git a/openocd-0.10.0/scripts/target/or1k.cfg b/openocd-0.10.0/scripts/target/or1k.cfg
deleted file mode 100644
index 360a0ddf3d80c5f3f4e9e007014a1c084cec769c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/or1k.cfg
+++ /dev/null
@@ -1,72 +0,0 @@
-set _ENDIAN big
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME or1k
-}
-
-if { [info exists TAP_TYPE] } {
- set _TAP_TYPE $TAP_TYPE
-} else {
- puts "You need to select a tap type"
- shutdown
-}
-
-# Configure the target
-if { [string compare $_TAP_TYPE "VJTAG"] == 0 } {
- if { [info exists FPGATAPID] } {
- set _FPGATAPID $FPGATAPID
- } else {
- puts "You need to set your FPGA JTAG ID"
- shutdown
- }
-
- jtag newtap $_CHIPNAME cpu -irlen 10 -expected-id $_FPGATAPID
-
- set _TARGETNAME $_CHIPNAME.cpu
- target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
-
- # Select the TAP core we are using
- tap_select vjtag
-
-} elseif { [string compare $_TAP_TYPE "XILINX_BSCAN"] == 0 } {
-
- if { [info exists FPGATAPID] } {
- set _FPGATAPID $FPGATAPID
- } else {
- puts "You need to set your FPGA JTAG ID"
- shutdown
- }
-
- jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id $_FPGATAPID
-
- set _TARGETNAME $_CHIPNAME.cpu
- target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
-
- # Select the TAP core we are using
- tap_select xilinx_bscan
-} else {
- # OpenCores Mohor JTAG TAP ID
- set _CPUTAPID 0x14951185
-
- jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
- set _TARGETNAME $_CHIPNAME.cpu
- target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
-
- # Select the TAP core we are using
- tap_select mohor
-}
-
-# Select the debug unit core we are using. This debug unit as an option.
-
-set ADBG_USE_HISPEED 1
-set ENABLE_JSP_SERVER 2
-set ENABLE_JSP_MULTI 4
-
-# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
-# on burst reads and writes to improve download speeds.
-# This option must match the RTL configured option.
-
-du_select adv [expr $ADBG_USE_HISPEED | $ENABLE_JSP_SERVER | $ENABLE_JSP_MULTI]
diff --git a/openocd-0.10.0/scripts/target/pic32mx.cfg b/openocd-0.10.0/scripts/target/pic32mx.cfg
deleted file mode 100644
index d53b99a587cf82e3240ec7611e5ca8e52c749c4b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/pic32mx.cfg
+++ /dev/null
@@ -1,90 +0,0 @@
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME pic32mx
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x30938053
-}
-
-# default working area is 16384
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x4000
-}
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
-
-#
-# At reset the pic32mx does not allow code execution from RAM
-# we have to setup the BMX registers to allow this.
-# One limitation is that we loose the first 2k of RAM.
-#
-
-global _PIC32MX_DATASIZE
-global _WORKAREASIZE
-set _PIC32MX_DATASIZE 0x800
-set _PIC32MX_PROGSIZE [expr ($_WORKAREASIZE - $_PIC32MX_DATASIZE)]
-
-$_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0
-$_TARGETNAME configure -event reset-init {
- #
- # from reset the pic32 cannot execute code in ram - enable ram execution
- # minimum offset from start of ram is 2k
- #
- global _PIC32MX_DATASIZE
- global _WORKAREASIZE
-
- # BMXCON set 0 wait state option by clearing BMXWSDRM bit, bit 6
- mww 0xbf882000 0x001f0000
- # BMXDKPBA: 2k kernel data @ 0xa0000000
- mww 0xbf882010 $_PIC32MX_DATASIZE
- # BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA)
- mww 0xbf882020 $_WORKAREASIZE
- # BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA)
- mww 0xbf882030 $_WORKAREASIZE
-
- #
- # Set system clock to 8Mhz if the default clock configuration is set
- #
-
- # SYSKEY register, make sure OSCCON is locked
- mww 0xbf80f230 0x0
- # SYSKEY register, write unlock sequence
- mww 0xbf80f230 0xaa996655
- mww 0xbf80f230 0x556699aa
- # OSCCON register + 4, clear OSCCON FRCDIV bits: 24, 25 and 26, divided by 1
- mww 0xbf80f004 0x07000000
- # SYSKEY register, relock OSCCON
- mww 0xbf80f230 0x0
-}
-
-set _FLASHNAME $_CHIPNAME.flash0
-flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
-# add virtual banks for kseg0 and kseg1
-flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
-flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
-
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME
-# add virtual banks for kseg0 and kseg1
-flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME
-flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME
diff --git a/openocd-0.10.0/scripts/target/psoc4.cfg b/openocd-0.10.0/scripts/target/psoc4.cfg
deleted file mode 100644
index d443b014499e1838ba26ba9c4f535e932a3ca989..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/psoc4.cfg
+++ /dev/null
@@ -1,152 +0,0 @@
-# script for Cypress PSoC 41xx/42xx family
-
-#
-# PSoC 4 devices support SWD transports only.
-#
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME psoc4
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 4kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x1000
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x0bb11477
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME psoc4 0 0 0 0 $_TARGETNAME
-
-adapter_khz 1500
-
-# Reset, bloody PSoC 4 reset
-#
-# 1) XRES (nSRST) resets also SWD DP so SWD line reset and DP reinit is needed.
-# High level adapter stops working after SRST and needs OpenOCD restart.
-# If your hw does not use SRST for other circuits, use sysresetreq instead
-#
-# 2) PSoC 4 executes initialization code from system ROM after reset.
-# This code subsequently jumps to user flash reset vector address.
-# Unfortunately the system ROM code is protected from reading and debugging.
-# Protection breaks vector catch VC_CORERESET used for "reset halt" by cortex_m.
-#
-# Cypress uses TEST_MODE flag to loop CPU in system ROM before executing code
-# from user flash. Programming specifications states that TEST_MODE flag must be
-# set in time frame 400 usec delayed about 1 msec from reset.
-#
-# OpenOCD have no standard way how to set TEST_MODE in specified time frame.
-# TEST_MODE flag is set before reset instead. It worked for tested chips
-# despite it is not guaranteed by specification.
-#
-# 3) SWD cannot be connected during system initialization after reset.
-# This might be a reason for unconnecting ST-Link v2 when deasserting reset.
-# As a workaround arp_reset deassert is not called for hla
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-proc ocd_process_reset_inner { MODE } {
- if { 0 != [string compare psoc4.cpu [target names]] } {
- return -code error "PSoC 4 reset can handle only one psoc4.cpu target";
- }
- set t psoc4.cpu
-
- # If this target must be halted...
- set halt -1
- if { 0 == [string compare $MODE halt] } {
- set halt 1
- }
- if { 0 == [string compare $MODE init] } {
- set halt 1;
- }
- if { 0 == [string compare $MODE run ] } {
- set halt 0;
- }
- if { $halt < 0 } {
- return -code error "Invalid mode: $MODE, must be one of: halt, init, or run";
- }
-
- #$t invoke-event reset-start
- $t invoke-event reset-assert-pre
-
- set TEST_MODE 0x40030014
- if { $halt == 1 } {
- mww $TEST_MODE 0x80000000
- } else {
- mww $TEST_MODE 0
- }
-
- $t arp_reset assert 0
- $t invoke-event reset-assert-post
- $t invoke-event reset-deassert-pre
- if {![using_hla]} { # workaround ST-Link v2 fails and forcing reconnect
- $t arp_reset deassert 0
- }
- $t invoke-event reset-deassert-post
-
- # Pass 1 - Now wait for any halt (requested as part of reset
- # assert/deassert) to happen. Ideally it takes effect without
- # first executing any instructions.
- if { $halt } {
- # Now PSoC CPU should loop in system ROM
- $t arp_waitstate running 200
- $t arp_halt
-
- # Catch, but ignore any errors.
- catch { $t arp_waitstate halted 1000 }
-
- # Did we succeed?
- set s [$t curstate]
-
- if { 0 != [string compare $s "halted" ] } {
- return -code error [format "TARGET: %s - Not halted" $t]
- }
-
- # Check if PSoC CPU is stopped in system ROM
- set pc [ocd_reg pc]
- regsub {pc[^:]*: } $pc "" pc
- if { $pc < 0x10000000 || $pc > 0x1000ffff } {
- return -code error [format "TARGET: %s - Not halted in system ROM, use 'reset_config none'" $t]
- }
-
- # Set registers to reset vector values
- mem2array value 32 0 2
- reg pc [expr $value(1) & 0xfffffffe ]
- reg msp $value(0)
-
- mww $TEST_MODE 0
- }
-
- #Pass 2 - if needed "init"
- if { 0 == [string compare init $MODE] } {
- set err [catch "$t arp_waitstate halted 5000"]
-
- # Did it halt?
- if { $err == 0 } {
- $t invoke-event reset-init
- }
- }
-
- $t invoke-event reset-end
-}
diff --git a/openocd-0.10.0/scripts/target/psoc5lp.cfg b/openocd-0.10.0/scripts/target/psoc5lp.cfg
deleted file mode 100644
index 1cdde4712e1af50ed93687c69686e15451bc91cd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/psoc5lp.cfg
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# Cypress PSoC 5LP
-#
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME psoc5lp
-}
-
-if { [info exists CPUTAPID] } {
- set _CPU_TAPID $CPUTAPID
-} else {
- set _CPU_TAPID 0x4BA00477
-}
-
-if { [using_jtag] } {
- set _CPU_DAP_ID $_CPU_TAPID
-} else {
- set _CPU_DAP_ID 0x2ba01477
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_DAP_ID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
-if {![using_hla]} {
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/pxa255.cfg b/openocd-0.10.0/scripts/target/pxa255.cfg
deleted file mode 100644
index 386242597cefd9b3a8ae3d59a455c67170458a62..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/pxa255.cfg
+++ /dev/null
@@ -1,59 +0,0 @@
-# PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
-# This chip is now at end-of-life. Final orders have been taken.
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME pxa255
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x69264013
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME xscale -endian $_ENDIAN \
- -chain-position $_CHIPNAME.cpu
-
-# PXA255 comes out of reset using 3.6864 MHz oscillator.
-# Until the PLL kicks in, keep the JTAG clock slow enough
-# that we get no errors.
-adapter_khz 300
-$_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
-
-# both TRST and SRST are *required* for debug
-# DCSR is often accessed with SRST active
-reset_config trst_and_srst separate srst_nogate
-
-# reset processing that works with PXA
-proc init_reset {mode} {
- # assert both resets; equivalent to power-on reset
- jtag_reset 1 1
-
- # drop TRST after at least 32 cycles
- sleep 1
- jtag_reset 0 1
-
- # minimum 32 TCK cycles to wake up the controller
- runtest 50
-
- # now the TAP will be responsive; validate scanchain
- jtag arp_init
-
- # ... and take it out of reset
- jtag_reset 0 0
-}
-
-proc jtag_init {} {
- init_reset startup
-}
diff --git a/openocd-0.10.0/scripts/target/pxa270.cfg b/openocd-0.10.0/scripts/target/pxa270.cfg
deleted file mode 100644
index 95f7f16f0767bce66b4c682411cdcbb32df0bd75..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/pxa270.cfg
+++ /dev/null
@@ -1,50 +0,0 @@
-#Marvell/Intel PXA270 Script
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME pxa270
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-#IDs for pxa270. Are there more?
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # set useful default
- set _CPUTAPID 0x49265013
-}
-
-if { [info exists CPUTAPID2] } {
- set _CPUTAPID2 $CPUTAPID2
-} else {
- # set useful default
- set _CPUTAPID2 0x79265013
-}
-
-if { [info exists CPUTAPID3] } {
- set _CPUTAPID2 $CPUTAPID3
-} else {
- # set useful default
- set _CPUTAPID3 0x89265013
-}
-
-# set adapter_nsrst_delay to the delay introduced by your reset circuit
-# the rest of the needed delays are built into the openocd program
-adapter_nsrst_delay 260
-# set the jtag_ntrst_delay to the delay introduced by a reset circuit
-# the rest of the needed delays are built into the openocd program
-jtag_ntrst_delay 250
-
-set _TARGETNAME $_CHIPNAME.cpu
-jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3
-
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
-# maps to PXA internal RAM. If you are using a PXA255
-# you must initialize SDRAM or leave this option off
-$_TARGETNAME configure -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0
diff --git a/openocd-0.10.0/scripts/target/pxa3xx.cfg b/openocd-0.10.0/scripts/target/pxa3xx.cfg
deleted file mode 100644
index c459f6eaaec226bee7455745e685d88a6249313b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/pxa3xx.cfg
+++ /dev/null
@@ -1,86 +0,0 @@
-# Marvell PXA3xx
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME pxa3xx
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# IDs for all currently known PXA3xx chips
-if { [info exists CPUTAPID_PXA30X_A0] } {
- set _CPUTAPID_PXA30X_A0 $CPUTAPID_PXA30X_A0
-} else {
- set _CPUTAPID_PXA30X_A0 0x0E648013
-}
-if { [info exists CPUTAPID_PXA30X_A1] } {
- set _CPUTAPID_PXA30X_A1 $CPUTAPID_PXA30X_A1
-} else {
- set _CPUTAPID_PXA30X_A1 0x1E648013
-}
-if { [info exists CPUTAPID_PXA31X_A0] } {
- set _CPUTAPID_PXA31X_A0 $CPUTAPID_PXA31X_A0
-} else {
- set _CPUTAPID_PXA31X_A0 0x0E649013
-}
-if { [info exists CPUTAPID_PXA31X_A1] } {
- set _CPUTAPID_PXA31X_A1 $CPUTAPID_PXA31X_A1
-} else {
- set _CPUTAPID_PXA31X_A1 0x1E649013
-}
-if { [info exists CPUTAPID_PXA31X_A2] } {
- set _CPUTAPID_PXA31X_A2 $CPUTAPID_PXA31X_A2
-} else {
- set _CPUTAPID_PXA31X_A2 0x2E649013
-}
-if { [info exists CPUTAPID_PXA31X_B0] } {
- set _CPUTAPID_PXA31X_B0 $CPUTAPID_PXA31X_B0
-} else {
- set _CPUTAPID_PXA31X_B0 0x3E649013
-}
-if { [info exists CPUTAPID_PXA32X_B1] } {
- set _CPUTAPID_PXA32X_B1 $CPUTAPID_PXA32X_B1
-} else {
- set _CPUTAPID_PXA32X_B1 0x5E642013
-}
-if { [info exists CPUTAPID_PXA32X_B2] } {
- set _CPUTAPID_PXA32X_B2 $CPUTAPID_PXA32X_B2
-} else {
- set _CPUTAPID_PXA32X_B2 0x6E642013
-}
-if { [info exists CPUTAPID_PXA32X_C0] } {
- set _CPUTAPID_PXA32X_C0 $CPUTAPID_PXA32X_C0
-} else {
- set _CPUTAPID_PXA32X_C0 0x7E642013
-}
-
-# set adapter_nsrst_delay to the delay introduced by your reset circuit
-# the rest of the needed delays are built into the openocd program
-adapter_nsrst_delay 260
-
-# set the jtag_ntrst_delay to the delay introduced by a reset circuit
-# the rest of the needed delays are built into the openocd program
-jtag_ntrst_delay 250
-
-set _TARGETNAME $_CHIPNAME.cpu
-jtag newtap $_CHIPNAME cpu -irlen 11 -ircapture 0x1 -irmask 0x7f \
- -expected-id $_CPUTAPID_PXA30X_A0 \
- -expected-id $_CPUTAPID_PXA30X_A1 \
- -expected-id $_CPUTAPID_PXA31X_A0 \
- -expected-id $_CPUTAPID_PXA31X_A1 \
- -expected-id $_CPUTAPID_PXA31X_A2 \
- -expected-id $_CPUTAPID_PXA31X_B0 \
- -expected-id $_CPUTAPID_PXA32X_B1 \
- -expected-id $_CPUTAPID_PXA32X_B2 \
- -expected-id $_CPUTAPID_PXA32X_C0
-
-target create $_TARGETNAME xscale -endian $_ENDIAN \
- -chain-position $_TARGETNAME
-
-# work area in internal RAM.
-$_TARGETNAME configure -work-area-phys 0x5c030000 -work-area-size 0x10000
diff --git a/openocd-0.10.0/scripts/target/quark_d20xx.cfg b/openocd-0.10.0/scripts/target/quark_d20xx.cfg
deleted file mode 100644
index 419f9dc4df40a6135c81589717a1ad2bc182cfcd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/quark_d20xx.cfg
+++ /dev/null
@@ -1,50 +0,0 @@
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x38289013
-}
-
-jtag newtap quark_d20xx quark -irlen 8 -irmask 0xff -expected-id $_CPUTAPID -disable
-jtag newtap quark_d20xx cltap -irlen 8 -irmask 0xff -expected-id 0x0e786013 -enable
-
-proc quark_d20xx_tapenable {} {
- echo "enabling quark core tap"
- irscan quark_d20xx.cltap 0x11
- drscan quark_d20xx.cltap 12 1
- runtest 10
-}
-
-proc quark_d20xx_tapdisable {} {
- echo "disabling quark core tap"
- irscan quark_d20xx.cltap 0x11
- drscan quark_d20xx.cltap 12 0
- runtest 10
-}
-
-proc quark_d20xx_setup {} {
- jtag tapenable quark_d20xx.quark
-}
-
-jtag configure quark_d20xx.quark -event tap-enable \
- "quark_d20xx_tapenable"
-
-jtag configure quark_d20xx.quark -event tap-disable \
- "quark_d20xx_tapdisable"
-
-target create quark_d20xx.quark quark_d20xx -endian little -chain-position quark_d20xx.quark
-
-quark_d20xx.quark configure -event gdb-attach { halt }
-
-quark_d20xx.quark configure -event reset-start {
- # need to halt the target to write to memory
- if {[quark_d20xx.quark curstate] ne "halted"} { halt }
- # set resetbreak via the core tap
- irscan quark_d20xx.quark 0x35 ; drscan quark_d20xx.quark 1 0x1
- # trigger a warm reset
- mww 0xb0800570 0x2
- # clear resetbreak
- irscan quark_d20xx.quark 0x35 ; drscan quark_d20xx.quark 1 0x0
-}
-
-jtag configure quark_d20xx.quark -event setup \
- "quark_d20xx_setup"
diff --git a/openocd-0.10.0/scripts/target/quark_x10xx.cfg b/openocd-0.10.0/scripts/target/quark_x10xx.cfg
deleted file mode 100644
index a5bbfb497158a68de4c25bdb4777ba2e9b2ef8b6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/quark_x10xx.cfg
+++ /dev/null
@@ -1,52 +0,0 @@
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME quark_x10xx
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x18289013
-}
-
-jtag newtap quark_x10xx cpu -irlen 8 -irmask 0xff -expected-id $_CPUTAPID -disable
-jtag newtap quark_x10xx cltap -irlen 8 -irmask 0xff -expected-id 0x0e681013 -enable
-
-#openocd puts tap at front of chain not end of chain
-proc quark_x10xx_tapenable {} {
- echo "enabling core tap"
- irscan quark_x10xx.cltap 0x11
- drscan quark_x10xx.cltap 64 1
- runtest 10
-}
-
-proc quark_x10xx_tapdisable {} {
- echo "disabling core tap"
- irscan quark_x10xx.cltap 0x11
- drscan quark_x10xx.cltap 64 0
- runtest 10
-}
-
-proc quark_x10xx_setup {} {
- jtag tapenable quark_x10xx.cpu
-}
-
-jtag configure $_CHIPNAME.cpu -event tap-enable \
- "quark_x10xx_tapenable"
-
-jtag configure $_CHIPNAME.cpu -event tap-disable \
- "quark_x10xx_tapdisable"
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create quark_x10xx.cpu quark_x10xx -endian $_ENDIAN -chain-position quark_x10xx.cpu
-
-jtag configure $_CHIPNAME.cpu -event setup \
- "quark_x10xx_setup"
diff --git a/openocd-0.10.0/scripts/target/readme.txt b/openocd-0.10.0/scripts/target/readme.txt
deleted file mode 100644
index f028b11c732325343af0cd41aba00a617282164f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/readme.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-Prerequisites:
-The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands
-do the same thing across all the targets.
-
-Rules to follow when writing scripts:
-
-1. The configuration script should be defined such as , for example, the following sequences are working:
- reset
- flash info <bank>
-and
- reset
- flash erase_address <start> <len>
-and
- reset init
- load
-
-In most cases this can be accomplished by specifying the default startup mode as reset_init (target command
-in the configuration file).
-
-2. If the target is correctly configured, flash must be writable without any other helper commands. It is
-assumed that all write-protect mechanisms should be disabled.
-
-3. The configuration scripts should be defined such as the binary that was written to flash verifies
-(turn off remapping, checksums, etc...)
-
-flash write_image [file] <parameters>
-verify_image [file] <parameters>
-
-4. adapter_khz sets the maximum speed (or alternatively RCLK). If invoked
-multiple times only the last setting is used.
-
-interface/xxx.cfg files are always executed *before* target/xxx.cfg
-files, so any adapter_khz in interface/xxx.cfg will be overridden by
-target/xxx.cfg. adapter_khz in interface/xxx.cfg would then, effectively,
-set the default JTAG speed.
-
-Note that a target/xxx.cfg file can invoke another target/yyy.cfg file,
-so one can create target subtype configurations where e.g. only
-amount of DRAM, oscillator speeds differ and having a single
-config file for the default/common settings.
-
diff --git a/openocd-0.10.0/scripts/target/renesas_s7g2.cfg b/openocd-0.10.0/scripts/target/renesas_s7g2.cfg
deleted file mode 100644
index a09377b2d2ce3da7f37d187a9a1243c0f483da58..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/renesas_s7g2.cfg
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# Renesas Synergy S7 G2 w/ ARM Cortex-M4 @ 240 MHz
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME s7g2
-}
-
-if { [info exists CPU_JTAG_TAPID] } {
- set _CPU_JTAG_TAPID $CPU_JTAG_TAPID
-} else {
- set _CPU_JTAG_TAPID 0x5ba00477
-}
-
-if { [info exists CPU_SWD_TAPID] } {
- set _CPU_SWD_TAPID $CPU_SWD_TAPID
-} else {
- set _CPU_SWD_TAPID 0x5ba02477
-}
-
-source [find target/swj-dp.tcl]
-
-if { [using_jtag] } {
- set _CPU_TAPID $_CPU_JTAG_TAPID
-} else {
- set _CPU_TAPID $_CPU_SWD_TAPID
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- # 640 KB On-Chip SRAM
- set _WORKAREASIZE 0xa0000
-}
-
-$_TARGETNAME configure -work-area-phys 0x1ffe0000 \
- -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-if { ![using_hla] } {
- cortex_m reset_config sysresetreq
-}
-
-adapter_khz 1000
diff --git a/openocd-0.10.0/scripts/target/samsung_s3c2410.cfg b/openocd-0.10.0/scripts/target/samsung_s3c2410.cfg
deleted file mode 100644
index 017c104927e25ac31e5bd64fa3e331d236630923..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/samsung_s3c2410.cfg
+++ /dev/null
@@ -1,36 +0,0 @@
-# Found on the 'TinCanTools' Hammer board.
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME s3c2410
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # This config file was defaulting to big endian..
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # Force an error until we get a good number.
- set _CPUTAPID 0xffffffff
-}
-
-#use combined on interfaces or targets that cannot set TRST/SRST separately
-reset_config trst_and_srst
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0
-
-# speed up memory downloads
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
diff --git a/openocd-0.10.0/scripts/target/samsung_s3c2440.cfg b/openocd-0.10.0/scripts/target/samsung_s3c2440.cfg
deleted file mode 100644
index 2a0a915d69b4592d91ea677570ee5ed5fb0856e9..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/samsung_s3c2440.cfg
+++ /dev/null
@@ -1,35 +0,0 @@
-# Target configuration for the Samsung 2440 system on chip
-# Tested on a S3C2440 Evaluation board by keesj
-# Processor : ARM920Tid(wb) rev 0 (v4l)
-# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME s3c2440
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a bigendian
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x0032409d
-}
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1
-
-#reset configuration
-reset_config trst_and_srst
-
diff --git a/openocd-0.10.0/scripts/target/samsung_s3c2450.cfg b/openocd-0.10.0/scripts/target/samsung_s3c2450.cfg
deleted file mode 100644
index 1bc4f2d87581f7aeacea9dfa7fcc10d795a0df57..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/samsung_s3c2450.cfg
+++ /dev/null
@@ -1,48 +0,0 @@
-# Target configuration for the Samsung 2450 system on chip
-# Processor : ARM926ejs (wb) rev 0 (v4l)
-# Info: JTAG tap: s3c2450.cpu tap/device found: 0x07926F0F
-
-
-# FIX!!! what to use here?
-#
-# RCLK?
-#
-# adapter_khz 0
-#
-# Really low clock during reset?
-#
-# adapter_khz 1
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME s3c2450
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a bigendian
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07926f0f
-}
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xE -irmask 0x0f -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# FIX!!!!! should this really use srst_pulls_trst?
-# With srst_pulls_trst "reset halt" will not reset into the
-# halted mode, but rather "reset run" and then halt the target.
-#
-# However, without "srst_pulls_trst", then "reset halt" produces weird
-# errors:
-# WARNING: unknown debug reason: 0x0
-reset_config trst_and_srst
diff --git a/openocd-0.10.0/scripts/target/samsung_s3c4510.cfg b/openocd-0.10.0/scripts/target/samsung_s3c4510.cfg
deleted file mode 100644
index 461d0478ac73ed8f4e6b04615fa2fda3e5efa8b8..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/samsung_s3c4510.cfg
+++ /dev/null
@@ -1,24 +0,0 @@
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME s3c4510
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-
-# This appears to be a "Version 1" arm7tdmi.
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x1f0f0f0f
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
diff --git a/openocd-0.10.0/scripts/target/samsung_s3c6410.cfg b/openocd-0.10.0/scripts/target/samsung_s3c6410.cfg
deleted file mode 100644
index 88fe966dcd3b42f7c84963ac6ba0227b6d499da2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/samsung_s3c6410.cfg
+++ /dev/null
@@ -1,51 +0,0 @@
-# -*- tcl -*-
-# Target configuration for the Samsung s3c6410 system on chip
-# Tested on a SMDK6410
-# Processor : ARM1176
-# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
-# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places]
-# [and I do not believe it to be accurate, hence the 0xffffffff below]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME s3c6410
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a bigendian
- set _ENDIAN little
-}
-
-# trace buffer
-if { [info exists ETBTAPID] } {
- set _ETBTAPID $ETBTAPID
-} else {
- set _ETBTAPID 0x2b900f0f
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07b76f0f
-}
-
-#jtag scan chain
-
-jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETBTAPID
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-adapter_nsrst_delay 500
-jtag_ntrst_delay 500
-
-#reset configuration
-reset_config trst_and_srst
-
-# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
-etm config $_TARGETNAME 16 normal full etb
-etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/openocd-0.10.0/scripts/target/sharp_lh79532.cfg b/openocd-0.10.0/scripts/target/sharp_lh79532.cfg
deleted file mode 100644
index 6f2cf223451bdb0c093465f8826a790656a0136e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/sharp_lh79532.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-reset_config srst_only srst_pulls_trst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lh79532
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # sharp changed the number!
- set _CPUTAPID 0x00002061
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-
diff --git a/openocd-0.10.0/scripts/target/sim3x.cfg b/openocd-0.10.0/scripts/target/sim3x.cfg
deleted file mode 100644
index f721f36c87a0a1b6c6ec5b2f6960c76485b616e0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/sim3x.cfg
+++ /dev/null
@@ -1,55 +0,0 @@
-#
-# Silicon Laboratories SiM3x Cortex-M3
-#
-
-# SiM3x devices support both JTAG and SWD transports.
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME SiM3x
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4ba00477
-}
-
-if { [info exists CPURAMSIZE] } {
- set _CPURAMSIZE $CPURAMSIZE
-} else {
-# Minimum size of RAM in the Silicon Labs product matrix (8KB)
- set _CPURAMSIZE 0x2000
-}
-
-if { [info exists CPUROMSIZE] } {
- set _CPUROMSIZE $CPUROMSIZE
-} else {
-# Minimum size of FLASH in the Silicon Labs product matrix (32KB)
- set _CPUROMSIZE 0x8000
-}
-
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE $_CPURAMSIZE
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
-
-adapter_khz 1000
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
diff --git a/openocd-0.10.0/scripts/target/smp8634.cfg b/openocd-0.10.0/scripts/target/smp8634.cfg
deleted file mode 100644
index c13414c873b054c2537147b3c92fae8e3a6031fc..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/smp8634.cfg
+++ /dev/null
@@ -1,31 +0,0 @@
-# script for Sigma Designs SMP8634 (eventually even SMP8635)
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME smp8634
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x08630001
-}
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
-reset_config trst_and_srst separate
-
-# jtag scan chain
-# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME mips_m4k -endian $_ENDIAN
diff --git a/openocd-0.10.0/scripts/target/spear3xx.cfg b/openocd-0.10.0/scripts/target/spear3xx.cfg
deleted file mode 100644
index a86a3c4ebe0c5b657420fb839fae4a1cc53f37a6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/spear3xx.cfg
+++ /dev/null
@@ -1,41 +0,0 @@
-# Target configuration for the ST SPEAr3xx family of system on chip
-# Supported SPEAr300, SPEAr310, SPEAr320
-# http://www.st.com/spear
-#
-# Processor: ARM926ejs
-# Info: JTAG tap: spear3xx.cpu tap/device found: 0x07926041
-# Date: 2009-10-31
-# Author: Antonio Borneo <borneo.antonio@gmail.com>
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME spear3xx
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07926041
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x03 \
- -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN \
- -chain-position $_TARGETNAME
-
-# SPEAr3xx has a 8K block of sram @ 0xd280.0000
-# REVISIT: what OS puts virtual address equal to phys?
-$_TARGETNAME configure \
- -work-area-virt 0xd2800000 \
- -work-area-phys 0xd2800000 \
- -work-area-size 0x2000 \
- -work-area-backup 0
diff --git a/openocd-0.10.0/scripts/target/stellaris.cfg b/openocd-0.10.0/scripts/target/stellaris.cfg
deleted file mode 100644
index 4fe99394aa83191e1b3c4e056a88a6a5a7b3b40e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stellaris.cfg
+++ /dev/null
@@ -1,176 +0,0 @@
-# TI/Luminary Stellaris LM3S chip family
-
-# Some devices have errata in returning their device class.
-# DEVICECLASS is provided as a manual override
-# Manual setting of a device class of 0xff is not allowed
-
-global _DEVICECLASS
-
-if { [info exists DEVICECLASS] } {
- set _DEVICECLASS $DEVICECLASS
-} else {
- set _DEVICECLASS 0xff
-}
-
-# Luminary chips support both JTAG and SWD transports.
-# Adapt based on what transport is active.
-source [find target/swj-dp.tcl]
-
-# For now we ignore the SPI and UART options, which
-# are usable only for ISP style initial flash programming.
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME lm3s
-}
-
-# CPU TAP ID 0x1ba00477 for early Sandstorm parts
-# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
-# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
-# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)
-# CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)
-# ... we'll ignore the JTAG version field, rather than list every
-# chip revision that turns up.
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x0ba00477
-}
-
-# SWD DAP, and JTAG TAP, take same params for now;
-# ... even though SWD ignores all except TAPID, and
-# JTAG shouldn't need anything more then irlen. (and TAPID).
-swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
- -expected-id $_CPUTAPID -ignore-version
-
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- # default to 2K working area
- set _WORKAREASIZE 0x800
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
-
-# 8K working area at base of ram, not backed up
-#
-# NOTE: you may need or want to reconfigure the work area;
-# some parts have just 6K, and you may want to use other
-# addresses (at end of mem not beginning) or back it up.
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
-
-# JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
-# LM3S parts don't support RTCK
-#
-# NOTE: this may be increased by a reset-init handler, after it
-# configures and enables the PLL. Or you might need to decrease
-# this, if you're using a slower clock.
-adapter_khz 500
-
-source [find mem_helper.tcl]
-
-proc reset_peripherals {family} {
-
- source [find chip/ti/lm3s/lm3s.tcl]
-
- echo "Resetting Core Peripherals"
-
- # Disable the PLL and the system clock divider (nop if disabled)
- mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV
- mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
-
- # RCC and RCC2 to their reset values
- mww $SYSCTL_RCC [expr (0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS))]
- mww $SYSCTL_RCC2 0x07806810
- mww $SYSCTL_RCC 0x078e3ad1
-
- # Reset the deep sleep clock configuration register
- mww $SYSCTL_DSLPCLKCFG 0x07800000
-
- # Reset the clock gating registers
- mww $SYSCTL_RCGC0 0x00000040
- mww $SYSCTL_RCGC1 0
- mww $SYSCTL_RCGC2 0
- mww $SYSCTL_SCGC0 0x00000040
- mww $SYSCTL_SCGC1 0
- mww $SYSCTL_SCGC2 0
- mww $SYSCTL_DCGC0 0x00000040
- mww $SYSCTL_DCGC1 0
- mww $SYSCTL_DCGC2 0
-
- # Reset the remaining SysCtl registers
- mww $SYSCTL_PBORCTL 0
- mww $SYSCTL_IMC 0
- mww $SYSCTL_GPIOHBCTL 0
- mww $SYSCTL_MOSCCTL 0
- mww $SYSCTL_PIOSCCAL 0
- mww $SYSCTL_I2SMCLKCFG 0
-
- # Reset the peripherals
- mww $SYSCTL_SRCR0 0xffffffff
- mww $SYSCTL_SRCR1 0xffffffff
- mww $SYSCTL_SRCR2 0xffffffff
- mww $SYSCTL_SRCR0 0
- mww $SYSCTL_SRCR1 0
- mww $SYSCTL_SRCR2 0
-
- # Clear any pending SysCtl interrupts
- mww $SYSCTL_MISC 0xffffffff
-
- # Wait for any pending flash operations to complete
- while {[expr [mrw $FLASH_FMC] & 0xffff] != 0} { sleep 1 }
- while {[expr [mrw $FLASH_FMC2] & 0xffff] != 0} { sleep 1 }
-
- # Reset the flash controller registers
- mww $FLASH_FMA 0
- mww $FLASH_FCIM 0
- mww $FLASH_FCMISC 0xffffffff
- mww $FLASH_FWBVAL 0
-}
-
-$_TARGETNAME configure -event reset-start {
- adapter_khz 500
-
- #
- # When nRST is asserted on most Stellaris devices, it clears some of
- # the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
- # and OpenOCD depends on those TRMs. So we won't use SRST on those
- # chips. (Only power-on reset should affect debug state, beyond a
- # few specified bits; not the chip's nRST input, wired to SRST.)
- #
- # REVISIT current errata specs don't seem to cover this issue.
- # Do we have more details than this email?
- # https://lists.berlios.de/pipermail
- # /openocd-development/2008-August/003065.html
- #
-
- global _DEVICECLASS
-
- if {$_DEVICECLASS != 0xff} {
- set device_class $_DEVICECLASS
- } else {
- set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
- }
-
- if {$device_class == 0 || $device_class == 1 ||
- $device_class == 3 || $device_class == 5 || $device_class == 0xa} {
- if {![using_hla]} {
- # Sandstorm, Fury, DustDevil, Blizzard and Snowflake are able to use NVIC SYSRESETREQ
- cortex_m reset_config sysresetreq
- }
- } else {
- if {![using_hla]} {
- # Tempest and Firestorm default to using NVIC VECTRESET
- # peripherals will need reseting manually, see proc reset_peripherals
- cortex_m reset_config vectreset
- }
- # reset peripherals, based on code in
- # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
- reset_peripherals $device_class
- }
-}
-
-# flash configuration ... autodetects sizes, autoprobed
-flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/stellaris_icdi.cfg b/openocd-0.10.0/scripts/target/stellaris_icdi.cfg
deleted file mode 100644
index f856a7a8d83f22fc19e91d44d552c69b356754b2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stellaris_icdi.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-echo "WARNING: target/stellaris_icdi.cfg is deprecated, please switch to target/stellaris.cfg"
-source [find target/stellaris.cfg]
diff --git a/openocd-0.10.0/scripts/target/stm32_stlink.cfg b/openocd-0.10.0/scripts/target/stm32_stlink.cfg
deleted file mode 100644
index 295292e3e50e401cfc8ec8ffdedb13bd32bb028e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32_stlink.cfg
+++ /dev/null
@@ -1 +0,0 @@
-echo "WARNING: stm32_stlink.cfg is deprecated (and does nothing, you can safely remove it.)"
diff --git a/openocd-0.10.0/scripts/target/stm32f0x.cfg b/openocd-0.10.0/scripts/target/stm32f0x.cfg
deleted file mode 100644
index 2b48cfce3e93c5bce0b3719229901ebbd1873ae3..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32f0x.cfg
+++ /dev/null
@@ -1,86 +0,0 @@
-# script for stm32f0x family
-
-#
-# stm32 devices support SWD transports only.
-#
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32f0x
-}
-
-set _ENDIAN little
-
-# Work-area is a space in RAM used for flash programming
-# By default use 4kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x1000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # See STM Document RM0091
- # Section 29.5.3
- set _CPUTAPID 0x0bb11477
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# flash size will be probed
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
-
-# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
-
-adapter_nsrst_delay 100
-
-reset_config srst_nogate
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-proc stm32f0x_default_reset_start {} {
- # Reset clock is HSI (8 MHz)
- adapter_khz 1000
-}
-
-proc stm32f0x_default_examine_end {} {
- # Enable debug during low power modes (uses more power)
- mmw 0x40015804 0x00000006 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
-
- # Stop watchdog counters during halt
- mmw 0x40015808 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
-}
-
-proc stm32f0x_default_reset_init {} {
- # Configure PLL to boost clock to HSI x 6 (48 MHz)
- mww 0x40021004 0x00100000 ;# RCC_CFGR = PLLMUL[2]
- mmw 0x40021000 0x01000000 0 ;# RCC_CR[31:16] |= PLLON
- mww 0x40022000 0x00000011 ;# FLASH_ACR = PRFTBE | LATENCY[0]
- sleep 10 ;# Wait for PLL to lock
- mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
-
- # Boost JTAG frequency
- adapter_khz 8000
-}
-
-# Default hooks
-$_TARGETNAME configure -event examine-end { stm32f0x_default_examine_end }
-$_TARGETNAME configure -event reset-start { stm32f0x_default_reset_start }
-$_TARGETNAME configure -event reset-init { stm32f0x_default_reset_init }
diff --git a/openocd-0.10.0/scripts/target/stm32f0x_stlink.cfg b/openocd-0.10.0/scripts/target/stm32f0x_stlink.cfg
deleted file mode 100644
index cecfb7a78cb2524cf0368ed01fbea0104d06f89c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32f0x_stlink.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-echo "WARNING: target/stm32f0x_stlink.cfg is deprecated, please switch to target/stm32f0x.cfg"
-source [find target/stm32f0x.cfg]
diff --git a/openocd-0.10.0/scripts/target/stm32f1x.cfg b/openocd-0.10.0/scripts/target/stm32f1x.cfg
deleted file mode 100644
index 5a4c2fa702c760949cf07348692f4c20be1e3c52..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32f1x.cfg
+++ /dev/null
@@ -1,80 +0,0 @@
-# script for stm32f1x family
-
-#
-# stm32 devices support both JTAG and SWD transports.
-#
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32f1x
-}
-
-set _ENDIAN little
-
-# Work-area is a space in RAM used for flash programming
-# By default use 4kB (as found on some STM32F100s)
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x1000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- # See STM Document RM0008 Section 26.6.3
- set _CPUTAPID 0x3ba00477
- } {
- # this is the SW-DP tap id not the jtag tap id
- set _CPUTAPID 0x1ba01477
- }
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if {[using_jtag]} {
- jtag newtap $_CHIPNAME bs -irlen 5
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# flash size will be probed
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
-
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-adapter_khz 1000
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-reset_config srst_nogate
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-$_TARGETNAME configure -event examine-end {
- # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
- # DBG_STANDBY | DBG_STOP | DBG_SLEEP
- mmw 0xE0042004 0x00000307 0
-}
-
-$_TARGETNAME configure -event trace-config {
- # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
- # change this value accordingly to configure trace pins
- # assignment
- mmw 0xE0042004 0x00000020 0
-}
diff --git a/openocd-0.10.0/scripts/target/stm32f1x_stlink.cfg b/openocd-0.10.0/scripts/target/stm32f1x_stlink.cfg
deleted file mode 100644
index 0a3e6430ed72de408ad3eb813c23ffab55c098e0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32f1x_stlink.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-echo "WARNING: target/stm32f1x_stlink.cfg is deprecated, please switch to target/stm32f1x.cfg"
-source [find target/stm32f1x.cfg]
diff --git a/openocd-0.10.0/scripts/target/stm32f2x.cfg b/openocd-0.10.0/scripts/target/stm32f2x.cfg
deleted file mode 100644
index 44955d4559f25db22016d4ab395a59fa81ed4452..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32f2x.cfg
+++ /dev/null
@@ -1,87 +0,0 @@
-# script for stm32f2x family
-
-#
-# stm32 devices support both JTAG and SWD transports.
-#
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32f2x
-}
-
-set _ENDIAN little
-
-# Work-area is a space in RAM used for flash programming
-# By default use 64kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x10000
-}
-
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-#
-# Since we may be running of an RC oscilator, we crank down the speed a
-# bit more to be on the safe side. Perhaps superstition, but if are
-# running off a crystal, we can run closer to the limit. Note
-# that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- # See STM Document RM0033
- # Section 32.6.3 - corresponds to Cortex-M3 r2p0
- set _CPUTAPID 0x4ba00477
- } {
- set _CPUTAPID 0x2ba01477
- }
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if {[using_jtag]} {
- jtag newtap $_CHIPNAME bs -irlen 5
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
-
-reset_config srst_nogate
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-$_TARGETNAME configure -event examine-end {
- # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
- mmw 0xE0042004 0x00000007 0
-
- # Stop watchdog counters during halt
- # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
- mmw 0xE0042008 0x00001800 0
-}
-
-$_TARGETNAME configure -event trace-config {
- # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
- # change this value accordingly to configure trace pins
- # assignment
- mmw 0xE0042004 0x00000020 0
-}
diff --git a/openocd-0.10.0/scripts/target/stm32f2x_stlink.cfg b/openocd-0.10.0/scripts/target/stm32f2x_stlink.cfg
deleted file mode 100644
index 451b2b5e2e625aae6421f2b6848bf3773f81a0dd..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32f2x_stlink.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-echo "WARNING: target/stm32f2x_stlink.cfg is deprecated, please switch to target/stm32f2x.cfg"
-source [find target/stm32f2x.cfg]
diff --git a/openocd-0.10.0/scripts/target/stm32f3x.cfg b/openocd-0.10.0/scripts/target/stm32f3x.cfg
deleted file mode 100644
index 0c8919f1dc1ddf22822d3abbe8c66ecbf12cdb9c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32f3x.cfg
+++ /dev/null
@@ -1,108 +0,0 @@
-# script for stm32f3x family
-
-#
-# stm32 devices support both JTAG and SWD transports.
-#
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32f3x
-}
-
-set _ENDIAN little
-
-# Work-area is a space in RAM used for flash programming
-# By default use 16kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x4000
-}
-
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
-#
-# Since we may be running of an RC oscilator, we crank down the speed a
-# bit more to be on the safe side. Perhaps superstition, but if are
-# running off a crystal, we can run closer to the limit. Note
-# that there can be a pretty wide band where things are more or less stable.
-adapter_khz 1000
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- # See STM Document RM0316
- # Section 29.6.3 - corresponds to Cortex-M4 r0p1
- set _CPUTAPID 0x4ba00477
- } {
- set _CPUTAPID 0x2ba01477
- }
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if {[using_jtag]} {
- jtag newtap $_CHIPNAME bs -irlen 5
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
-
-reset_config srst_nogate
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-proc stm32f3x_default_reset_start {} {
- # Reset clock is HSI (8 MHz)
- adapter_khz 1000
-}
-
-proc stm32f3x_default_examine_end {} {
- # Enable debug during low power modes (uses more power)
- mmw 0xe0042004 0x00000007 0 ;# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
-
- # Stop watchdog counters during halt
- mmw 0xe0042008 0x00001800 0 ;# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
-}
-
-proc stm32f3x_default_reset_init {} {
- # Configure PLL to boost clock to HSI x 8 (64 MHz)
- mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2]
- mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON
- mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1]
- sleep 10 ;# Wait for PLL to lock
- mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1]
-
- # Boost JTAG frequency
- adapter_khz 8000
-}
-
-# Default hooks
-$_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
-$_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
-$_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
-
-$_TARGETNAME configure -event trace-config {
- # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
- # change this value accordingly to configure trace pins
- # assignment
- mmw 0xe0042004 0x00000020 0
-}
diff --git a/openocd-0.10.0/scripts/target/stm32f3x_stlink.cfg b/openocd-0.10.0/scripts/target/stm32f3x_stlink.cfg
deleted file mode 100644
index 87693586dcd6a2ccca789053a658ee1df3872716..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32f3x_stlink.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-echo "WARNING: target/stm32f3x_stlink.cfg is deprecated, please switch to target/stm32f3x.cfg"
-source [find target/stm32f3x.cfg]
diff --git a/openocd-0.10.0/scripts/target/stm32f4x.cfg b/openocd-0.10.0/scripts/target/stm32f4x.cfg
deleted file mode 100644
index 7a0af9fba0d24845b101207283327c766aacf22b..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32f4x.cfg
+++ /dev/null
@@ -1,106 +0,0 @@
-# script for stm32f4x family
-
-#
-# stm32 devices support both JTAG and SWD transports.
-#
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32f4x
-}
-
-set _ENDIAN little
-
-# Work-area is a space in RAM used for flash programming
-# By default use 32kB (Available RAM in smallest device STM32F410)
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x8000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- # See STM Document RM0090
- # Section 38.6.3 - corresponds to Cortex-M4 r0p1
- set _CPUTAPID 0x4ba00477
- } {
- set _CPUTAPID 0x2ba01477
- }
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if {[using_jtag]} {
- jtag newtap $_CHIPNAME bs -irlen 5
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
-
-# JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
-#
-# Since we may be running of an RC oscilator, we crank down the speed a
-# bit more to be on the safe side. Perhaps superstition, but if are
-# running off a crystal, we can run closer to the limit. Note
-# that there can be a pretty wide band where things are more or less stable.
-adapter_khz 2000
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-reset_config srst_nogate
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-$_TARGETNAME configure -event examine-end {
- # Enable debug during low power modes (uses more power)
- # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
- mmw 0xE0042004 0x00000007 0
-
- # Stop watchdog counters during halt
- # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
- mmw 0xE0042008 0x00001800 0
-}
-
-$_TARGETNAME configure -event trace-config {
- # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
- # change this value accordingly to configure trace pins
- # assignment
- mmw 0xE0042004 0x00000020 0
-}
-
-$_TARGETNAME configure -event reset-init {
- # Configure PLL to boost clock to HSI x 4 (64 MHz)
- mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
- mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency)
- mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
- sleep 10 ;# Wait for PLL to lock
- mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
- mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
-
- # Boost JTAG frequency
- adapter_khz 8000
-}
-
-$_TARGETNAME configure -event reset-start {
- # Reduce speed since CPU speed will slow down to 16MHz with the reset
- adapter_khz 2000
-}
diff --git a/openocd-0.10.0/scripts/target/stm32f4x_stlink.cfg b/openocd-0.10.0/scripts/target/stm32f4x_stlink.cfg
deleted file mode 100644
index af3e8a098cd372429df15bfb5c7178f6a460e5b5..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32f4x_stlink.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-echo "WARNING: target/stm32f4x_stlink.cfg is deprecated, please switch to target/stm32f4x.cfg"
-source [find target/stm32f4x.cfg]
diff --git a/openocd-0.10.0/scripts/target/stm32f7x.cfg b/openocd-0.10.0/scripts/target/stm32f7x.cfg
deleted file mode 100644
index 4065e2a07335eb6a232604e2bcd9da760ab80b51..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32f7x.cfg
+++ /dev/null
@@ -1,83 +0,0 @@
-# script for stm32f7x family
-
-#
-# stm32f7 devices support both JTAG and SWD transports.
-#
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32f7x
-}
-
- set _ENDIAN little
-
-# Work-area is a space in RAM used for flash programming
-# By default use 128kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x20000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- # See STM Document RM0385
- # Section 40.6.3 - corresponds to Cortex-M7 with FPU r0p0
- set _CPUTAPID 0x5ba00477
- } {
- set _CPUTAPID 0x5ba02477
- }
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if {[using_jtag]} {
- jtag newtap $_CHIPNAME bs -irlen 5
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
-
-# adapter speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
-adapter_khz 2000
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-$_TARGETNAME configure -event examine-end {
- # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
- mmw 0xE0042004 0x00000007 0
-
- # Stop watchdog counters during halt
- # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
- mmw 0xE0042008 0x00001800 0
-}
-
-$_TARGETNAME configure -event trace-config {
- # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
- # change this value accordingly to configure trace pins
- # assignment
- mmw 0xE0042004 0x00000020 0
-}
diff --git a/openocd-0.10.0/scripts/target/stm32l0.cfg b/openocd-0.10.0/scripts/target/stm32l0.cfg
deleted file mode 100644
index 245213b425af400fc21d6f395a16caccc3c690aa..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32l0.cfg
+++ /dev/null
@@ -1,87 +0,0 @@
-#
-# M0+ devices only have SW-DP, but swj-dp code works, just don't
-# set any jtag related features
-#
-
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32l0
-}
-
-set _ENDIAN little
-
-# Work-area is a space in RAM used for flash programming
-# By default use 8kB (max ram on smallest part)
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x2000
-}
-
-# JTAG speed should be <= F_CPU/6.
-# F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
-
-adapter_nsrst_delay 100
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # Arm, m0+, non-multidrop.
- # http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html
- set _CPUTAPID 0x0bc11477
-}
-
-swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# flash size will be probed
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
-
-reset_config srst_nogate
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-proc stm32l0_enable_HSI16 {} {
- # Enable HSI16 as clock source
- echo "STM32L0: Enabling HSI16"
-
- # Set HSI16ON in RCC_CR (leave MSI enabled)
- mww 0x40021000 0x00000101
-
- # Set HSI16 as SYSCLK (RCC_CFGR)
- mww 0x4002100c 0x00000001
-
- # Increase speed
- adapter_khz 2500
-}
-
-$_TARGETNAME configure -event reset-init {
- stm32l0_enable_HSI16
-}
-
-$_TARGETNAME configure -event reset-start {
- adapter_khz 300
-}
-
-$_TARGETNAME configure -event examine-end {
- # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
- mmw 0x40015804 0x00000007 0
-
- # Stop watchdog counters during halt
- # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
- mmw 0x40015808 0x00001800 0
-}
diff --git a/openocd-0.10.0/scripts/target/stm32l1.cfg b/openocd-0.10.0/scripts/target/stm32l1.cfg
deleted file mode 100644
index a8d6fdf257f2a15003b7f4a279d7232a1e0cdb4a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32l1.cfg
+++ /dev/null
@@ -1,106 +0,0 @@
-#
-# stm32l1 devices support both JTAG and SWD transports.
-#
-
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32l1
-}
-
-set _ENDIAN little
-
-# Work-area is a space in RAM used for flash programming
-# By default use 10kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x2800
-}
-
-# JTAG speed should be <= F_CPU/6.
-# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
-adapter_khz 300
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- # See STM Document RM0038
- # Section 30.6.3 - corresponds to Cortex-M3 r2p0
- set _CPUTAPID 0x4ba00477
- } else {
- # SWD IDCODE (single drop, arm)
- set _CPUTAPID 0x2ba01477
- }
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if {[using_jtag]} {
- jtag newtap $_CHIPNAME bs -irlen 5
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# flash size will be probed
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
-
-reset_config srst_nogate
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-proc stm32l_enable_HSI {} {
- # Enable HSI as clock source
- echo "STM32L: Enabling HSI"
-
- # Set HSION in RCC_CR
- mww 0x40023800 0x00000101
-
- # Set HSI as SYSCLK
- mww 0x40023808 0x00000001
-
- # Increase JTAG speed
- adapter_khz 2000
-}
-
-$_TARGETNAME configure -event reset-init {
- stm32l_enable_HSI
-}
-
-$_TARGETNAME configure -event reset-start {
- adapter_khz 300
-}
-
-$_TARGETNAME configure -event examine-end {
- # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
- mmw 0xE0042004 0x00000007 0
-
- # Stop watchdog counters during halt
- # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
- mmw 0xE0042008 0x00001800 0
-}
-
-$_TARGETNAME configure -event trace-config {
- # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
- # change this value accordingly to configure trace pins
- # assignment
- mmw 0xE0042004 0x00000020 0
-}
diff --git a/openocd-0.10.0/scripts/target/stm32l1x_dual_bank.cfg b/openocd-0.10.0/scripts/target/stm32l1x_dual_bank.cfg
deleted file mode 100644
index a3f7413a0c6fa9f9bd931245dd0e196ae77a84a9..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32l1x_dual_bank.cfg
+++ /dev/null
@@ -1,8 +0,0 @@
-source [find target/stm32l1.cfg]
-
-# The stm32l1x 384kb have a dual bank flash.
-# Let's add a definition for the second bank here.
-
-# Add the second flash bank.
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/stm32l4x.cfg b/openocd-0.10.0/scripts/target/stm32l4x.cfg
deleted file mode 100644
index 9cad7c492c6b2ea29a905b7dfbd48f4d439324a2..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32l4x.cfg
+++ /dev/null
@@ -1,102 +0,0 @@
-# script for stm32l4x family
-
-#
-# stm32l4 devices support both JTAG and SWD transports.
-#
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32l4x
-}
-
-set _ENDIAN little
-
-# Work-area is a space in RAM used for flash programming
-# Smallest current target has 64kB ram, use 32kB by default to avoid surprises
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x8000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- # See STM Document RM0351
- # Section 44.6.3 - corresponds to Cortex-M4 r0p1
- set _CPUTAPID 0x4ba00477
- } {
- set _CPUTAPID 0x2ba01477
- }
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if {[using_jtag]} {
- jtag newtap $_CHIPNAME bs -irlen 5
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
-
-# Common knowledges tells JTAG speed should be <= F_CPU/6.
-# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
-# the safe side.
-#
-# Note that there is a pretty wide band where things are
-# more or less stable, see http://openocd.zylin.com/#/c/3366/
-adapter_khz 500
-
-adapter_nsrst_delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-reset_config srst_nogate
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-$_TARGETNAME configure -event reset-init {
- # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
- # Use MSI 24 MHz clock, compliant even with VOS == 2.
- # 3 WS compliant with VOS == 2 and 24 MHz.
- mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency)
- mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL| MSI Range 10
- # Boost JTAG frequency
- adapter_khz 4000
-}
-
-$_TARGETNAME configure -event reset-start {
- # Reset clock is MSI (4 MHz)
- adapter_khz 500
-}
-
-$_TARGETNAME configure -event examine-end {
- # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
- mmw 0xE0042004 0x00000007 0
-
- # Stop watchdog counters during halt
- # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
- mmw 0xE0042008 0x00001800 0
-}
-
-$_TARGETNAME configure -event trace-config {
- # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
- # change this value accordingly to configure trace pins
- # assignment
- mmw 0xE0042004 0x00000020 0
-}
diff --git a/openocd-0.10.0/scripts/target/stm32lx_stlink.cfg b/openocd-0.10.0/scripts/target/stm32lx_stlink.cfg
deleted file mode 100644
index 5f694b546fbe866899d3694298d2078a99f2f46e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32lx_stlink.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-echo "WARNING: target/stm32lx_stlink.cfg is deprecated, please switch to target/stm32l1.cfg"
-source [find target/stm32l1.cfg]
diff --git a/openocd-0.10.0/scripts/target/stm32w108_stlink.cfg b/openocd-0.10.0/scripts/target/stm32w108_stlink.cfg
deleted file mode 100644
index 120feea947aabb66e5fb1abedb6d21f71a9c60b6..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32w108_stlink.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-echo "WARNING: target/stm32w108xx_stlink.cfg is deprecated, please switch to target/stm32w108xx.cfg"
-source [find target/stm32w108xx.cfg]
diff --git a/openocd-0.10.0/scripts/target/stm32w108xx.cfg b/openocd-0.10.0/scripts/target/stm32w108xx.cfg
deleted file mode 100644
index d07afc414f526c2327c346f1cecc17c96a874b2c..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32w108xx.cfg
+++ /dev/null
@@ -1,70 +0,0 @@
-#
-# Target configuration for the ST STM32W108xx chips
-#
-# Processor: ARM Cortex-M3
-# Date: 2013-06-09
-# Author: Giuseppe Barba <giuseppe.barba@gmail.com>
-
-#
-# stm32 devices support both JTAG and SWD transports.
-#
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] == 0 } {
- set _CHIPNAME stm32w108
-} else {
- set _CHIPNAME $CHIPNAME
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 8kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x2000
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- set _CPUTAPID 0x3ba00477
- } {
- set _CPUTAPID 0x1ba01477
- }
-}
-
-set _ENDIAN little
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if {[using_jtag]} {
- if { [info exists BSTAPID] } {
- set _BSTAPID $BSTAPID
- swj_newdap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id _BSTAPID
- } else {
- set _BSTAPID_1 0x169a862b
- set _BSTAPID_2 0x269a862b
- swj_newdap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf \
- -expected-id $_BSTAPID_1 -expected-id $_BSTAPID_2
- }
-}
-#
-# Set Target
-#
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-
-# Use the flash driver from the EM357
-set _FLASHNAME $_CHIPNAME.flash
-
-# 64k (0x10000) of flash
-flash bank $_FLASHNAME em357 0x08000000 0x10000 0 0 $_TARGETNAME
-
-reset_config srst_nogate
-
-if {![using_hla]} {
- cortex_m reset_config sysresetreq
-}
diff --git a/openocd-0.10.0/scripts/target/stm32xl.cfg b/openocd-0.10.0/scripts/target/stm32xl.cfg
deleted file mode 100644
index f72896d32f45120d40f608a3afddb9abf14f333d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/stm32xl.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-# script for stm32xl family (dual flash bank)
-source [find target/stm32f1x.cfg]
-
-# flash size will be probed
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/str710.cfg b/openocd-0.10.0/scripts/target/str710.cfg
deleted file mode 100644
index d26a8b1cf0650ed89b209b28245418b3e1951361..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/str710.cfg
+++ /dev/null
@@ -1,53 +0,0 @@
-#start slow, speed up after reset
-adapter_khz 10
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str710
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x3f0f0f0f
-}
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst srst_pulls_trst
-
-#jtag scan chain
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
-$_TARGETNAME configure -event reset-init {
- adapter_khz 6000
-
-# Because the hardware cannot be interrogated for the protection state
-# of sectors, initialize all the sectors to be unprotected. The initial
-# state is reflected by the driver, too.
- flash protect 0 0 last off
- flash protect 1 0 last off
-}
-$_TARGETNAME configure -event gdb-flash-erase-start {
- flash protect 0 0 7 off
- flash protect 1 0 1 off
-}
-
-$_TARGETNAME configure -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank str7x <base> <size> 0 0 <target#> <variant>
-set _FLASHNAME $_CHIPNAME.flash0
-flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME str7x 0x400C0000 0x00004000 0 0 $_TARGETNAME STR71x
diff --git a/openocd-0.10.0/scripts/target/str730.cfg b/openocd-0.10.0/scripts/target/str730.cfg
deleted file mode 100644
index 48d3134aac151c92724dcc14dd0a2bf8fca6ae14..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/str730.cfg
+++ /dev/null
@@ -1,54 +0,0 @@
-#STR730 CPU
-
-adapter_khz 3000
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str730
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x3f0f0f0f
-}
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst srst_pulls_trst
-
-#jtag scan chain
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
-
-#jtag nTRST and nSRST delay
-adapter_nsrst_delay 500
-jtag_ntrst_delay 500
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
-
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
-$_TARGETNAME configure -event reset-init {
- adapter_khz 3000
-
-# Because the hardware cannot be interrogated for the protection state
-# of sectors, initialize all the sectors to be unprotected. The initial
-# state is reflected by the driver, too.
- flash protect 0 0 last off
-}
-$_TARGETNAME configure -event gdb-flash-erase-start {
- flash protect 0 0 7 off
-}
-
-$_TARGETNAME configure -work-area-phys 0xA0000000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME str7x 0x80000000 0x00040000 0 0 $_TARGETNAME STR73x
-
diff --git a/openocd-0.10.0/scripts/target/str750.cfg b/openocd-0.10.0/scripts/target/str750.cfg
deleted file mode 100644
index ef6e7954e48dc39e57ffc4cf31e93d03852962bb..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/str750.cfg
+++ /dev/null
@@ -1,72 +0,0 @@
-#STR750 CPU
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str750
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4f1f0041
-}
-
-# jtag speed
-adapter_khz 10
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst srst_pulls_trst
-
-#jtag scan chain
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
-
-#jtag nTRST and nSRST delay
-adapter_nsrst_delay 500
-jtag_ntrst_delay 500
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
-
-$_TARGETNAME configure -event reset-start { adapter_khz 10 }
-$_TARGETNAME configure -event reset-init {
- adapter_khz 3000
-
- init_smi
-# Because the hardware cannot be interrogated for the protection state
-# of sectors, initialize all the sectors to be unprotected. The initial
-# state is reflected by the driver, too.
- flash protect 0 0 last off
- flash protect 1 0 last off
-}
-$_TARGETNAME configure -event gdb-flash-erase-start {
- flash protect 0 0 7 off
- flash protect 1 0 1 off
-}
-
-$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-set _FLASHNAME $_CHIPNAME.flash0
-flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 $_TARGETNAME STR75x
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 $_TARGETNAME STR75x
-
-# Serial NOR on SMI CS0.
-set _FLASHNAME $_CHIPNAME.snor
-flash bank $_FLASHNAME stmsmi 0x80000000 0 0 0 $_TARGETNAME
-
-source [find mem_helper.tcl]
-
-proc init_smi {} {
- mmw 0x60000030 0x01000000 0x00000000; # enable clock for GPIO regs
- mmw 0xffffe420 0x00000001 0x00000000; # set SMI_EN bit
- mmw 0x90000000 0x00000001 0x00000000; # set BLOCK_EN_1
-}
diff --git a/openocd-0.10.0/scripts/target/str912.cfg b/openocd-0.10.0/scripts/target/str912.cfg
deleted file mode 100644
index 36c0b2a544721a4dd35e4bf986f58f0d2361dbe0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/str912.cfg
+++ /dev/null
@@ -1,71 +0,0 @@
-# script for str9
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str912
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# jtag speed. We need to stick to 16kHz until we've finished reset.
-adapter_khz 16
-
-adapter_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-
-if { [info exists FLASHTAPID] } {
- set _FLASHTAPID $FLASHTAPID
-} else {
- set _FLASHTAPID 0x04570041
-}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x25966041
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-
-if { [info exists BSTAPID] } {
- set _BSTAPID $BSTAPID
-} else {
- # possible values: 0x1457f041, 0x2457f041
- # we ignore version in check below
- set _BSTAPID 0x1457f041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID -ignore-version
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -event reset-start { adapter_khz 16 }
-
-$_TARGETNAME configure -event reset-init {
- # We can increase speed now that we know the target is halted.
- #adapter_khz 3000
-
- # -- Enable 96K RAM
- # PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
-
- str9x flash_config 0 4 2 0 0x80000
- flash protect 0 0 7 off
-}
-
-$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
-
-#flash bank str9x <base> <size> 0 0 <target#> <variant>
-set _FLASHNAME $_CHIPNAME.flash0
-flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 $_TARGETNAME
-set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 $_TARGETNAME
diff --git a/openocd-0.10.0/scripts/target/swj-dp.tcl b/openocd-0.10.0/scripts/target/swj-dp.tcl
deleted file mode 100644
index 1d274cb1290cbb73e6efdd64d2ef82b529732ac0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/swj-dp.tcl
+++ /dev/null
@@ -1,34 +0,0 @@
-# ARM Debug Interface V5 (ADI_V5) utility
-# ... Mostly for SWJ-DP (not SW-DP or JTAG-DP, since
-# SW-DP and JTAG-DP targets don't need to switch based
-# on which transport is active.
-#
-# declare a JTAG or SWD Debug Access Point (DAP)
-# based on the transport in use with this session.
-# You can't access JTAG ops when SWD is active, etc.
-
-# params are currently what "jtag newtap" uses
-# because OpenOCD internals are still strongly biased
-# to JTAG .... but for SWD, "irlen" etc are ignored,
-# and the internals work differently
-
-# for now, ignore non-JTAG and non-SWD transports
-# (e.g. initial flash programming via SPI or UART)
-
-# split out "chip" and "tag" so we can someday handle
-# them more uniformly irlen too...)
-
-if [catch {transport select}] {
- echo "Error: unable to select a session transport. Can't continue."
- shutdown
-}
-
-proc swj_newdap {chip tag args} {
- if [using_hla] {
- eval hla newtap $chip $tag $args
- } elseif [using_jtag] {
- eval jtag newtap $chip $tag $args
- } elseif [using_swd] {
- eval swd newdap $chip $tag $args
- }
-}
diff --git a/openocd-0.10.0/scripts/target/test_reset_syntax_error.cfg b/openocd-0.10.0/scripts/target/test_reset_syntax_error.cfg
deleted file mode 100644
index cb4e46fa4efeeb264a5fc112c765151f875ef0cc..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/test_reset_syntax_error.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-# Test script to check that syntax error in reset
-# script is reported properly.
-
-# at91eb40a target
-
-#jtag scan chain
-set _CHIPNAME syntaxtest
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
-
-#target configuration
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -event reset-init {
-
- syntax error
-}
diff --git a/openocd-0.10.0/scripts/target/test_syntax_error.cfg b/openocd-0.10.0/scripts/target/test_syntax_error.cfg
deleted file mode 100644
index d4f92fab7b3911c967a388fbedfe9e2bfdcdfa60..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/test_syntax_error.cfg
+++ /dev/null
@@ -1,4 +0,0 @@
-# This script tests a syntax error in the startup
-# config script
-
-syntax error here
diff --git a/openocd-0.10.0/scripts/target/ti-ar7.cfg b/openocd-0.10.0/scripts/target/ti-ar7.cfg
deleted file mode 100644
index 19d8c6f349c4085af375c4514039e05e89ffd7e3..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ti-ar7.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-#
-# Texas Instruments AR7 SOC - used in many adsl modems.
-# http://www.linux-mips.org/wiki/AR7
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME ti-ar7
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x0000100f
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_CHIPNAME.cpu
-
-# use onboard 4k sram as working area
-$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x00001000
diff --git a/openocd-0.10.0/scripts/target/ti-cjtag.cfg b/openocd-0.10.0/scripts/target/ti-cjtag.cfg
deleted file mode 100644
index 7114b2adf9df23aceae0ebbe0770d6a0504aaab4..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ti-cjtag.cfg
+++ /dev/null
@@ -1,32 +0,0 @@
-# A start sequence to change from cJTAG to 4-pin JTAG
-# This is needed for CC2538 and CC26xx to be able to communicate through JTAG
-# Read section 6.3 in http://www.ti.com/lit/pdf/swru319 for more information.
-proc ti_cjtag_to_4pin_jtag {jrc} {
- # Bypass
- irscan $jrc 0x3f -endstate RUN/IDLE
- # Two zero bit scans and a one bit drshift
- pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
- pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
- pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
- pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
- pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
- pathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRUPDATE RUN/IDLE
- pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
-
- # A two bit drhift and a 9 bit drshift
- pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRUPDATE RUN/IDLE
- pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
- pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
- pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
- pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
- pathmove DRPAUSE DREXIT2 DRSHIFT DRSHIFT DREXIT1 DRPAUSE
- pathmove DRPAUSE DREXIT2 DRSHIFT DREXIT1 DRPAUSE
- pathmove DRPAUSE DREXIT2 DRUPDATE RUN/IDLE
- pathmove RUN/IDLE DRSELECT DRCAPTURE DREXIT1 DRPAUSE
-
- # Bypass
- irscan $jrc 0x3f -endstate RUN/IDLE
-
- # Set ICEPick IDCODE in data register
- irscan $jrc 0x04 -endstate RUN/IDLE
-}
diff --git a/openocd-0.10.0/scripts/target/ti_calypso.cfg b/openocd-0.10.0/scripts/target/ti_calypso.cfg
deleted file mode 100644
index 9d3b293eebde6cbe8a5a5afba958b4a09a7e224e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ti_calypso.cfg
+++ /dev/null
@@ -1,57 +0,0 @@
-#
-# TI Calypso (lite) G2 C035 Digital Base Band chip
-#
-# ARM7TDMIE + DSP subchip (S28C128)
-#
-# 512K SRAM Calypso
-# 256K SRAM Calypso lite
-#
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME calypso
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x3100e02f
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 64kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x10000
-}
-
-adapter_khz 1000
-
-reset_config trst_and_srst
-
-jtag newtap $_CHIPNAME dsp -expected-id 0x00000000 -irlen 8
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# target
-
-set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm7tdmi -endian little -chain-position $_TARGETNAME
-
-# workarea
-
-$_TARGETNAME configure -work-area-phys 0x00800000 -work-area-size $_WORKAREASIZE -work-area-backup 1
-
-arm7_9 dcc_downloads enable
-arm7_9 fast_memory_access enable
-
-$_TARGETNAME configure -event examine-start {
- irscan calypso.arm 0x0b -endstate DRPAUSE
- drscan calypso.arm 2 2 -endstate RUN/IDLE
-}
diff --git a/openocd-0.10.0/scripts/target/ti_dm355.cfg b/openocd-0.10.0/scripts/target/ti_dm355.cfg
deleted file mode 100644
index 4f8f523e889ded0fbc8b04381b4932d862bbd300..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ti_dm355.cfg
+++ /dev/null
@@ -1,109 +0,0 @@
-#
-# Texas Instruments DaVinci family: TMS320DM355
-#
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME dm355
-}
-
-# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
-# after JTAG reset until ICEpick is used to route them in.
-set EMU01 "-disable"
-
-# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
-# needing any ICEpick interaction.
-#set EMU01 "-enable"
-
-source [find target/icepick.cfg]
-
-#
-# Also note: when running without RTCK before the PLLs are set up, you
-# may need to slow the JTAG clock down quite a lot (under 2 MHz).
-#
-
-# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
-if { [info exists ETB_TAPID] } {
- set _ETB_TAPID $ETB_TAPID
-} else {
- set _ETB_TAPID 0x2b900f0f
-}
-jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
-jtag configure $_CHIPNAME.etb -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 1"
-
-# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
-if { [info exists CPU_TAPID] } {
- set _CPU_TAPID $CPU_TAPID
-} else {
- set _CPU_TAPID 0x07926001
-}
-jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
-jtag configure $_CHIPNAME.arm -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 0"
-
-# Primary TAP: ICEpick (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x0b73b02f
-}
-jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
-
-jtag configure $_CHIPNAME.jrc -event setup \
- "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
-
-################
-
-# various symbol definitions, to avoid hard-wiring addresses
-# and enable some sharing of DaVinci-family utility code
-global dm355
-set dm355 [ dict create ]
-
-# Physical addresses for controllers and memory
-# (Some of these are valid for many DaVinci family chips)
-dict set dm355 sram0 0x00010000
-dict set dm355 sram1 0x00014000
-dict set dm355 sysbase 0x01c40000
-dict set dm355 pllc1 0x01c40800
-dict set dm355 pllc2 0x01c40c00
-dict set dm355 psc 0x01c41000
-dict set dm355 gpio 0x01c67000
-dict set dm355 a_emif 0x01e10000
-dict set dm355 a_emif_cs0 0x02000000
-dict set dm355 a_emif_cs1 0x04000000
-dict set dm355 ddr_emif 0x20000000
-dict set dm355 ddr 0x80000000
-dict set dm355 uart0 0x01c20000
-dict set dm355 uart1 0x01c20400
-dict set dm355 uart2 0x01e06000
-
-source [find target/davinci.cfg]
-
-################
-# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
-# and the ETB memory (4K) are other options, while trace is unused.
-set _TARGETNAME $_CHIPNAME.arm
-
-target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
-
-# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
-# and that the work area is used only with a kernel mmu context ...
-$_TARGETNAME configure \
- -work-area-virt [expr 0xfffe0000 + 0x4000] \
- -work-area-phys [dict get $dm355 sram1] \
- -work-area-size 0x4000 \
- -work-area-backup 0
-
-# be absolutely certain the JTAG clock will work with the worst-case
-# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
-# on the PLL and starts using it. OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
-
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-# trace setup
-etm config $_TARGETNAME 16 normal full etb
-etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/openocd-0.10.0/scripts/target/ti_dm365.cfg b/openocd-0.10.0/scripts/target/ti_dm365.cfg
deleted file mode 100644
index 0db83dbaa3cde90840fe253aea20c19756e6a9de..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ti_dm365.cfg
+++ /dev/null
@@ -1,101 +0,0 @@
-#
-# Texas Instruments DaVinci family: TMS320DM365
-#
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME dm365
-}
-
-# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
-# after JTAG reset until ICEpick is used to route them in.
-set EMU01 "-disable"
-
-# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
-# needing any ICEpick interaction.
-#set EMU01 "-enable"
-
-source [find target/icepick.cfg]
-
-# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
-if { [info exists ETB_TAPID] } {
- set _ETB_TAPID $ETB_TAPID
-} else {
- set _ETB_TAPID 0x2b900f0f
-}
-jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
-jtag configure $_CHIPNAME.etb -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 1"
-
-# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
-if { [info exists CPU_TAPID] } {
- set _CPU_TAPID $CPU_TAPID
-} else {
- set _CPU_TAPID 0x0792602f
-}
-jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
-jtag configure $_CHIPNAME.arm -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 0"
-
-# Primary TAP: ICEpick (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x0b83e02f
-}
-jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
-
-jtag configure $_CHIPNAME.jrc -event setup \
- "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
-
-################
-
-# various symbol definitions, to avoid hard-wiring addresses
-# and enable some sharing of DaVinci-family utility code
-global dm365
-set dm365 [ dict create ]
-
-# Physical addresses for controllers and memory
-# (Some of these are valid for many DaVinci family chips)
-dict set dm365 sram0 0x00010000
-dict set dm365 sram1 0x00014000
-dict set dm365 sysbase 0x01c40000
-dict set dm365 pllc1 0x01c40800
-dict set dm365 pllc2 0x01c40c00
-dict set dm365 psc 0x01c41000
-dict set dm365 gpio 0x01c67000
-dict set dm365 a_emif 0x01d10000
-dict set dm365 a_emif_cs0 0x02000000
-dict set dm365 a_emif_cs1 0x04000000
-dict set dm365 ddr_emif 0x20000000
-dict set dm365 ddr 0x80000000
-
-source [find target/davinci.cfg]
-
-################
-# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
-# and the ETB memory (4K) are other options, while trace is unused.
-set _TARGETNAME $_CHIPNAME.arm
-
-target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
-
-# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
-# and that the work area is used only with a kernel mmu context ...
-$_TARGETNAME configure \
- -work-area-virt [expr 0xfffe0000 + 0x4000] \
- -work-area-phys [dict get $dm365 sram1] \
- -work-area-size 0x4000 \
- -work-area-backup 0
-
-# be absolutely certain the JTAG clock will work with the worst-case
-# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
-# on the PLL and starts using it. OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
-
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-# trace setup
-etm config $_TARGETNAME 16 normal full etb
-etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/openocd-0.10.0/scripts/target/ti_dm6446.cfg b/openocd-0.10.0/scripts/target/ti_dm6446.cfg
deleted file mode 100644
index fa1e6e957c316cb74552198aa9daacee9fcc5153..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ti_dm6446.cfg
+++ /dev/null
@@ -1,81 +0,0 @@
-#
-# Texas Instruments DaVinci family: TMS320DM6446
-#
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME dm6446
-}
-
-# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
-# after JTAG reset until ICEpick is used to route them in.
-set EMU01 "-disable"
-
-# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
-# needing any ICEpick interaction.
-#set EMU01 "-enable"
-
-source [find target/icepick.cfg]
-
-# Subsidiary TAP: unknown ... must enable via ICEpick
-jtag newtap $_CHIPNAME unknown -irlen 8 -disable
-jtag configure $_CHIPNAME.unknown -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 3"
-
-# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
-jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
-jtag configure $_CHIPNAME.dsp -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 2"
-
-# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
-if { [info exists ETB_TAPID] } {
- set _ETB_TAPID $ETB_TAPID
-} else {
- set _ETB_TAPID 0x2b900f0f
-}
-jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
-jtag configure $_CHIPNAME.etb -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 1"
-
-# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
-if { [info exists CPU_TAPID] } {
- set _CPU_TAPID $CPU_TAPID
-} else {
- set _CPU_TAPID 0x07926001
-}
-jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
-jtag configure $_CHIPNAME.arm -event tap-enable \
- "icepick_c_tapenable $_CHIPNAME.jrc 0"
-
-# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
-if { [info exists JRC_TAPID] } {
- set _JRC_TAPID $JRC_TAPID
-} else {
- set _JRC_TAPID 0x0b70002f
-}
-jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
-
-jtag configure $_CHIPNAME.jrc -event setup \
- "jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
-
-################
-# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
-# and the ETB memory (4K) are other options, while trace is unused.
-# Little-endian; use the OpenOCD default.
-set _TARGETNAME $_CHIPNAME.arm
-
-target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
-$_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
-
-# be absolutely certain the JTAG clock will work with the worst-case
-# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
-# on the PLL and starts using it. OK to speed up after clock setup.
-adapter_khz 1500
-$_TARGETNAME configure -event "reset-start" { adapter_khz 1500 }
-
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-# trace setup
-etm config $_TARGETNAME 16 normal full etb
-etb config $_TARGETNAME $_CHIPNAME.etb
diff --git a/openocd-0.10.0/scripts/target/ti_msp432p4xx.cfg b/openocd-0.10.0/scripts/target/ti_msp432p4xx.cfg
deleted file mode 100644
index 8600867077c7433272961f3097526633ea929a96..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ti_msp432p4xx.cfg
+++ /dev/null
@@ -1,52 +0,0 @@
-#
-# Texas Instruments MSP432P4xx - ARM Cortex-M4F @ up to 48 MHz
-#
-# http://www.ti.com/MSP432
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME msp432p4xx
-}
-
-if { [info exists CPUTAPID] } {
- set _DAP_TAPID $CPUTAPID
-} else {
- set _DAP_TAPID 0x4ba00477
-}
-
-if { [info exists DAP_SWD_ID] } {
- set _DAP_SWD_ID $DAP_SWD_ID
-} else {
- set _DAP_SWD_ID 0x2ba01477
-}
-
-source [find target/swj-dp.tcl]
-
-if { [using_jtag] } {
- set _DAP_ID $_DAP_TAPID
-} else {
- set _DAP_ID $_DAP_SWD_ID
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- # On MSP432P401x Bank0 (8k) is always powered
- set _WORKAREASIZE 0x2000
-}
-
-$_TARGETNAME configure -work-area-phys 0x20000000 \
- -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-if { ![using_hla] } {
- cortex_m reset_config sysresetreq
-}
-
-adapter_khz 500
diff --git a/openocd-0.10.0/scripts/target/ti_rm4x.cfg b/openocd-0.10.0/scripts/target/ti_rm4x.cfg
deleted file mode 100644
index 85c3e814b37015d8fefb0b54421a47994d6b190a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ti_rm4x.cfg
+++ /dev/null
@@ -1 +0,0 @@
-source [find target/ti_tms570.cfg]
diff --git a/openocd-0.10.0/scripts/target/ti_tms570.cfg b/openocd-0.10.0/scripts/target/ti_tms570.cfg
deleted file mode 100644
index 21da6c017a0a8f32e9eb7cf9b261a457ecce1b6a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ti_tms570.cfg
+++ /dev/null
@@ -1,74 +0,0 @@
-adapter_khz 1500
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME tms570
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN big
-}
-
-# TMS570 has an ICEpick-C on which we need the router commands.
-source [find target/icepick.cfg]
-
-# Main DAP
-# DAP_TAPID should be set before source-ing this file
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-}
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
-
-# ICEpick-C (JTAG route controller)
-# JRC_TAPID should be set before source-ing this file
-if { [info exists JRC_TAPID] } {
- set _JRC_TAPID $JRC_TAPID
-}
-
-set _JRC_TAPID2 0x0B7B302F
-set _JRC_TAPID3 0x0B95502F
-set _JRC_TAPID4 0x0B97102F
-set _JRC_TAPID5 0x0D8A002F
-set _JRC_TAPID6 0x2B8A002F
-set _JRC_TAPID7 0x2D8A002F
-set _JRC_TAPID8 0x3B8A002F
-set _JRC_TAPID9 0x3D8A002F
-
-
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
- -expected-id $_JRC_TAPID \
- -expected-id $_JRC_TAPID2 \
- -expected-id $_JRC_TAPID3 \
- -expected-id $_JRC_TAPID4 \
- -expected-id $_JRC_TAPID5 \
- -expected-id $_JRC_TAPID6 \
- -expected-id $_JRC_TAPID7 \
- -expected-id $_JRC_TAPID8 \
- -expected-id $_JRC_TAPID9 \
- -ignore-version
-jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
-jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
-
-# Cortex-R4 target
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_r4 -endian $_ENDIAN \
- -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x00001003
-
-# TMS570 uses quirky BE-32 mode
-$_TARGETNAME dap ti_be_32_quirks 1
-
-$_TARGETNAME configure -event gdb-attach {
- cortex_r4 dbginit
- halt
-}
-
-$_TARGETNAME configure -event "reset-assert" {
- global _CHIPNAME
-
- # assert warm system reset through ICEPick
- icepick_c_wreset $_CHIPNAME.jrc
-}
diff --git a/openocd-0.10.0/scripts/target/ti_tms570ls20xxx.cfg b/openocd-0.10.0/scripts/target/ti_tms570ls20xxx.cfg
deleted file mode 100644
index ef45b7a5cb654df63367365e4374276d878c6377..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ti_tms570ls20xxx.cfg
+++ /dev/null
@@ -1,6 +0,0 @@
-# TMS570LS20216, TMS570LS20206, TMS570LS10216
-# TMS570LS10206, TMS570LS10116, TMS570LS10106
-set DAP_TAPID 0x0B7B302F
-set JRC_TAPID 0x0B7B302F
-
-source [find target/ti_tms570.cfg]
diff --git a/openocd-0.10.0/scripts/target/ti_tms570ls3137.cfg b/openocd-0.10.0/scripts/target/ti_tms570ls3137.cfg
deleted file mode 100644
index f29180356b5284d9dae5a65090cbc375f3dad225..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/ti_tms570ls3137.cfg
+++ /dev/null
@@ -1,5 +0,0 @@
-# TMS570LS3137
-set DAP_TAPID 0x0B8A002F
-set JRC_TAPID 0x0B8A002F
-
-source [find target/ti_tms570.cfg]
diff --git a/openocd-0.10.0/scripts/target/tmpa900.cfg b/openocd-0.10.0/scripts/target/tmpa900.cfg
deleted file mode 100644
index 3ba3591beb263fe17778b98a36fa20b632809742..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/tmpa900.cfg
+++ /dev/null
@@ -1,46 +0,0 @@
-######################################
-# Target: Toshiba TMPA900
-######################################
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME tmpa900
-}
-
-# Toshiba TMPA900 series MCUs are always little endian as per datasheet.
-set _ENDIAN little
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07926031
-}
-
-#TMPA900 has following IDs:
-# CP15.0 register 0x41069265
-# CP15.1 register 0x1d152152
-# ARM core 0x07926031
-
-
-#
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-adapter_nsrst_delay 20
-jtag_ntrst_delay 20
-
-######################
-# Target configuration
-######################
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# Internal RAM-0 (16kB): 0xf8004000
-# Internal RAM-1 (8kB): 0xf8008000
-
-# Use internal RAM-0 and RAM-1 as working area (24kB total).
-$_TARGETNAME configure -work-area-phys 0xf8004000 -work-area-size 0x6000 \
--work-area-backup 0
diff --git a/openocd-0.10.0/scripts/target/tmpa910.cfg b/openocd-0.10.0/scripts/target/tmpa910.cfg
deleted file mode 100644
index 5d41c8c2ad7076c26809dd69fceba15bc3b3ead7..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/tmpa910.cfg
+++ /dev/null
@@ -1,47 +0,0 @@
-######################################
-# Target: Toshiba TMPA910
-######################################
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME tmpa910
-}
-
-# Toshiba TMPA910 series MCUs are always little endian as per datasheet.
-set _ENDIAN little
-
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x07926031
-}
-
-#TMPA910 has following IDs:
-# CP15.0 register 0x41069265
-# CP15.1 register 0x1d152152
-# ARM core 0x07926031
-
-
-#
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-adapter_nsrst_delay 20
-jtag_ntrst_delay 20
-
-######################
-# Target configuration
-######################
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
-
-# Internal RAM-0 (16kB): 0xf8004000
-# Internal RAM-1 (16kB): 0xf8008000
-# Internal RAM-2 (16kB): 0xf800c000
-
-# Use internal RAM-0, RAM-1, and RAM-2 as working area (48kB total).
-$_TARGETNAME configure -work-area-phys 0xf8004000 -work-area-size 0xc000 \
--work-area-backup 0
diff --git a/openocd-0.10.0/scripts/target/u8500.cfg b/openocd-0.10.0/scripts/target/u8500.cfg
deleted file mode 100644
index 66fc075c222e7f1278526ae4e318c2c627899071..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/u8500.cfg
+++ /dev/null
@@ -1,332 +0,0 @@
-# Copyright (C) ST-Ericsson SA 2011
-# Author : michel.jaouen@stericsson.com
-# U8500 target
-
-proc mmu_off {} {
- set cp [arm mrc 15 0 1 0 0]
- set cp [expr ($cp & ~1)]
- arm mcr 15 0 1 0 0 $cp
-}
-
-proc mmu_on {} {
- set cp [arm mrc 15 0 1 0 0]
- set cp [expr ($cp | 1)]
- arm mcr 15 0 1 0 0 $cp
-}
-
-proc ocd_gdb_restart {target_id} {
- global _TARGETNAME_1
- global _SMP
- targets $_TARGETNAME_1
- if { [expr ($_SMP == 1)] } {
- cortex_a smp_off
- }
- rst_run
- halt
- if { [expr ($_SMP == 1)]} {
- cortex_a smp_on
- }
-}
-
-proc smp_reg {} {
- global _TARGETNAME_1
- global _TARGETNAME_2
- targets $_TARGETNAME_1
- echo "$_TARGETNAME_1"
- set pc1 [reg pc]
- set stck1 [reg sp_svc]
- targets $_TARGETNAME_2
- echo "$_TARGETNAME_1"
- set pc2 [reg pc]
- set stck2 [reg sp_svc]
-}
-
-
-proc u8500_tapenable {chip val} {
- echo "JTAG tap enable $chip"
-}
-
-
-proc pwrsts { } {
- global _CHIPNAME
- irscan $_CHIPNAME.jrc 0x3a
- drscan $_CHIPNAME.jrc 4 0
- set pwrsts [drscan $_CHIPNAME.jrc 16 0]
- echo "pwrsts ="$pwrsts
- set a9 [expr (0x$pwrsts & 0xc)]
- set ape [expr (0x$pwrsts & 0x3)]
- if {[string equal "0" $ape]} {
- echo "ape off"
- } else {
- echo "ape on"
- }
- echo "$a9"
- switch $a9 {
- 4 {
- echo "A9 in retention"
- }
- 8 {
- echo "A9 100% DVFS"
- }
- c {
- echo "A9 50% DVFS"
- }
- }
-}
-
-proc poll_pwrsts { } {
- global _CHIPNAME
- set result 1
- set i 0
- irscan $_CHIPNAME.jrc 0x3a
- drscan $_CHIPNAME.jrc 4 0
- set pwrsts [drscan $_CHIPNAME.jrc 16 0]
- set pwrsts [expr (0x$pwrsts & 0xc)]
- while {[string equal "4" $pwrsts] && $i<20} {
- irscan $_CHIPNAME.jrc 0x3a
- drscan $_CHIPNAME.jrc 4 0;
- set pwrsts [drscan $_CHIPNAME.jrc 16 0]
- set pwrsts [expr (0x$pwrsts & 0xc)]
- if {![string equal "4" $pwrsts]} {
- set result 1
- } else {
- set result 0
- sleep 200
- echo "loop $i"
- }
- incr i
- }
- return $result
-}
-
-proc halt_ { } {
- if {[poll_pwrsts]==1} {
- halt
- } else {
- echo "halt failed : target in retention"
- }
-}
-
-
-proc u8500_dapenable {chip} {
-}
-
-proc u8500_tapdisable {chip val} {
- echo "JTAG tap disable $chip"
-}
-
-
-proc enable_apetap {} {
- global _CHIPNAME
- global _TARGETNAME_2
- global _TARGETNAME_1
- poll off
- irscan $_CHIPNAME.jrc 0x3e
- drscan $_CHIPNAME.jrc 8 0xcf
- jtag tapenable $_CHIPNAME.dap
- irscan $_CHIPNAME.jrc 0x6
- drscan $_CHIPNAME.jrc 32 0
- irscan $_CHIPNAME.jrc 0x6
- drscan $_CHIPNAME.jrc 32 0
- set status [$_TARGETNAME_1 curstate]
- if {[string equal "unknown" $status]} {
- $_TARGETNAME_1 arp_examine
- cache_config l2x 0xa0412000 8
- }
-
- set status [$_TARGETNAME_2 curstate]
- if {[string equal "unknown" $status]} {
- $_TARGETNAME_2 arp_examine
- }
- }
-
-tcl_port 5555
-telnet_port 4444
-gdb_port 3333
-
-if { [info exists CHIPNAME] } {
-global _CHIPNAME
- set _CHIPNAME $CHIPNAME
-} else {
-global _CHIPNAME
- set _CHIPNAME u8500
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a bigendian
- set _ENDIAN little
-}
-
-
-
-# Subsidiary TAP: APE with scan chains for ARM Debug, EmbeddedICE-RT,
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x4ba00477
-}
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_CPUTAPID -disable
-jtag configure $_CHIPNAME.dap -event tap-enable \
- "u8500_dapenable $_CHIPNAME.dap"
-jtag configure $_CHIPNAME.dap -event tap-disable \
- "u8500_tapdisable $_CHIPNAME.dap 0xc0"
-
-
-#CLTAPC TAP JRC equivalent
-if { [info exists CLTAPC_ID] } {
- set _CLTAPC_ID $CLTAPC_ID
-} else {
- set _CLTAPC_ID 0x22286041
-}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x6 -irmask 0xf -expected-id $_CLTAPC_ID -ignore-version
-
-
-if { ![info exists TARGETNAME_1] } {
-global _TARGETNAME_1
-set _TARGETNAME_1 $_CHIPNAME.cpu1
-} else {
-global _TARGETNAME_1
-set _TARGETNAME_1 $TARGETNAME_1
-}
-
-if { [info exists DAP_DBG1] } {
- set _DAP_DBG1 $DAP_DBG1
-} else {
- set _DAP_DBG1 0x801A8000
-}
-if { [info exists DAP_DBG2] } {
- set _DAP_DBG2 $DAP_DBG2
-} else {
- set _DAP_DBG2 0x801AA000
-}
-
-target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
-
-$_TARGETNAME_1 configure -event gdb-attach {
- halt
-}
-
-
-if { ![info exists TARGETNAME_2] } {
-global _TARGETNAME_2
-set _TARGETNAME_2 $_CHIPNAME.cpu2
-} else {
-global _TARGETNAME_2
-set _TARGETNAME_2 $TARGETNAME_2
-}
-
-target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
-
-$_TARGETNAME_2 configure -event gdb-attach {
- halt
-}
-
-
-if {![info exists SMP]} {
-global _SMP
-set _SMP 1
-} else {
-global _SMP
-set _SMP $SMP
-}
-global SMP
-if { $_SMP == 1} {
-target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
-}
-
-
-
-
-proc secsts1 { } {
- global _CHIPNAME
- irscan $_CHIPNAME.jrc 0x3a
- drscan $_CHIPNAME.jrc 4 4
- set secsts1 [drscan $_CHIPNAME.jrc 16 0]
- echo "secsts1 ="$secsts1
- set secsts1 [expr (0x$secsts1 & 0x4)]
- if {![string equal "4" $secsts1]} {
- echo "APE target secured"
- } else {
- echo "APE target not secured"
- }
-}
-
-proc att { } {
- global _CHIPNAME
- jtag arp_init
- irscan $_CHIPNAME.jrc 0x3a
- drscan $_CHIPNAME.jrc 4 4
- set secsts1 [drscan $_CHIPNAME.jrc 16 0]
- echo "secsts1 ="$secsts1
- set secsts1 [expr (0x$secsts1 & 0x4)]
- if {[string equal "4" $secsts1]} {
- if {[poll_pwrsts]==1} {
- enable_apetap
- } else {
- echo "target in retention"
- }
- } else {
- echo "target secured"
- }
-
-}
-
-
-
-proc rst_run { } {
- global _CHIPNAME
- global _TARGETNAME_2
- global _TARGETNAME_1
- set status [$_TARGETNAME_1 curstate]
- if {[string equal "halted" $status]} {
- resume
- targets $_TARGETNAME_1
- }
- set status [$_TARGETNAME_2 curstate]
- if {[string equal "halted" $status]} {
- resume
- targets $_TARGETNAME_2
- }
- poll off
- jtag arp_init
- reset
- sleep 20
- irscan $_CHIPNAME.jrc 0x3a
- drscan $_CHIPNAME.jrc 4 4
- set secsts1 [drscan $_CHIPNAME.jrc 16 0]
- echo "secsts1 ="$secsts1
- set secsts1 [expr (0x$secsts1 & 0x4)]
- while {![string equal "4" $secsts1]} {
- irscan u8500.jrc 0x3a
- drscan u8500.jrc 4 4
- set secsts1 [drscan $_CHIPNAME.jrc 16 0]
- echo "secsts1 ="$secsts1
- set secsts1 [expr (0x$secsts1 & 0x4)]
- }
- echo "ape debugable"
- enable_apetap
- poll on
- targets $_TARGETNAME_1
- dap apsel 1
-}
-
-if {![info exists MAXSPEED]} {
-global _MAXSPEED
-set _MAXSPEED 15000
-} else {
-global _MAXSPEED
-set _MAXSPEED $MAXSPEED
-}
-global _MAXSPEED
-adapter_khz $_MAXSPEED
-
-
-gdb_breakpoint_override hard
-set mem inaccessible-by-default-off
-
-jtag_ntrst_delay 100
-reset_config trst_and_srst combined
-
-
diff --git a/openocd-0.10.0/scripts/target/vybrid_vf6xx.cfg b/openocd-0.10.0/scripts/target/vybrid_vf6xx.cfg
deleted file mode 100644
index 6ec4b35cd2caa5cd5d897517e3a79dc863043c1d..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/vybrid_vf6xx.cfg
+++ /dev/null
@@ -1,36 +0,0 @@
-#
-# Freescale Vybrid VF610
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME vf610
-}
-
-if { [info exists A5_JTAG_TAPID] } {
- set _A5_JTAG_TAPID $A5_JTAG_TAPID
-} else {
- set _A5_JTAG_TAPID 0x4BA00477
-}
-
-if { [info exists A5_SWD_TAPID] } {
- set _A5_SWD_TAPID $A5_SWD_TAPID
-} else {
- set _A5_SWD_TAPID 0x3BA02477
-}
-
-if { [using_jtag] } {
- set _A5_TAPID $_A5_JTAG_TAPID
-} else {
- set _A5_TAPID $_A5_SWD_TAPID
-}
-
-source [find target/swj-dp.tcl]
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_A5_TAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.cpu -dbgbase 0xc0088000
-
-adapter_khz 1000
diff --git a/openocd-0.10.0/scripts/target/xmc1xxx.cfg b/openocd-0.10.0/scripts/target/xmc1xxx.cfg
deleted file mode 100644
index d3123c4376275cdae560ac44a44efbe330c84f38..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/xmc1xxx.cfg
+++ /dev/null
@@ -1,40 +0,0 @@
-#
-# Infineon XMC1100/XMC1200/XMC1300 family (ARM Cortex-M0 @ 32 MHz)
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME xmc1000
-}
-
-#
-# Only SWD and SPD supported
-#
-source [find target/swj-dp.tcl]
-
-if { [info exists CPUTAPID] } {
- set _CPU_SWD_TAPID $CPUTAPID
-} else {
- set _CPU_SWD_TAPID 0x0BB11477
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_SWD_TAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
-
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x4000
-}
-
-$_TARGETNAME configure -work-area-phys 0x20000000 \
- -work-area-size $_WORKAREASIZE \
- -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME xmc1xxx 0x10000000 0 0 0 $_TARGETNAME
-
-adapter_khz 1000
diff --git a/openocd-0.10.0/scripts/target/xmc4xxx.cfg b/openocd-0.10.0/scripts/target/xmc4xxx.cfg
deleted file mode 100644
index bc007779977f3bd516720a8bd9ae3bcfcb655c8a..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/xmc4xxx.cfg
+++ /dev/null
@@ -1,59 +0,0 @@
-#
-# Infineon XMC4100/XMC4200/XMC4400/XMC4500 family (ARM Cortex-M4 @ 80-120 MHz)
-#
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME xmc4000
-}
-
-source [find target/swj-dp.tcl]
-
-#
-# SWJ-DP
-#
-if { [info exists CPU_JTAG_TAPID] } {
- set _CPU_JTAG_TAPID $CPU_JTAG_TAPID
-} else {
- set _CPU_JTAG_TAPID 0x4BA00477
-}
-
-#
-# SW_DP
-#
-if { [info exists CPU_SWD_TAPID] } {
- set _CPU_SWD_TAPID $CPU_SWD_TAPID
-} else {
- set _CPU_SWD_TAPID 0x2BA01477
-}
-
-if { [using_jtag] } {
- set _CPU_TAPID $_CPU_JTAG_TAPID
-} else {
- set _CPU_TAPID $_CPU_SWD_TAPID
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
-
-# Work-area is a space in RAM used for flash programming
-# By default use 16 kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x1000
-}
-
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME xmc4xxx 0x0C000000 0 0 0 $_TARGETNAME
-
-if { ![using_hla] } {
- cortex_m reset_config sysresetreq
-}
-
-adapter_khz 1000
diff --git a/openocd-0.10.0/scripts/target/xmos_xs1-xau8a-10_arm.cfg b/openocd-0.10.0/scripts/target/xmos_xs1-xau8a-10_arm.cfg
deleted file mode 100644
index 3fc197a3c66f4bdb2247a75df3e3039586b2001e..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/xmos_xs1-xau8a-10_arm.cfg
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# XMOS xCORE-XA XS1-XAU8A-10: ARM Cortex-M3 @ 48 MHz
-#
-# http://www.xmos.com/products/silicon/xcore-xa/xa-series
-#
-
-if { ![info exists CHIPNAME] } {
- set CHIPNAME xcorexa
-}
-
-if { ![info exists WORKAREASIZE] } {
- # XS1-XAU8A-10-FB265: 128 KB SRAM
- set WORKAREASIZE 0x20000
-}
-
-source [find target/efm32.cfg]
diff --git a/openocd-0.10.0/scripts/target/zynq_7000.cfg b/openocd-0.10.0/scripts/target/zynq_7000.cfg
deleted file mode 100644
index b11de328791b4ea681e553e02cf41ac3573ff7e0..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/target/zynq_7000.cfg
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# Xilinx Zynq-7000 All Programmable SoC
-#
-# http://www.xilinx.com/products/silicon-devices/soc/zynq-7000/index.htm
-#
-
-set _CHIPNAME zynq
-set _TARGETNAME $_CHIPNAME.cpu
-
-jtag newtap zynq_pl bs -irlen 6 -ircapture 0x1 -irmask 0x03 \
- -expected-id 0x23727093 \
- -expected-id 0x13722093 \
- -expected-id 0x03727093
-
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
-
-target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.dap \
- -coreid 0 -dbgbase 0x80090000
-target create ${_TARGETNAME}1 cortex_a -chain-position $_CHIPNAME.dap \
- -coreid 1 -dbgbase 0x80092000
-target smp ${_TARGETNAME}0 ${_TARGETNAME}1
-
-adapter_khz 1000
-
-${_TARGETNAME}0 configure -event reset-assert-post "cortex_a dbginit"
-${_TARGETNAME}1 configure -event reset-assert-post "cortex_a dbginit"
diff --git "a/openocd-0.10.0/scripts/target/\320\2721879x\320\2611\321\217.cfg" "b/openocd-0.10.0/scripts/target/\320\2721879x\320\2611\321\217.cfg"
deleted file mode 100644
index 7d8c1135838a7aac82eb59571d5d84b54059a9c3..0000000000000000000000000000000000000000
--- "a/openocd-0.10.0/scripts/target/\320\2721879x\320\2611\321\217.cfg"
+++ /dev/null
@@ -1,35 +0,0 @@
-# СБИС К1879ХБ1Я
-# http://www.module.ru/catalog/micro/mikroshema_dekodera_cifrovogo_televizionnogo_signala_sbis_k1879hb1ya/
-
-adapter_khz 1000
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME к1879хб1я
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists DSP_TAPID] } {
- set _DSP_TAPID $DSP_TAPID
-} else {
- set _DSP_TAPID 0x2b900f0f
-}
-
-jtag newtap $_CHIPNAME dsp -irlen 4 -expected-id $_DSP_TAPID
-
-if { [info exists CPU_TAPID] } {
- set _CPU_TAPID $CPU_TAPID
-} else {
- set _CPU_TAPID 0x07b76f0f
-}
-
-jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID
-
-set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm11 -chain-position $_CHIPNAME.arm
diff --git a/openocd-0.10.0/scripts/test/selftest.cfg b/openocd-0.10.0/scripts/test/selftest.cfg
deleted file mode 100644
index be420ca0ca9c8269c729fa5b23e6c3b638e4c19f..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/test/selftest.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-
-add_help_text selftest "run selftest using working ram <tmpfile> <address> <size>"
-
-proc selftest {tmpfile address size} {
-
- for {set i 0} {$i < $size } {set i [expr $i+4]} {
- mww [expr $address+$i] $i
- }
-
- for {set i 0} {$i < 10 } {set i [expr $i+1]} {
- echo "Test iteration $i"
- dump_image $tmpfile $address $size
- verify_image $tmpfile $address bin
- load_image $tmpfile $address bin
- }
-
-}
diff --git a/openocd-0.10.0/scripts/test/syntax1.cfg b/openocd-0.10.0/scripts/test/syntax1.cfg
deleted file mode 100644
index 79d53848025dfc134b7cd1824344aa76920077aa..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/test/syntax1.cfg
+++ /dev/null
@@ -1,30 +0,0 @@
-adapter_nsrst_delay 200
-jtag_ntrst_delay 200
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst srst_pulls_trst
-
-#LPCs need reset pulled while RTCK is low. 0 to activate JTAG, power-on reset is not enough
-jtag_reset 1 1
-jtag_reset 0 0
-
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag newtap lpc2148 one -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4f1f0f0f
-
-#target configuration
-#daemon_startup reset
-
-set _TARGETNAME [format "%s.cpu" lpc2148]
-target create lpc2148.cpu arm7tdmi -endian little -work-area-size 0x4000 -work-area-phys 0x40000000 -work-area-backup 0
-
-$_TARGETNAME configure -event reset-init {
-soft_reset_halt
-mvb 0xE01FC040 0x01
-}
-
-
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765
-
diff --git a/openocd-0.10.0/scripts/tools/firmware-recovery.tcl b/openocd-0.10.0/scripts/tools/firmware-recovery.tcl
deleted file mode 100644
index 8e017ce5b3cf55d04af4b7c3f2595b5728e918ac..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/tools/firmware-recovery.tcl
+++ /dev/null
@@ -1,113 +0,0 @@
-echo "\n\nFirmware recovery helpers"
-echo "Use -c firmware_help to get help\n"
-
-set known_boards {
- "asus-rt-n16 ASUS RT-N16"
- "asus-rt-n66u ASUS RT-N66U"
- "linksys-wag200g Linksys WAG200G"
- "linksys-wrt54gl Linksys WRT54GL v1.1"
- "netgear-dg834v3 Netgear DG834G v3"
- "tp-link_tl-mr3020 TP-LINK TL-MR3020"
- "bt-homehubv1 BT HomeHub v1"
-}
-
-proc firmware_help { } {
- echo "
-Your OpenOCD command should look like this:
-openocd -f interface/<jtag adapter>.cfg -f tools/firmware-recovery.tcl -c \"<commands>*; shutdown\"
-
-Where:
-<jtag adapter> is one of the supported devices, e.g. ftdi/jtagkey2
-<commands> are firmware-recovery commands separated by semicolon
-
-Supported commands:
-firmware_help get this help
-list_boards list known boards and exit
-board <name> select board you work with
-list_partitions list partitions of the currently selected board
-dump_part <name> <filename> save partition's contents to a file
-erase_part <name> erase the given partition
-flash_part <name> <filename> erase, flash and verify the given partition
-ram_boot <filename> load binary file to RAM and run it
-adapter_khz <freq> set JTAG clock frequency in kHz
-
-For example, to clear nvram and reflash CFE on an RT-N16 using TUMPA, run:
-openocd -f interface/ftdi/tumpa.cfg -f tools/firmware-recovery.tcl \\
- -c \"board asus-rt-n16; erase_part nvram; flash_part CFE cfe-n16.bin; shutdown\"
-\n\n"
- shutdown
-}
-
-# set default, can be overriden later
-adapter_khz 1000
-
-proc get_partition { name } {
- global partition_list
- dict get $partition_list $name
-}
-
-proc partition_desc { name } { lindex [get_partition $name] 0 }
-proc partition_start { name } { lindex [get_partition $name] 1 }
-proc partition_size { name } { lindex [get_partition $name] 2 }
-
-proc list_boards { } {
- global known_boards
- echo "List of the supported boards:\n"
- echo "Board name\t\tDescription"
- echo "-----------------------------------"
- foreach i $known_boards {
- echo $i
- }
- echo "\n\n"
-}
-
-proc board { name } {
- script [find board/$name.cfg]
-}
-
-proc list_partitions { } {
- global partition_list
- set fstr "%-16s%-14s%-14s%s"
- echo "\nThe currently selected board is known to have these partitions:\n"
- echo [format $fstr Name Start Size Description]
- echo "-------------------------------------------------------"
- for {set i 0} {$i < [llength $partition_list]} {incr i 2} {
- set key [lindex $partition_list $i]
- echo [format $fstr $key [partition_start $key] [partition_size $key] [partition_desc $key]]
- }
- echo "\n\n"
-}
-
-# Magic to work with any targets, including semi-functional
-proc prepare_target { } {
- init
- catch {halt}
- catch {reset init}
- catch {halt}
-}
-
-proc dump_part { name filename } {
- prepare_target
- dump_image $filename [partition_start $name] [partition_size $name]
-}
-
-proc erase_part { name } {
- prepare_target
- flash erase_address [partition_start $name] [partition_size $name]
-}
-
-proc flash_part { name filename } {
- prepare_target
- flash write_image erase $filename [partition_start $name] bin
- echo "Verifying:"
- verify_image $filename [partition_start $name]
-}
-
-proc ram_boot { filename } {
- global ram_boot_address
- prepare_target
- load_image $filename $ram_boot_address bin
- resume $ram_boot_address
-}
-
-echo ""
diff --git a/openocd-0.10.0/scripts/tools/memtest.tcl b/openocd-0.10.0/scripts/tools/memtest.tcl
deleted file mode 100644
index 02f94d30780ec70bb11933dc799fbdf0367cfdf3..0000000000000000000000000000000000000000
--- a/openocd-0.10.0/scripts/tools/memtest.tcl
+++ /dev/null
@@ -1,189 +0,0 @@
-# Algorithms by Michael Barr, released into public domain
-# Ported to OpenOCD by Shane Volpe, additional fixes by Paul Fertser
-
-set CPU_MAX_ADDRESS 0xFFFFFFFF
-source [find bitsbytes.tcl]
-source [find memory.tcl]
-
-proc runAllMemTests { baseAddress nBytes } {
- memTestDataBus $baseAddress
- memTestAddressBus $baseAddress $nBytes
- memTestDevice $baseAddress $nBytes
-}
-
-#***********************************************************************************
-# *
-# * Function: memTestDataBus()
-# *
-# * Description: Test the data bus wiring in a memory region by
-# * performing a walking 1's test at a fixed address
-# * within that region. The address (and hence the
-# * memory region) is selected by the caller.
-# * Ported from:
-# * http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C
-# * Notes:
-# *
-# * Returns: Empty string if the test succeeds.
-# * A non-zero result is the first pattern that failed.
-# *
-#***********************************************************************************
-proc memTestDataBus { address } {
- echo "Running memTestDataBus"
-
- for {set i 0} {$i < 32} {incr i} {
- # Shift bit
- set pattern [expr {1 << $i}]
-
- # Write pattern to memory
- memwrite32 $address $pattern
-
- # Read pattern from memory
- set data [memread32 $address]
-
- if {$data != $pattern} {
- echo "FAILED DATABUS: Address: $address, Pattern: $pattern, Returned: $data"
- return $pattern
- }
- }
-}
-
-#***********************************************************************************
-# *
-# * Function: memTestAddressBus()
-# *
-# * Description: Perform a walking 1's test on the relevant bits
-# * of the address and check for aliasing. This test
-# * will find single-bit address failures such as stuck
-# * -high, stuck-low, and shorted pins. The base address
-# * and size of the region are selected by the caller.
-# * Ported from:
-# * http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C
-# *
-# * Notes: For best results, the selected base address should
-# * have enough LSB 0's to guarantee single address bit
-# * changes. For example, to test a 64-Kbyte region,
-# * select a base address on a 64-Kbyte boundary. Also,
-# * select the region size as a power-of-two--if at all
-# * possible.
-# *
-# * Returns: Empty string if the test succeeds.
-# * A non-zero result is the first address at which an
-# * aliasing problem was uncovered. By examining the
-# * contents of memory, it may be possible to gather
-# * additional information about the problem.
-# *
-#***********************************************************************************
-proc memTestAddressBus { baseAddress nBytes } {
- set addressMask [expr $nBytes - 1]
- set pattern 0xAAAAAAAA
- set antipattern 0x55555555
-
- echo "Running memTestAddressBus"
-
- echo "addressMask: [convertToHex $addressMask]"
-
- echo "memTestAddressBus: Writing the default pattern at each of the power-of-two offsets..."
- for {set offset 32} {[expr $offset & $addressMask] != 0} {set offset [expr $offset << 1] } {
- set addr [expr $baseAddress + $offset]
- memwrite32 $addr $pattern
- }
-
- echo "memTestAddressBus: Checking for address bits stuck high..."
- memwrite32 $baseAddress $antipattern
-
- for {set offset 32} {[expr $offset & $addressMask] != 0} {set offset [expr $offset << 1]} {
- set addr [expr $baseAddress + $offset]
- set data [memread32 $addr]
-
- if {$data != $pattern} {
- echo "FAILED DATA_ADDR_BUS_SHIGH: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data]"
- return $pattern
- }
- }
-
- echo "memTestAddressBus: Checking for address bits stuck low or shorted..."
- memwrite32 $baseAddress $pattern
- for {set testOffset 32} {[expr $testOffset & $addressMask] != 0} {set testOffset [expr $testOffset << 1] } {
- set addr [expr $baseAddress + $testOffset]
- memwrite32 $addr $antipattern
-
- set data [memread32 $baseAddress]
- if {$data != $pattern} {
- echo "FAILED DATA_ADDR_BUS_SLOW: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data]"
- return $pattern
- }
-
- for {set offset 32} {[expr $offset & $addressMask] != 0} {set offset [expr $offset << 1]} {
- set addr [expr $baseAddress + $offset]
- set data [memread32 $baseAddress]
-
- if {(($data != $pattern) && ($offset != $testOffset))} {
- echo "FAILED DATA_ADDR_BUS_SLOW2: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data], offset: [convertToHex $offset], testOffset [convertToHex $testOffset]"
- return $pattern
- }
- }
- set addr [expr $baseAddress + $testOffset]
- memwrite32 $addr $pattern
- }
-}
-
-#***********************************************************************************
-# *
-# * Function: memTestDevice()
-# *
-# * Description: Test the integrity of a physical memory device by
-# * performing an increment/decrement test over the
-# * entire region. In the process every storage bit
-# * in the device is tested as zero and as one. The
-# * base address and the size of the region are
-# * selected by the caller.
-# * Ported from:
-# * http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C
-# * Notes:
-# *
-# * Returns: Empty string if the test succeeds.
-# * A non-zero result is the first address at which an
-# * incorrect value was read back. By examining the
-# * contents of memory, it may be possible to gather
-# * additional information about the problem.
-# *
-#***********************************************************************************
-proc memTestDevice { baseAddress nBytes } {
- echo "Running memTestDevice"
-
- echo "memTestDevice: Filling memory with a known pattern..."
- for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} {
- memwrite32 [expr $baseAddress + $offset] $pattern
- }
-
- echo "memTestDevice: Checking each location and inverting it for the second pass..."
- for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} {
- set addr [expr $baseAddress + $offset]
- set data [memread32 $addr]
-
- if {$data != $pattern} {
- echo "FAILED memTestDevice_pattern: Address: [convertToHex $addr], Pattern: [convertToHex $pattern], Returned: [convertToHex $data], offset: [convertToHex $offset]"
- return $pattern
- }
-
- set antiPattern [expr ~$pattern]
- memwrite32 [expr $baseAddress + $offset] $antiPattern
- }
-
- echo "memTestDevice: Checking each location for the inverted pattern and zeroing it..."
- for {set pattern 1; set offset 0} {$offset < $nBytes} {incr pattern; incr offset 32} {
- set antiPattern [expr ~$pattern & ((1<<32) - 1)]
- set addr [expr $baseAddress + $offset]
- set data [memread32 $addr]
- set dataHex [convertToHex $data]
- set antiPatternHex [convertToHex $antiPattern]
- if {[expr $dataHex != $antiPatternHex]} {
- echo "FAILED memTestDevice_antipattern: Address: [convertToHex $addr], antiPattern: $antiPatternHex, Returned: $dataHex, offset: $offset"
- return $pattern
- }
- }
-}
-
-proc convertToHex { value } {
- format 0x%08x $value
-}
diff --git a/spi_test.cpp b/spi_test.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..4545c8e41a06666301a663da5045025db80814c8
--- /dev/null
+++ b/spi_test.cpp
@@ -0,0 +1,55 @@
+#include <pigpio.h>
+#include <iostream>
+#include <unistd.h>
+
+using namespace std;
+
+uint16_t dataRed[40*24] = {0};
+uint16_t dataGreen[40*24] = {0};
+char dataRed2[40*24*2] = {0};
+char dataGreen2[40*24*2] = {0};
+char ures[40*24*2] = {0};
+
+void initData()
+{
+ for(size_t i = 0; i < 40; i++)
+ {
+ for(size_t j = 0; j < 24; j++)
+ {
+ dataRed[24*i+j] = 0;
+ }
+ dataRed[24*i] = 0x0100;
+ }
+ for(size_t i = 0; i < 40; i++)
+ {
+ for(size_t j = 0; j < 24; j++)
+ {
+ dataGreen[24*i+j] = 0;
+ }
+ dataGreen[24*i+8] = 0x0100;
+ }
+ for(size_t i = 0; i < 40*24; i++)
+ {
+ dataRed2[2*i] = dataRed[i] >> 8;
+ dataRed2[2*i + 1] = dataRed[i];
+ dataGreen2[2*i] = dataGreen[i] >> 8;
+ dataGreen2[2*i + 1] = dataGreen[i];
+ }
+}
+
+int main(int argc, char *argv[])
+{
+ initData();
+ gpioInitialise();
+ int spiHandle = spiOpen(0, 16000000, 0b0100000000000000000000);
+ if(spiHandle >= 0) cout << "SPI Opened" << endl;
+ char buff[2] = {0, 1}; //ez lesz így 0x0001
+ while(1){
+ spiWrite(spiHandle, dataRed2, 40*24*2);
+ usleep(10000);
+ spiWrite(spiHandle, dataGreen2, 40*24*2);
+ usleep(10000);
+ }
+
+ return 0;
+}
diff --git a/startup_stm32f103xb.s b/startup_stm32f103xb.s
deleted file mode 100644
index 3a0a3b97756bbf09cebaf31f9c9a0744e21b4f16..0000000000000000000000000000000000000000
--- a/startup_stm32f103xb.s
+++ /dev/null
@@ -1,379 +0,0 @@
-/**
- *************** (C) COPYRIGHT 2017 STMicroelectronics ************************
- * @file startup_stm32f103xb.s
- * @author MCD Application Team
- * @version V4.2.0
- * @date 31-March-2017
- * @brief STM32F103xB Devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the clock system
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M3 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- *
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m3
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ BootRAM, 0xF108F85F
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2], #4
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
- bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
- .word WWDG_IRQHandler
- .word PVD_IRQHandler
- .word TAMPER_IRQHandler
- .word RTC_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_IRQHandler
- .word EXTI0_IRQHandler
- .word EXTI1_IRQHandler
- .word EXTI2_IRQHandler
- .word EXTI3_IRQHandler
- .word EXTI4_IRQHandler
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_IRQHandler
- .word DMA1_Channel3_IRQHandler
- .word DMA1_Channel4_IRQHandler
- .word DMA1_Channel5_IRQHandler
- .word DMA1_Channel6_IRQHandler
- .word DMA1_Channel7_IRQHandler
- .word ADC1_2_IRQHandler
- .word USB_HP_CAN1_TX_IRQHandler
- .word USB_LP_CAN1_RX0_IRQHandler
- .word CAN1_RX1_IRQHandler
- .word CAN1_SCE_IRQHandler
- .word EXTI9_5_IRQHandler
- .word TIM1_BRK_IRQHandler
- .word TIM1_UP_IRQHandler
- .word TIM1_TRG_COM_IRQHandler
- .word TIM1_CC_IRQHandler
- .word TIM2_IRQHandler
- .word TIM3_IRQHandler
- .word TIM4_IRQHandler
- .word I2C1_EV_IRQHandler
- .word I2C1_ER_IRQHandler
- .word I2C2_EV_IRQHandler
- .word I2C2_ER_IRQHandler
- .word SPI1_IRQHandler
- .word SPI2_IRQHandler
- .word USART1_IRQHandler
- .word USART2_IRQHandler
- .word USART3_IRQHandler
- .word EXTI15_10_IRQHandler
- .word RTC_Alarm_IRQHandler
- .word USBWakeUp_IRQHandler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word BootRAM /* @0x108. This is for boot in RAM mode for
- STM32F10x Medium Density devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak TAMPER_IRQHandler
- .thumb_set TAMPER_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_IRQHandler
- .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
- .weak DMA1_Channel3_IRQHandler
- .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_IRQHandler
- .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
- .weak DMA1_Channel5_IRQHandler
- .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
- .weak DMA1_Channel6_IRQHandler
- .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
- .weak DMA1_Channel7_IRQHandler
- .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
- .weak ADC1_2_IRQHandler
- .thumb_set ADC1_2_IRQHandler,Default_Handler
-
- .weak USB_HP_CAN1_TX_IRQHandler
- .thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler
-
- .weak USB_LP_CAN1_RX0_IRQHandler
- .thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler
-
- .weak CAN1_RX1_IRQHandler
- .thumb_set CAN1_RX1_IRQHandler,Default_Handler
-
- .weak CAN1_SCE_IRQHandler
- .thumb_set CAN1_SCE_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_IRQHandler
- .thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
- .weak TIM1_UP_IRQHandler
- .thumb_set TIM1_UP_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_IRQHandler
- .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
- .thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_IRQHandler
- .thumb_set USART3_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak USBWakeUp_IRQHandler
- .thumb_set USBWakeUp_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-