From 95a20cbf64e83ec752d74c7067fc19727ae354b0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tam=C3=A1si=20Benjamin?= <halftome@yahoo.com> Date: Fri, 17 Oct 2014 13:19:35 +0200 Subject: [PATCH] Tonz of debugging --- cntr.v | 4 ++-- data.v | 2 +- debouncer.v | 10 ++++----- rategen.v | 8 +++---- uartop.v | 63 +++++++++++++++++++++++++++++++++++++---------------- 5 files changed, 54 insertions(+), 33 deletions(-) diff --git a/cntr.v b/cntr.v index 5608338..8235e5c 100644 --- a/cntr.v +++ b/cntr.v @@ -13,7 +13,7 @@ always @ (posedge clk) begin else if(en) begin if(par) begin - if(cntr >= 9) begin + if(cntr >= 10) begin cntr <= 0; end else begin @@ -22,7 +22,7 @@ always @ (posedge clk) begin end else begin - if(cntr >= 8) begin + if(cntr >= 9) begin cntr <= 0; end else begin diff --git a/data.v b/data.v index c82a7eb..d662ab6 100644 --- a/data.v +++ b/data.v @@ -20,7 +20,7 @@ module data( end else if(en) begin - data <= {0, data[41:1]}; // Shift -> LSB + data <= {1'b0, data[41:1]}; // Shift -> LSB end end diff --git a/debouncer.v b/debouncer.v index fd8d0a6..8d28987 100644 --- a/debouncer.v +++ b/debouncer.v @@ -3,20 +3,18 @@ input clk, rst, din, output q ); +reg in; reg state; always @ (posedge clk) begin if(rst) begin + in <= 0; state <= 0; end else begin - if(din) begin - state <= 1; - end - else begin - state <= 0; - end + in <= din; + state <= in; end end diff --git a/rategen.v b/rategen.v index a03b78c..6cbf374 100644 --- a/rategen.v +++ b/rategen.v @@ -1,7 +1,7 @@ // SYSCLK is 50MHz module rategen( input clk, rst, start, sw_speed, sw_par, - output iclk, pulse + output iclk ); reg [15:0] cntr; @@ -19,22 +19,20 @@ module rategen( if(cntr >= 5208) begin cntr <= 0; end + else cntr <= cntr + 1; end else begin // Baud rate at 1200 if(cntr >= 41666) begin cntr <= 0; end + else cntr <= cntr + 1; end - cntr <= cntr + 1; end end assign fast = (cntr >= 5208) ? 1 : 0; // pulse width of clk for SYNC assign slow = (cntr >= 41666) ? 1 : 0; // pulse width of clk for SYNC -assign p_fast = (cntr >= 2704) ? 1 : 0; // pulse width of 50% -assign p_slow = (cntr >= 20833) ? 1 : 0; // pulse width of 50% assign iclk = (sw_speed) ? fast : slow; -assign pulse = (sw_speed) ? p_fast : p_slow; endmodule diff --git a/uartop.v b/uartop.v index 46c1e96..0c16694 100644 --- a/uartop.v +++ b/uartop.v @@ -10,26 +10,39 @@ module uartop( reg outbuf; reg [6:0] datacntr; + reg main_en; wire iclk; // Internal CLK for correct Baud Rate wire starten; // Main enabler wire [3:0] count; - wire mpxen; + wire shiften; wire dout; - wire pulse; - wire parity; + wire w_parity; wire uart_data; wire [15:0] uart_mpx; wire wordend; wire [6:0] data_count; wire eot; // End of transmit + wire dbnc; - assign uart_mpx[15] = 0; // Start bit - assign uart_mpx[14:8] = dout; // UART DATA 7bit - assign uart_mpx[7] = (sw7) ? parity : 1; // Parity or stop bit - assign uart_mpx[6:0] = 1; // Stop bits + assign uart_mpx[0] = 0; // Start bit + assign uart_mpx[1] = dout; // UART DATA 7bit + assign uart_mpx[2] = dout; // UART DATA 7bit + assign uart_mpx[3] = dout; // UART DATA 7bit + assign uart_mpx[4] = dout; // UART DATA 7bit + assign uart_mpx[5] = dout; // UART DATA 7bit + assign uart_mpx[6] = dout; // UART DATA 7bit + assign uart_mpx[7] = dout; // UART DATA 7bit + assign uart_mpx[8] = (sw7) ? w_parity : 1; // Parity or stop bit + assign uart_mpx[9] = 1; // Stop bits + assign uart_mpx[10] = 1; // Stop bits + assign uart_mpx[11] = 1; // Stop bits + assign uart_mpx[12] = 1; // Stop bits + assign uart_mpx[13] = 1; // Stop bits + assign uart_mpx[14] = 1; // Stop bits + assign uart_mpx[15] = 1; // Stop bits - assign mpxen = (count == 0 || (count >= 8 && count <= 10)); + assign shiften = !(count == 0 || (count >= 8 && count <= 10)); rategen rategen( .clk(clk), @@ -37,15 +50,14 @@ module uartop( .start(btn1), .sw_speed(sw6), .sw_par(sw7), - .iclk(iclk), - .pulse(pulse) + .iclk(iclk) ); debouncer debouncer( .clk(clk), .rst(rst), .din(btn1 || eot), - .q(starten) + .q(dbnc) ); cntr cntr( @@ -59,7 +71,7 @@ module uartop( data data( .clk(clk), .rst(rst), - .en(mpxen && iclk && starten), + .en(shiften && iclk && starten), .q(dout) ); @@ -69,7 +81,7 @@ module uartop( .din(dout), .en(iclk), .par(1), // Odd Parity - .q(parity) + .q(w_parity) ); udata udata( @@ -83,19 +95,32 @@ module uartop( always @ (posedge clk) begin if(rst) begin - outbuf <= 0; + outbuf <= 1; datacntr <= 0; + main_en <= 0; end - else if(datacntr == 41 && mpxen) begin + else begin + if(dbnc) main_en <= ~main_en; // T FF + if(datacntr == 41 && shiften && iclk) begin datacntr <= 0; - end - else if(mpxen) begin + end + else if(shiften && iclk) begin datacntr <= datacntr + 1; - end + end + end + + if(starten && iclk) begin + outbuf <= uart_data; + end + end assign data_count = datacntr; -assign wordend = (data_count%6 == 0); +assign wordend = ((data_count%6) == 0); assign eot = (data_count == 42); +assign starten = main_en; + +assign txd = outbuf; +assign rts = starten; endmodule -- GitLab